From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35522) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UtpMK-0002Im-8S for qemu-devel@nongnu.org; Mon, 01 Jul 2013 21:26:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UtpMJ-0005eF-1d for qemu-devel@nongnu.org; Mon, 01 Jul 2013 21:26:20 -0400 Message-ID: <51D22C33.5020005@suse.de> Date: Tue, 02 Jul 2013 03:26:11 +0200 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= MIME-Version: 1.0 References: <1372536117-28167-1-git-send-email-afaerber@suse.de> <1372536117-28167-2-git-send-email-afaerber@suse.de> In-Reply-To: <1372536117-28167-2-git-send-email-afaerber@suse.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH RFC qom-cpu 01/41] log: Change log_cpu_state[_mask]() argument to CPUState List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Michael Walle , Richard Henderson Cc: Peter Maydell , Peter Crosthwaite , Anthony Green , Riku Voipio , qemu-devel@nongnu.org, Alexander Graf , Blue Swirl , qemu-ppc , Paul Brook , "Edgar E. Iglesias" , Jan Kiszka , Aurelien Jarno Am 29.06.2013 22:01, schrieb Andreas F=C3=A4rber: > diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c > index 01d4bbf..86aad6a 100644 > --- a/target-microblaze/helper.c > +++ b/target-microblaze/helper.c > @@ -152,7 +152,7 @@ void mb_cpu_do_interrupt(CPUState *cs) > "hw exception at pc=3D%x ear=3D%x esr=3D%x i= flags=3D%x\n", > env->sregs[SR_PC], env->sregs[SR_EAR], > env->sregs[SR_ESR], env->iflags); > - log_cpu_state_mask(CPU_LOG_INT, env, 0); > + log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), 0); > env->iflags &=3D ~(IMM_FLAG | D_FLAG); > env->sregs[SR_PC] =3D cpu->base_vectors + 0x20; > break; > @@ -175,7 +175,7 @@ void mb_cpu_do_interrupt(CPUState *cs) > "bimm exception at pc=3D%x iflags=3D= %x\n", > env->sregs[SR_PC], env->iflags); > env->regs[17] -=3D 4; > - log_cpu_state_mask(CPU_LOG_INT, env, 0); > + log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), 0); > } > } else if (env->iflags & IMM_FLAG) { > D(qemu_log("IMM_FLAG set at exception\n")); > @@ -192,7 +192,7 @@ void mb_cpu_do_interrupt(CPUState *cs) > qemu_log_mask(CPU_LOG_INT, > "exception at pc=3D%x ear=3D%x iflags=3D%x\n= ", > env->sregs[SR_PC], env->sregs[SR_EAR], env->= iflags); > - log_cpu_state_mask(CPU_LOG_INT, env, 0); > + log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), 0); > env->iflags &=3D ~(IMM_FLAG | D_FLAG); > env->sregs[SR_PC] =3D cpu->base_vectors + 0x20; > break; > @@ -222,7 +222,7 @@ void mb_cpu_do_interrupt(CPUState *cs) > env->sregs[SR_PC], env->sregs[SR_MSR], t, env= ->iflags, > sym); > =20 > - log_cpu_state(env, 0); > + log_cpu_state(CPU(cpu), 0); > } > } > #endif > @@ -236,7 +236,7 @@ void mb_cpu_do_interrupt(CPUState *cs) > =20 > env->regs[14] =3D env->sregs[SR_PC]; > env->sregs[SR_PC] =3D cpu->base_vectors + 0x10; > - //log_cpu_state_mask(CPU_LOG_INT, env, 0); > + //log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), 0); > break; > =20 > case EXCP_BREAK: > @@ -247,7 +247,7 @@ void mb_cpu_do_interrupt(CPUState *cs) > qemu_log_mask(CPU_LOG_INT, > "break at pc=3D%x msr=3D%x %x iflags=3D%x\n", > env->sregs[SR_PC], env->sregs[SR_MSR], t, env-= >iflags); > - log_cpu_state_mask(CPU_LOG_INT, env, 0); > + log_cpu_state_mask(CPU_LOG_INT, CPU(cpu), 0); > env->sregs[SR_MSR] &=3D ~(MSR_VMS | MSR_UMS | MSR_VM | MSR= _UM); > env->sregs[SR_MSR] |=3D t; > env->sregs[SR_MSR] |=3D MSR_BIP; Re-reviewing this patch for my X86CPU changes, I noticed all these could use "cs" rather than "CPU(cpu)" - fixed and applied along with the following one to qom-cpu: https://github.com/afaerber/qemu-cpu/commits/qom-cpu > diff --git a/target-microblaze/translate.c b/target-microblaze/translat= e.c > index 54f439f..f9acdb1 100644 > --- a/target-microblaze/translate.c > +++ b/target-microblaze/translate.c > @@ -1741,6 +1741,9 @@ static void > gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb, > int search_pc) > { > +#if !SIM_COMPAT > + MicroBlazeCPU *cpu =3D mb_env_get_cpu(env); > +#endif > uint16_t *gen_opc_end; > uint32_t pc_start; > int j, lj; [snip] This hunk would benefit from the gen_intermediate_code_internal() argument type change prompted by gdbstub later in this series, so I intend to prepend those once v2 is done - inline is missing here. Trying to avoid resending a 41-patch series. ;) TBD: Follow up with patches for the x86 and ppc logging macros respectively before I forget about them. Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=C3=B6rffer; HRB 16746 AG N=C3=BC= rnberg