From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54952) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V1MXh-0004ue-VM for qemu-devel@nongnu.org; Mon, 22 Jul 2013 16:17:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V1MXf-0007Dx-TD for qemu-devel@nongnu.org; Mon, 22 Jul 2013 16:17:13 -0400 Received: from smtp1-g21.free.fr ([2a01:e0c:1:1599::10]:41885) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V1MXf-0007AX-8q for qemu-devel@nongnu.org; Mon, 22 Jul 2013 16:17:11 -0400 Message-ID: <51ED9334.2010409@reactos.org> Date: Mon, 22 Jul 2013 22:16:52 +0200 From: =?UTF-8?B?SGVydsOpIFBvdXNzaW5lYXU=?= MIME-Version: 1.0 References: <1374501278-31549-1-git-send-email-pbonzini@redhat.com> <51ED4362.8060709@redhat.com> <51ED4AC5.5030501@redhat.com> In-Reply-To: <51ED4AC5.5030501@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 00/28] Memory API for 1.6: fix I/O port endianness mess List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: Peter Maydell , aliguori@us.ibm.com, aik@ozlabs.ru, jan.kiszka@siemens.com, qemu-devel@nongnu.org, agraf@suse.de, aurelien@aurel32.net Paolo Bonzini a =C3=A9crit : > Il 22/07/2013 17:04, Peter Maydell ha scritto: >> On 22 July 2013 15:36, Paolo Bonzini wrote: >>> Il 22/07/2013 16:32, Peter Maydell ha scritto: >>>> In the long term it would be good to identify which boards >>>> were using isa_mmio purely for the benefit of old_portio >>>> (which I think is basically "boards where the CPU has no >>>> concept of port I/O instructions"). >>> All of them. Only i386/x86_64 has I/O space, as far as I know. >> Sounds plausible. I had wondered if our ISA bus infrastructure >> assumed that ISA device IO ports live in the system IO space, >> but it doesn't. >=20 > No, luckily it doesn't, and neither should the PCI-to-ISA bridges as yo= u > found out---they do not after these patches. PReP is an exception, but > I think it could be rewritten to use an IOMMU memory region. PReP PCI I/O area is located at 0x80000000, up to 0xbf7fffff (in main=20 memory space region), while ISA I/O area is at 0x80000000, up to=20 0x8000ffff (size=3D64KB) However, as they are overlapped, some strange things can happen. For example, IBM 40p firmware configures the PCI SCSI bar at 0x20000000=20 (ie 0xa0000000 in main memory), while Linux sets bar to 0x1000 (ie=20 0x80001000 in main memory), ie also in ISA I/O space. I don't know exactly what you mean by an "IOMMU memory region", but how=20 would you modelize it, so that 0x80001000 and 0xa0000000 accesses are=20 redirected to PCI SCSI card, while 0x800003f8 redirects (for example) to=20 an ISA serial port? If you create a new memory region for ISA I/O space, and you redirect=20 all accesses from 0x80000000-0x8000ffff to this new address space,=20 0x80001000 won't work to access the SCSI I/O bar (located in the PCI I/O=20 address space). That's why I think the i82378 device should not create a whole new=20 address space for ISA I/O space, but use the first 64KB of the PCI I/O=20 space. BTW, I've a patch to really cleanup i82378 implementation (47=20 insertions, 175 deletions). Should I send it now, during 1.6 soft freeze? Herv=C3=A9