From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38400) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V1su4-0002Q1-KP for qemu-devel@nongnu.org; Wed, 24 Jul 2013 02:50:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V1su2-0006qG-OS for qemu-devel@nongnu.org; Wed, 24 Jul 2013 02:50:28 -0400 Received: from cantor2.suse.de ([195.135.220.15]:42300 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V1su2-0006pi-CS for qemu-devel@nongnu.org; Wed, 24 Jul 2013 02:50:26 -0400 Message-ID: <51EF7925.1080804@suse.de> Date: Wed, 24 Jul 2013 08:50:13 +0200 From: =?ISO-8859-1?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <20130724060104.GA18072@redhat.com> In-Reply-To: <20130724060104.GA18072@redhat.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] pc: limit 64 bit hole to 2G by default List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: Anthony Liguori , Eduardo Habkost , qemu-devel@nongnu.org, Isaku Yamahata , Alex Williamson , Gerd Hoffmann , Paolo Bonzini , Laszlo Ersek , David Gibson Hi, Am 24.07.2013 08:01, schrieb Michael S. Tsirkin: > It turns out that some 32 bit windows guests crash > if 64 bit PCI hole size is >2G. > Limit it to 2G for piix and q35 by default, > add properties to let management override the hole size. >=20 > Examples: > -global i440FX-pcihost.pci_hole64_size=3D137438953472 >=20 > -global q35-pcihost.pci_hole64_size=3D137438953472 >=20 > Reported-by: Igor Mammedov , > Signed-off-by: Michael S. Tsirkin > --- > hw/i386/pc.c | 35 ++++++++++++++++++++--------------- > hw/i386/pc_piix.c | 14 +------------- > hw/pci-host/piix.c | 42 ++++++++++++++++++++++++++++++++++-----= --- > hw/pci-host/q35.c | 29 +++++++++++++++++------------ > include/hw/i386/pc.h | 7 +++++-- > include/hw/pci-host/q35.h | 1 + > 6 files changed, 78 insertions(+), 50 deletions(-) [...] > diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c > index 7fb2fb1..963b3d8 100644 > --- a/hw/pci-host/piix.c > +++ b/hw/pci-host/piix.c > @@ -40,6 +41,7 @@ > =20 > typedef struct I440FXState { > PCIHostState parent_obj; > + uint64_t pci_hole64_size; > } I440FXState; > =20 > #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ > @@ -234,9 +236,9 @@ static PCIBus *i440fx_common_init(const char *devic= e_name, > hwaddr pci_hole_start, > hwaddr pci_hole_size, > hwaddr pci_hole64_start, > - hwaddr pci_hole64_size, > MemoryRegion *pci_address_space, > - MemoryRegion *ram_memory) > + MemoryRegion *ram_memory, > + PcGuestInfo *guest_info) > { > DeviceState *dev; > PCIBus *b; > @@ -245,15 +247,31 @@ static PCIBus *i440fx_common_init(const char *dev= ice_name, > PIIX3State *piix3; > PCII440FXState *f; > unsigned i; > + I440FXState *i440fx; > =20 > dev =3D qdev_create(NULL, "i440FX-pcihost"); > s =3D PCI_HOST_BRIDGE(dev); > + i440fx =3D OBJECT_CHECK(I440FXState, dev, "i440FX-pcihost"); If we're lacking a macro for this, please define one. E.g.: #define TYPE_I440FX "i440FX-pcihost" #define I440FX(obj) OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX) above I440FXState. i440fx =3D I440FX(dev); So far was unused due to PCI_HOST_BRIDGE(), I guess. > b =3D pci_bus_new(dev, NULL, pci_address_space, > address_space_io, 0, TYPE_PCI_BUS); > s->bus =3D b; > object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev= ), NULL); > qdev_init_nofail(dev); > =20 > + if (guest_info) { > + /* Set PCI window size the way seabios has always done it. */ > + /* Power of 2 so bios can cover it with a single MTRR */ > + if (ram_size <=3D 0x80000000) > + guest_info->pci_info.w32.begin =3D 0x80000000; > + else if (ram_size <=3D 0xc0000000) > + guest_info->pci_info.w32.begin =3D 0xc0000000; > + else > + guest_info->pci_info.w32.begin =3D 0xe0000000; > + > + pc_init_pci_info(&guest_info->pci_info, > + pci_hole64_start, i440fx->pci_hole64_size); > + } > + > d =3D pci_create_simple(b, 0, device_name); > *pi440fx_state =3D I440FX_PCI_DEVICE(d); > f =3D *pi440fx_state; > @@ -265,8 +283,8 @@ static PCIBus *i440fx_common_init(const char *devic= e_name, > memory_region_add_subregion(f->system_memory, pci_hole_start, &f->= pci_hole); > memory_region_init_alias(&f->pci_hole_64bit, OBJECT(d), "pci-hole6= 4", > f->pci_address_space, > - pci_hole64_start, pci_hole64_size); > - if (pci_hole64_size) { > + pci_hole64_start, i440fx->pci_hole64_size= ); > + if (i440fx->pci_hole64_size) { > memory_region_add_subregion(f->system_memory, pci_hole64_start= , > &f->pci_hole_64bit); > } > @@ -322,8 +340,8 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,= int *piix3_devfn, > hwaddr pci_hole_start, > hwaddr pci_hole_size, > hwaddr pci_hole64_start, > - hwaddr pci_hole64_size, > - MemoryRegion *pci_memory, MemoryRegion *ram_memory= ) > + MemoryRegion *pci_memory, MemoryRegion *ram_memory= , > + PcGuestInfo *guest_info) > =20 > { > PCIBus *b; > @@ -332,8 +350,9 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,= int *piix3_devfn, > piix3_devfn, isa_bus, pic, > address_space_mem, address_space_io, ram_si= ze, > pci_hole_start, pci_hole_size, > - pci_hole64_start, pci_hole64_size, > - pci_memory, ram_memory); > + pci_hole64_start, > + pci_memory, ram_memory, > + guest_info); > return b; > } > =20 > @@ -645,6 +664,12 @@ static const char *i440fx_pcihost_root_bus_path(PC= IHostState *host_bridge, > return "0000"; > } > =20 > +static Property i440fx_props[] =3D { > + DEFINE_PROP_UINT64("pci_hole64_size", I440FXState, "pci-hole64-size"? Same for q35. > + pci_hole64_size, 0x1ULL << 31), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > static void i440fx_pcihost_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc =3D DEVICE_CLASS(klass); > @@ -655,6 +680,7 @@ static void i440fx_pcihost_class_init(ObjectClass *= klass, void *data) > k->init =3D i440fx_pcihost_initfn; > dc->fw_name =3D "pci"; > dc->no_user =3D 1; > + dc->props =3D i440fx_props; > } > =20 > static const TypeInfo i440fx_pcihost_info =3D { > diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c > index c761a43..4dd7ca4 100644 > --- a/hw/pci-host/q35.c > +++ b/hw/pci-host/q35.c > @@ -73,6 +74,8 @@ static const char *q35_host_root_bus_path(PCIHostStat= e *host_bridge, > static Property mch_props[] =3D { > DEFINE_PROP_UINT64("MCFG", Q35PCIHost, host.base_addr, > MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), > + DEFINE_PROP_UINT64("pci_hole64_size", Q35PCIHost, > + mch.pci_hole64_size, 0x1ULL << 31), > DEFINE_PROP_END_OF_LIST(), > }; > =20 [snip] Do we need compat_props for pc-*-0.15 and earlier? Regards, Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg