From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57202) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V2sVu-0005Mv-IB for qemu-devel@nongnu.org; Fri, 26 Jul 2013 20:37:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V2sVs-0000ns-L9 for qemu-devel@nongnu.org; Fri, 26 Jul 2013 20:37:38 -0400 Message-ID: <51F31648.3090003@suse.de> Date: Sat, 27 Jul 2013 02:37:28 +0200 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= MIME-Version: 1.0 References: <1374532568-28051-1-git-send-email-afaerber@suse.de> <1374532568-28051-2-git-send-email-afaerber@suse.de> In-Reply-To: <1374532568-28051-2-git-send-email-afaerber@suse.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH qom-next v2 1/4] pci-bridge: Turn PCIBridge into abstract QOM type List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, Paolo Bonzini Cc: qemu-ppc , Alexander Graf , Don Koch , "Michael S. Tsirkin" Am 23.07.2013 00:36, schrieb Andreas F=C3=A4rber: > Introduce TYPE_PCI_BRIDGE as base type and use PCI_BRIDGE() casts. >=20 > Signed-off-by: Andreas F=C3=A4rber > --- > hw/pci-bridge/dec.c | 4 ++-- > hw/pci-bridge/i82801b11.c | 6 +++--- > hw/pci-bridge/ioh3420.c | 18 ++++++++--------- > hw/pci-bridge/pci_bridge_dev.c | 10 +++++----- > hw/pci-bridge/xio3130_downstream.c | 18 ++++++++--------- > hw/pci-bridge/xio3130_upstream.c | 19 +++++++++--------- > hw/pci-host/apb.c | 4 ++-- > hw/pci/pci.c | 2 +- > hw/pci/pci_bridge.c | 40 +++++++++++++++++++++++++++---= -------- > hw/pci/pcie.c | 2 +- > include/hw/pci/pci_bus.h | 7 ++++++- > 11 files changed, 77 insertions(+), 53 deletions(-) >=20 > diff --git a/hw/pci-bridge/dec.c b/hw/pci-bridge/dec.c > index efc07c4..e5e3be8 100644 > --- a/hw/pci-bridge/dec.c > +++ b/hw/pci-bridge/dec.c > @@ -74,7 +74,7 @@ static void dec_21154_pci_bridge_class_init(ObjectCla= ss *klass, void *data) > =20 > static const TypeInfo dec_21154_pci_bridge_info =3D { > .name =3D "dec-21154-p2p-bridge", > - .parent =3D TYPE_PCI_DEVICE, > + .parent =3D TYPE_PCI_BRIDGE, > .instance_size =3D sizeof(PCIBridge), > .class_init =3D dec_21154_pci_bridge_class_init, > }; > @@ -86,7 +86,7 @@ PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int de= vfn) > =20 > dev =3D pci_create_multifunction(parent_bus, devfn, false, > "dec-21154-p2p-bridge"); > - br =3D DO_UPCAST(PCIBridge, dev, dev); > + br =3D PCI_BRIDGE(dev); > pci_bridge_map_irq(br, "DEC 21154 PCI-PCI bridge", dec_map_irq); > qdev_init_nofail(&dev->qdev); > return pci_bridge_get_sec_bus(br); > diff --git a/hw/pci-bridge/i82801b11.c b/hw/pci-bridge/i82801b11.c > index b98bfb0..88f489a 100644 > --- a/hw/pci-bridge/i82801b11.c > +++ b/hw/pci-bridge/i82801b11.c > @@ -91,7 +91,7 @@ static void i82801b11_bridge_class_init(ObjectClass *= klass, void *data) > =20 > static const TypeInfo i82801b11_bridge_info =3D { > .name =3D "i82801b11-bridge", > - .parent =3D TYPE_PCI_DEVICE, > + .parent =3D TYPE_PCI_BRIDGE, > .instance_size =3D sizeof(I82801b11Bridge), > .class_init =3D i82801b11_bridge_class_init, > }; > @@ -107,8 +107,8 @@ PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int= sec_bus) > if (!d) { > return NULL; > } > - br =3D DO_UPCAST(PCIBridge, dev, d); > - qdev =3D &br->dev.qdev; > + br =3D PCI_BRIDGE(d); > + qdev =3D DEVICE(d); > =20 > snprintf(buf, sizeof(buf), "pci.%d", sec_bus); > pci_bridge_map_irq(br, buf, pci_swizzle_map_irq_fn); > diff --git a/hw/pci-bridge/ioh3420.c b/hw/pci-bridge/ioh3420.c > index bb541eb..728f658 100644 > --- a/hw/pci-bridge/ioh3420.c > +++ b/hw/pci-bridge/ioh3420.c > @@ -92,7 +92,7 @@ static void ioh3420_reset(DeviceState *qdev) > =20 > static int ioh3420_initfn(PCIDevice *d) > { > - PCIBridge* br =3D DO_UPCAST(PCIBridge, dev, d); > + PCIBridge *br =3D PCI_BRIDGE(d); > PCIEPort *p =3D DO_UPCAST(PCIEPort, br, br); > PCIESlot *s =3D DO_UPCAST(PCIESlot, port, p); > int rc; > @@ -148,7 +148,7 @@ err_bridge: > =20 > static void ioh3420_exitfn(PCIDevice *d) > { > - PCIBridge* br =3D DO_UPCAST(PCIBridge, dev, d); > + PCIBridge *br =3D PCI_BRIDGE(d); > PCIEPort *p =3D DO_UPCAST(PCIEPort, br, br); > PCIESlot *s =3D DO_UPCAST(PCIESlot, port, p); > =20 > @@ -171,9 +171,9 @@ PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool= multifunction, > if (!d) { > return NULL; > } > - br =3D DO_UPCAST(PCIBridge, dev, d); > + br =3D PCI_BRIDGE(d); > =20 > - qdev =3D &br->dev.qdev; > + qdev =3D DEVICE(d); > pci_bridge_map_irq(br, bus_name, map_irq); > qdev_prop_set_uint8(qdev, "port", port); > qdev_prop_set_uint8(qdev, "chassis", chassis); > @@ -190,8 +190,8 @@ static const VMStateDescription vmstate_ioh3420 =3D= { > .minimum_version_id_old =3D 1, > .post_load =3D pcie_cap_slot_post_load, > .fields =3D (VMStateField[]) { > - VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot), > - VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0, > + VMSTATE_PCIE_DEVICE(port.br.parent_obj, PCIESlot), > + VMSTATE_STRUCT(port.br.parent_obj.exp.aer_log, PCIESlot, 0, > vmstate_pcie_aer_log, PCIEAERLog), > VMSTATE_END_OF_LIST() > } > @@ -202,8 +202,8 @@ static Property ioh3420_properties[] =3D { > DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), > DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), > DEFINE_PROP_UINT16("aer_log_max", PCIESlot, > - port.br.dev.exp.aer_log.log_max, > - PCIE_AER_LOG_MAX_DEFAULT), > + port.br.parent_obj.exp.aer_log.log_max, > + PCIE_AER_LOG_MAX_DEFAULT), > DEFINE_PROP_END_OF_LIST(), > }; > =20 > @@ -228,7 +228,7 @@ static void ioh3420_class_init(ObjectClass *klass, = void *data) > =20 > static const TypeInfo ioh3420_info =3D { > .name =3D "ioh3420", > - .parent =3D TYPE_PCI_DEVICE, > + .parent =3D TYPE_PCI_BRIDGE, > .instance_size =3D sizeof(PCIESlot), > .class_init =3D ioh3420_class_init, > }; > diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_= dev.c > index 5f11323..00d2382 100644 > --- a/hw/pci-bridge/pci_bridge_dev.c > +++ b/hw/pci-bridge/pci_bridge_dev.c > @@ -38,7 +38,7 @@ typedef struct PCIBridgeDev PCIBridgeDev; > =20 > static int pci_bridge_dev_initfn(PCIDevice *dev) > { > - PCIBridge *br =3D DO_UPCAST(PCIBridge, dev, dev); > + PCIBridge *br =3D PCI_BRIDGE(dev); > PCIBridgeDev *bridge_dev =3D DO_UPCAST(PCIBridgeDev, bridge, br); > int err; > =20 > @@ -81,7 +81,7 @@ bridge_error: > =20 > static void pci_bridge_dev_exitfn(PCIDevice *dev) > { > - PCIBridge *br =3D DO_UPCAST(PCIBridge, dev, dev); > + PCIBridge *br =3D PCI_BRIDGE(dev); > PCIBridgeDev *bridge_dev =3D DO_UPCAST(PCIBridgeDev, bridge, br); > if (msi_present(dev)) { > msi_uninit(dev); > @@ -120,8 +120,8 @@ static Property pci_bridge_dev_properties[] =3D { > static const VMStateDescription pci_bridge_dev_vmstate =3D { > .name =3D "pci_bridge", > .fields =3D (VMStateField[]) { > - VMSTATE_PCI_DEVICE(bridge.dev, PCIBridgeDev), > - SHPC_VMSTATE(bridge.dev.shpc, PCIBridgeDev), > + VMSTATE_PCI_DEVICE(bridge.parent_obj, PCIBridgeDev), > + SHPC_VMSTATE(bridge.parent_obj.shpc, PCIBridgeDev), > VMSTATE_END_OF_LIST() > } > }; > @@ -145,7 +145,7 @@ static void pci_bridge_dev_class_init(ObjectClass *= klass, void *data) > =20 > static const TypeInfo pci_bridge_dev_info =3D { > .name =3D "pci-bridge", > - .parent =3D TYPE_PCI_DEVICE, > + .parent =3D TYPE_PCI_BRIDGE, > .instance_size =3D sizeof(PCIBridgeDev), > .class_init =3D pci_bridge_dev_class_init, > }; > diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130= _downstream.c > index 1810dd2..9acce3f 100644 > --- a/hw/pci-bridge/xio3130_downstream.c > +++ b/hw/pci-bridge/xio3130_downstream.c > @@ -56,7 +56,7 @@ static void xio3130_downstream_reset(DeviceState *qde= v) > =20 > static int xio3130_downstream_initfn(PCIDevice *d) > { > - PCIBridge* br =3D DO_UPCAST(PCIBridge, dev, d); > + PCIBridge *br =3D PCI_BRIDGE(d); > PCIEPort *p =3D DO_UPCAST(PCIEPort, br, br); > PCIESlot *s =3D DO_UPCAST(PCIESlot, port, p); > int rc; > @@ -113,7 +113,7 @@ err_bridge: > =20 > static void xio3130_downstream_exitfn(PCIDevice *d) > { > - PCIBridge* br =3D DO_UPCAST(PCIBridge, dev, d); > + PCIBridge *br =3D PCI_BRIDGE(d); > PCIEPort *p =3D DO_UPCAST(PCIEPort, br, br); > PCIESlot *s =3D DO_UPCAST(PCIESlot, port, p); > =20 > @@ -138,9 +138,9 @@ PCIESlot *xio3130_downstream_init(PCIBus *bus, int = devfn, bool multifunction, > if (!d) { > return NULL; > } > - br =3D DO_UPCAST(PCIBridge, dev, d); > + br =3D PCI_BRIDGE(d); > =20 > - qdev =3D &br->dev.qdev; > + qdev =3D DEVICE(d); > pci_bridge_map_irq(br, bus_name, map_irq); > qdev_prop_set_uint8(qdev, "port", port); > qdev_prop_set_uint8(qdev, "chassis", chassis); > @@ -157,8 +157,8 @@ static const VMStateDescription vmstate_xio3130_dow= nstream =3D { > .minimum_version_id_old =3D 1, > .post_load =3D pcie_cap_slot_post_load, > .fields =3D (VMStateField[]) { > - VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot), > - VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0, > + VMSTATE_PCIE_DEVICE(port.br.parent_obj, PCIESlot), > + VMSTATE_STRUCT(port.br.parent_obj.exp.aer_log, PCIESlot, 0, > vmstate_pcie_aer_log, PCIEAERLog), > VMSTATE_END_OF_LIST() > } > @@ -169,8 +169,8 @@ static Property xio3130_downstream_properties[] =3D= { > DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), > DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), > DEFINE_PROP_UINT16("aer_log_max", PCIESlot, > - port.br.dev.exp.aer_log.log_max, > - PCIE_AER_LOG_MAX_DEFAULT), > + port.br.parent_obj.exp.aer_log.log_max, > + PCIE_AER_LOG_MAX_DEFAULT), > DEFINE_PROP_END_OF_LIST(), > }; > =20 > @@ -195,7 +195,7 @@ static void xio3130_downstream_class_init(ObjectCla= ss *klass, void *data) > =20 > static const TypeInfo xio3130_downstream_info =3D { > .name =3D "xio3130-downstream", > - .parent =3D TYPE_PCI_DEVICE, > + .parent =3D TYPE_PCI_BRIDGE, > .instance_size =3D sizeof(PCIESlot), > .class_init =3D xio3130_downstream_class_init, > }; > diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_u= pstream.c > index 8e0d97a..0bc1d05 100644 > --- a/hw/pci-bridge/xio3130_upstream.c > +++ b/hw/pci-bridge/xio3130_upstream.c > @@ -53,7 +53,7 @@ static void xio3130_upstream_reset(DeviceState *qdev) > =20 > static int xio3130_upstream_initfn(PCIDevice *d) > { > - PCIBridge* br =3D DO_UPCAST(PCIBridge, dev, d); > + PCIBridge *br =3D PCI_BRIDGE(d); > PCIEPort *p =3D DO_UPCAST(PCIEPort, br, br); > int rc; > =20 > @@ -118,9 +118,9 @@ PCIEPort *xio3130_upstream_init(PCIBus *bus, int de= vfn, bool multifunction, > if (!d) { > return NULL; > } > - br =3D DO_UPCAST(PCIBridge, dev, d); > + br =3D PCI_BRIDGE(d); > =20 > - qdev =3D &br->dev.qdev; > + qdev =3D DEVICE(d); > pci_bridge_map_irq(br, bus_name, map_irq); > qdev_prop_set_uint8(qdev, "port", port); > qdev_init_nofail(qdev); > @@ -134,17 +134,18 @@ static const VMStateDescription vmstate_xio3130_u= pstream =3D { > .minimum_version_id =3D 1, > .minimum_version_id_old =3D 1, > .fields =3D (VMStateField[]) { > - VMSTATE_PCIE_DEVICE(br.dev, PCIEPort), > - VMSTATE_STRUCT(br.dev.exp.aer_log, PCIEPort, 0, vmstate_pcie_a= er_log, > - PCIEAERLog), > + VMSTATE_PCIE_DEVICE(br.parent_obj, PCIEPort), > + VMSTATE_STRUCT(br.parent_obj.exp.aer_log, PCIEPort, 0, > + vmstate_pcie_aer_log, PCIEAERLog), > VMSTATE_END_OF_LIST() > } > }; > =20 > static Property xio3130_upstream_properties[] =3D { > DEFINE_PROP_UINT8("port", PCIEPort, port, 0), > - DEFINE_PROP_UINT16("aer_log_max", PCIEPort, br.dev.exp.aer_log.log= _max, > - PCIE_AER_LOG_MAX_DEFAULT), > + DEFINE_PROP_UINT16("aer_log_max", PCIEPort, > + br.parent_obj.exp.aer_log.log_max, > + PCIE_AER_LOG_MAX_DEFAULT), > DEFINE_PROP_END_OF_LIST(), > }; > =20 > @@ -169,7 +170,7 @@ static void xio3130_upstream_class_init(ObjectClass= *klass, void *data) > =20 > static const TypeInfo xio3130_upstream_info =3D { > .name =3D "x3130-upstream", > - .parent =3D TYPE_PCI_DEVICE, > + .parent =3D TYPE_PCI_BRIDGE, > .instance_size =3D sizeof(PCIEPort), > .class_init =3D xio3130_upstream_class_init, > }; > diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c > index 06ace08..0277aa0 100644 > --- a/hw/pci-host/apb.c > +++ b/hw/pci-host/apb.c > @@ -464,7 +464,7 @@ PCIBus *pci_apb_init(hwaddr special_base, > /* APB secondary busses */ > pci_dev =3D pci_create_multifunction(d->bus, PCI_DEVFN(1, 0), true= , > "pbm-bridge"); > - br =3D DO_UPCAST(PCIBridge, dev, pci_dev); > + br =3D PCI_BRIDGE(pci_dev); > pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 1", > pci_apb_map_irq); > qdev_init_nofail(&pci_dev->qdev); > @@ -472,7 +472,7 @@ PCIBus *pci_apb_init(hwaddr special_base, > =20 > pci_dev =3D pci_create_multifunction(d->bus, PCI_DEVFN(1, 1), true= , > "pbm-bridge"); > - br =3D DO_UPCAST(PCIBridge, dev, pci_dev); > + br =3D PCI_BRIDGE(pci_dev); > pci_bridge_map_irq(br, "Advanced PCI Bus secondary bridge 2", > pci_apb_map_irq); > qdev_init_nofail(&pci_dev->qdev); This needs the following fixup. Thanks to Paolo for adding and enabling sparc64 qtests that uncovered this. Andreas diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 1e80556..870b05b 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -564,8 +564,7 @@ static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data) static const TypeInfo pbm_pci_bridge_info =3D { .name =3D "pbm-bridge", - .parent =3D TYPE_PCI_DEVICE, - .instance_size =3D sizeof(PCIBridge), + .parent =3D TYPE_PCI_BRIDGE, .class_init =3D pbm_pci_bridge_class_init, }; --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=C3=B6rffer; HRB 16746 AG N=C3=BC= rnberg