From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48975) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V3F02-0005Qs-4n for qemu-devel@nongnu.org; Sat, 27 Jul 2013 20:38:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V3Ezu-0001Ma-PB for qemu-devel@nongnu.org; Sat, 27 Jul 2013 20:38:14 -0400 Received: from cantor2.suse.de ([195.135.220.15]:48558 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V3Ezu-0001MO-Fi for qemu-devel@nongnu.org; Sat, 27 Jul 2013 20:38:06 -0400 Message-ID: <51F467E7.1010605@suse.de> Date: Sun, 28 Jul 2013 02:37:59 +0200 From: =?ISO-8859-1?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1374681580-17439-1-git-send-email-mst@redhat.com> <1374681580-17439-11-git-send-email-mst@redhat.com> In-Reply-To: <1374681580-17439-11-git-send-email-mst@redhat.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v3 10/14] ich9: APIs for pc guest info List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: qemu-devel@nongnu.org, Anthony Liguori , Gerd Hoffmann Am 24.07.2013 18:02, schrieb Michael S. Tsirkin: > This adds APIs that will be used to fill in > guest info table, implemented using QOM, > to various ich9 components. >=20 > Signed-off-by: Michael S. Tsirkin > --- > hw/acpi/ich9.c | 6 ++++++ > hw/isa/lpc_ich9.c | 19 +++++++++++++++++++ > hw/pci-host/q35.c | 10 ++++++++++ > include/hw/acpi/ich9.h | 2 ++ > include/hw/i386/ich9.h | 3 +++ > include/hw/pci-host/q35.h | 2 ++ > 6 files changed, 42 insertions(+) >=20 > diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c > index 3fb443d..7ea55e1 100644 > --- a/hw/acpi/ich9.c > +++ b/hw/acpi/ich9.c > @@ -228,3 +228,9 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs= *pm, > pm->powerdown_notifier.notify =3D pm_powerdown_req; > qemu_register_powerdown_notifier(&pm->powerdown_notifier); > } > + > +void ich9_pm_get_acpi_pm_info(ICH9LPCPMRegs *pm, AcpiPmInfo *info) > +{ > + info->gpe0_blk =3D PC_GUEST_PORT_ACPI_PM_BASE + ICH9_PMIO_GPE0_STS= ; > + info->gpe0_blk_len =3D ICH9_PMIO_GPE0_LEN; > +} > diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c > index d1921aa..12d4a23 100644 > --- a/hw/isa/lpc_ich9.c > +++ b/hw/isa/lpc_ich9.c > @@ -562,6 +562,25 @@ static bool ich9_rst_cnt_needed(void *opaque) > return (lpc->rst_cnt !=3D 0); > } > =20 > +ICH9LPCState *ich9_lpc_find(void) > +{ > + bool ambig; > + Object *o =3D object_resolve_path_type("", TYPE_ICH9_LPC_DEVICE, &= ambig); > + > + if (ambig) { > + return NULL; > + } > + return ICH9_LPC_DEVICE(o); > +} > + > +void ich9_lpc_get_acpi_pm_info(ICH9LPCState *lpc, AcpiPmInfo *info) > +{ > + info->sci_int =3D 9; Magic value. > + info->acpi_enable_cmd =3D ICH9_APM_ACPI_ENABLE; > + info->acpi_disable_cmd =3D ICH9_APM_ACPI_DISABLE; > + ich9_pm_get_acpi_pm_info(&lpc->pm, info); > +} > + > static const VMStateDescription vmstate_ich9_rst_cnt =3D { > .name =3D "ICH9LPC/rst_cnt", > .version_id =3D 1, > diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c > index 6b1b3b7..ca6f495 100644 > --- a/hw/pci-host/q35.c > +++ b/hw/pci-host/q35.c > @@ -298,6 +298,16 @@ static int mch_init(PCIDevice *d) > return 0; > } > =20 > +uint64_t mch_mcfg_base(void) > +{ > + bool ambiguous; > + Object *o =3D object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &a= mbiguous); If you take the minute to add in q35 machine init object_property_add_child(qdev_get_machine(), "q35", foo, NULL); then not only can you use object_resolve_path("/machine/q35/mch") to access it but everyone including qtest can. > + if (!o) { > + return 0; > + } > + return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; Another value constant for the device. Taking a wild guess: Is this an offset of a memory subregion where long-term Anthony's proposed MemoryRegion QOM'ification would allow us to get rid of this helper? Anyway, I would like it much better as: uint64_t mch_mcfg_base() { return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; } with the path resolution stuff, i.e. check for necessity, happening in ACPI code, if we don't get around these helpers for now. Andreas > +} > + > static void mch_class_init(ObjectClass *klass, void *data) > { > PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); > diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h > index b1fe71f..f5e8a88 100644 > --- a/include/hw/acpi/ich9.h > +++ b/include/hw/acpi/ich9.h > @@ -49,4 +49,6 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *= pm, > void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base); > extern const VMStateDescription vmstate_ich9_pm; > =20 > +void ich9_pm_get_acpi_pm_info(ICH9LPCPMRegs *, AcpiPmInfo *); > + > #endif /* HW_ACPI_ICH9_H */ > diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h > index c5f637b..6528dc0 100644 > --- a/include/hw/i386/ich9.h > +++ b/include/hw/i386/ich9.h > @@ -66,6 +66,9 @@ typedef struct ICH9LPCState { > qemu_irq *ioapic; > } ICH9LPCState; > =20 > +ICH9LPCState *ich9_lpc_find(void); > +void ich9_lpc_get_acpi_pm_info(ICH9LPCState *, AcpiPmInfo *); > + > #define Q35_MASK(bit, ms_bit, ls_bit) \ > ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) -= 1))) > =20 > diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h > index 3cb631e..6337dcf 100644 > --- a/include/hw/pci-host/q35.h > +++ b/include/hw/pci-host/q35.h > @@ -154,4 +154,6 @@ typedef struct Q35PCIHost { > #define MCH_PCIE_DEV 1 > #define MCH_PCIE_FUNC 0 > =20 > +uint64_t mch_mcfg_base(void); > + > #endif /* HW_Q35_H */ >=20 --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg