From: "Andreas Färber" <afaerber@suse.de>
To: Peter Maydell <peter.maydell@linaro.org>,
Peter Chubb <peter.chubb@nicta.com.au>
Cc: Jan Kiszka <jan.kiszka@siemens.com>, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [Patch] ARM: Add an L2 cache controller to KZM
Date: Mon, 05 Aug 2013 11:24:55 +0200 [thread overview]
Message-ID: <51FF6F67.8070101@suse.de> (raw)
In-Reply-To: <CAFEAcA9U=5RF7F==62c_9e9WEMhzq7t941ZqR79VrTbsaYBtxw@mail.gmail.com>
Am 05.08.2013 11:18, schrieb Peter Maydell:
> On 5 August 2013 02:21, Peter Chubb <peter.chubb@nicta.com.au> wrote:
>> Reads to unassigned memory now return non-zero (since patch
>> 9b8c69243585). This breaks guests runnong on i.MX31 that use the
>> cache controller --- they poll forever waiting for the L2CC cache
>> invalidate regsiter to be zero.
>
> That commit claims it was just restoring the previous
> behaviour, so it shouldn't break guests, surely?
See Jan's patches on the list. PReP was reported affected, too.
Peter Ch., if you know the exact differences, why don't you just derive
an imx-l2cc type (or so) derived from ARM's type, overriding the values
mentioned above? Sounds trivial to me.
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
next prev parent reply other threads:[~2013-08-05 9:25 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-05 1:21 [Qemu-devel] [Patch] ARM: Add an L2 cache controller to KZM Peter Chubb
2013-08-05 9:18 ` Peter Maydell
2013-08-05 9:24 ` Andreas Färber [this message]
2013-08-06 0:00 ` peter
2013-08-06 8:27 ` Andreas Färber
2013-08-07 2:21 ` Peter Chubb
2013-08-06 0:53 ` Peter Chubb
2013-08-05 23:31 ` Peter Chubb
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