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From: Philipp Kern <phil@philkern.de>
To: Richard Henderson <rth@twiddle.net>
Cc: Alexander Graf <agraf@suse.de>,
	Aurelien Jarno <aurelien@aurel32.net>,
	qemu-devel@nongnu.org, Richard Henderson <rth7680@gmail.com>
Subject: Re: [Qemu-devel] [PATCH] target-s390x: Mask the SIGP order_code to 8bit.
Date: Tue, 25 Apr 2017 13:21:42 +0200	[thread overview]
Message-ID: <51aa9f42dd0bb04e36dd67b02b226287@mail.kern.pm> (raw)
In-Reply-To: <70dad7b4-f893-1af7-d0c9-7dbb10506b04@twiddle.net>

On 2017-04-25 11:51, Richard Henderson wrote:
> On 04/24/2017 10:25 AM, Alexander Graf wrote:
>> On 24.04.17 00:32, Aurelien Jarno wrote:
>>> From: Philipp Kern <phil@philkern.de>
>>> 
>>> According to "CPU Signaling and Response", "Signal-Processor Orders",
>>> the order field is bit position 56-63. Without this, the Linux
>>> guest kernel is sometimes unable to stop emulation and enters
>>> an infinite loop of "XXX unknown sigp: 0xffffffff00000005".
>>> 
>>> Signed-off-by: Philipp Kern <phil@philkern.de>
>>> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
>>> ---
>>>  target/s390x/misc_helper.c | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>> 
>>> This patch has been sent by Philipp Kern a lot of time ago, and it 
>>> seems
>>> has been lost. I am resending it, as it is still useful.
>>> 
>>> diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c
>>> index 3bf09ea222..4946b56ab3 100644
>>> --- a/target/s390x/misc_helper.c
>>> +++ b/target/s390x/misc_helper.c
>>> @@ -534,7 +534,7 @@ uint32_t HELPER(sigp)(CPUS390XState *env, 
>>> uint64_t order_code, uint32_t r1,
>>>      /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered 
>>> register"
>>>         as parameter (input). Status (output) is always R1. */
>>> 
>>> -    switch (order_code) {
>>> +    switch (order_code & 0xff) {
>> 
>> This definitely needs a comment above the mask. Ideally I'd love to 
>> just change the function prototype to pass order_code as uint8_t, but 
>> I don't think that's possible with the TCG glue.
> 
> Correct.  We'll need to leave the mask here.

I shall point out that Alexander merged it into the s390-next tree when 
I first sent it but that was never merged into qemu proper. I don't 
think there's a problem in adding a comment that says what the commit 
description says right there, like this:

/* sigp contains the order code in bit positions 56-63, mask it here. */

Kind regards
Philipp Kern

  reply	other threads:[~2017-04-25 11:22 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-23 22:32 [Qemu-devel] [PATCH] target-s390x: Mask the SIGP order_code to 8bit Aurelien Jarno
2017-04-24  8:25 ` Alexander Graf
2017-04-25  9:51   ` Richard Henderson
2017-04-25 11:21     ` Philipp Kern [this message]
2017-04-25 11:32       ` Alexander Graf
     [not found] <1439897731-3645-1-git-send-email-phil@philkern.de>
2015-08-18 11:50 ` Philipp Kern
2015-08-20 17:16   ` Thomas Huth
2015-08-26  9:18     ` Alexander Graf
2016-05-29 14:10       ` Philipp Kern

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