From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Richard Henderson <richard.henderson@linaro.org>,
Gavin Shan <gshan@redhat.com>
Cc: qemu-devel@nongnu.org, Max Filippov <jcmvbkbc@gmail.com>
Subject: Re: [PATCH v5 21/31] target/xtensa: Use generic cpu_list()
Date: Thu, 16 Nov 2023 14:29:54 +0100 [thread overview]
Message-ID: <51ffd060-b2f8-405c-83e1-a0663c0183f5@linaro.org> (raw)
In-Reply-To: <4d12bbdb-8f6b-4fa0-8939-da3d7ae49467@linaro.org>
On 15/11/23 02:12, Richard Henderson wrote:
> On 11/14/23 15:56, Gavin Shan wrote:
>> Before it's applied:
>>
>> [gshan@gshan q]$ ./build/qemu-system-xtensa -cpu ?
>> Available CPUs:
>> test_mmuhifi_c3
>> sample_controller
>> lx106
>> dsp3400
>> de233_fpu
>> de212
>> dc233c
>> dc232b
>>
>> After it's applied:
>>
>> [gshan@gshan q]$ ./build/qemu-system-xtensa -cpu ?
>> Available CPUs:
>> dc232b
>> dc233c
>> de212
>> de233_fpu
>> dsp3400
>> lx106
>> sample_controller
>> test_mmuhifi_c3
>>
>> Signed-off-by: Gavin Shan <gshan@redhat.com>
>> ---
>> target/xtensa/cpu.h | 10 +---------
>> target/xtensa/helper.c | 19 +++----------------
>> target/xtensa/overlay_tool.h | 7 ++-----
>> 3 files changed, 6 insertions(+), 30 deletions(-)
>>
>> diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
>> index dd81729306..ffeb1ca43f 100644
>> --- a/target/xtensa/cpu.h
>> +++ b/target/xtensa/cpu.h
>> @@ -491,11 +491,6 @@ typedef struct XtensaConfig {
>> bool use_first_nan;
>> } XtensaConfig;
>> -typedef struct XtensaConfigList {
>> - const XtensaConfig *config;
>> - struct XtensaConfigList *next;
>> -} XtensaConfigList;
>> -
>> #if HOST_BIG_ENDIAN
>> enum {
>> FP_F32_HIGH,
>> @@ -600,8 +595,6 @@ G_NORETURN void
>> xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
>> MMUAccessType
>> access_type, int mmu_idx,
>> uintptr_t retaddr);
>> -#define cpu_list xtensa_cpu_list
>> -
>> #define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU
>> #if TARGET_BIG_ENDIAN
>> @@ -620,13 +613,12 @@ void xtensa_collect_sr_names(const XtensaConfig
>> *config);
>> void xtensa_translate_init(void);
>> void **xtensa_get_regfile_by_name(const char *name, int entries, int
>> bits);
>> void xtensa_breakpoint_handler(CPUState *cs);
>> -void xtensa_register_core(XtensaConfigList *node);
>> +void xtensa_register_core(XtensaConfig *config);
>> void xtensa_sim_open_console(Chardev *chr);
>> void check_interrupts(CPUXtensaState *s);
>> void xtensa_irq_init(CPUXtensaState *env);
>> qemu_irq *xtensa_get_extints(CPUXtensaState *env);
>> qemu_irq xtensa_get_runstall(CPUXtensaState *env);
>> -void xtensa_cpu_list(void);
>> void xtensa_sync_window_from_phys(CPUXtensaState *env);
>> void xtensa_sync_phys_from_window(CPUXtensaState *env);
>> void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta);
>> diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
>> index dbeb97a953..3654739b09 100644
>> --- a/target/xtensa/helper.c
>> +++ b/target/xtensa/helper.c
>> @@ -35,8 +35,6 @@
>> #include "qemu/qemu-print.h"
>> #include "qemu/host-utils.h"
>> -static struct XtensaConfigList *xtensa_cores;
>> -
>> static void add_translator_to_hash(GHashTable *translator,
>> const char *name,
>> const XtensaOpcodeOps *opcode)
>> @@ -187,17 +185,15 @@ static void xtensa_core_class_init(ObjectClass
>> *oc, void *data)
>> cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
>> }
>> -void xtensa_register_core(XtensaConfigList *node)
>> +void xtensa_register_core(XtensaConfig *config)
>> {
>> TypeInfo type = {
>> .parent = TYPE_XTENSA_CPU,
>> .class_init = xtensa_core_class_init,
>> - .class_data = (void *)node->config,
>> + .class_data = (void *)config,
>> };
>
> This patch does two things and should be split.
I'm doing the split. This patch becomes:
-- >8 --
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index dd81729306..d9c49a35fa 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -600,8 +600,6 @@ G_NORETURN void
xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
MMUAccessType
access_type, int mmu_idx,
uintptr_t retaddr);
-#define cpu_list xtensa_cpu_list
-
#define CPU_RESOLVING_TYPE TYPE_XTENSA_CPU
#if TARGET_BIG_ENDIAN
@@ -626,7 +624,6 @@ void check_interrupts(CPUXtensaState *s);
void xtensa_irq_init(CPUXtensaState *env);
qemu_irq *xtensa_get_extints(CPUXtensaState *env);
qemu_irq xtensa_get_runstall(CPUXtensaState *env);
-void xtensa_cpu_list(void);
void xtensa_sync_window_from_phys(CPUXtensaState *env);
void xtensa_sync_phys_from_window(CPUXtensaState *env);
void xtensa_rotate_window(CPUXtensaState *env, uint32_t delta);
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index dbeb97a953..f6632df646 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -234,15 +234,6 @@ void xtensa_breakpoint_handler(CPUState *cs)
}
}
-void xtensa_cpu_list(void)
-{
- XtensaConfigList *core = xtensa_cores;
- qemu_printf("Available CPUs:\n");
- for (; core; core = core->next) {
- qemu_printf(" %s\n", core->config->name);
- }
-}
-
#ifndef CONFIG_USER_ONLY
void xtensa_cpu_do_unaligned_access(CPUState *cs,
vaddr addr, MMUAccessType access_type,
---
What is left is:
-- >8 --
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index d9c49a35fa..ffeb1ca43f 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -491,11 +491,6 @@ typedef struct XtensaConfig {
bool use_first_nan;
} XtensaConfig;
-typedef struct XtensaConfigList {
- const XtensaConfig *config;
- struct XtensaConfigList *next;
-} XtensaConfigList;
-
#if HOST_BIG_ENDIAN
enum {
FP_F32_HIGH,
@@ -618,7 +613,7 @@ void xtensa_collect_sr_names(const XtensaConfig
*config);
void xtensa_translate_init(void);
void **xtensa_get_regfile_by_name(const char *name, int entries, int
bits);
void xtensa_breakpoint_handler(CPUState *cs);
-void xtensa_register_core(XtensaConfigList *node);
+void xtensa_register_core(XtensaConfig *config);
void xtensa_sim_open_console(Chardev *chr);
void check_interrupts(CPUXtensaState *s);
void xtensa_irq_init(CPUXtensaState *env);
diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h
index 701c00eed2..7373ba7592 100644
--- a/target/xtensa/overlay_tool.h
+++ b/target/xtensa/overlay_tool.h
@@ -450,13 +450,10 @@
#endif
#if TARGET_BIG_ENDIAN == (XCHAL_HAVE_BE != 0)
-#define REGISTER_CORE(core) \
+#define REGISTER_CORE(config) \
static void __attribute__((constructor)) register_core(void) \
{ \
- static XtensaConfigList node = { \
- .config = &core, \
- }; \
- xtensa_register_core(&node); \
+ xtensa_register_core(&config); \
}
#else
#define REGISTER_CORE(core)
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index f6632df646..3654739b09 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -35,8 +35,6 @@
#include "qemu/qemu-print.h"
#include "qemu/host-utils.h"
-static struct XtensaConfigList *xtensa_cores;
-
static void add_translator_to_hash(GHashTable *translator,
const char *name,
const XtensaOpcodeOps *opcode)
@@ -187,17 +185,15 @@ static void xtensa_core_class_init(ObjectClass
*oc, void *data)
cc->gdb_num_core_regs = config->gdb_regmap.num_regs;
}
-void xtensa_register_core(XtensaConfigList *node)
+void xtensa_register_core(XtensaConfig *config)
{
TypeInfo type = {
.parent = TYPE_XTENSA_CPU,
.class_init = xtensa_core_class_init,
- .class_data = (void *)node->config,
+ .class_data = (void *)config,
};
- node->next = xtensa_cores;
- xtensa_cores = node;
- type.name = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"),
node->config->name);
+ type.name = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), config->name);
type_register(&type);
g_free((gpointer)type.name);
}
---
Which I will skip for now unless Max Ack-by it, since as per commit
ac8b7db493 ("target-xtensa: extract core configuration from overlay")
this might be used externally by the overlay tool generator.
Regards,
Phil.
next prev parent reply other threads:[~2023-11-16 13:30 UTC|newest]
Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-14 23:55 [PATCH v5 00/31] Unified CPU type check Gavin Shan
2023-11-14 23:55 ` [PATCH v5 01/31] target/alpha: Remove 'ev67' CPU class Gavin Shan
2023-11-15 0:22 ` Richard Henderson
2023-11-16 6:58 ` Philippe Mathieu-Daudé
2024-01-04 17:58 ` Philippe Mathieu-Daudé
2024-01-04 18:03 ` Philippe Mathieu-Daudé
2024-01-04 18:12 ` Philippe Mathieu-Daudé
2023-11-14 23:55 ` [PATCH v5 02/31] target/hppa: Remove object_class_is_abstract() Gavin Shan
2023-11-15 0:26 ` Richard Henderson
2023-11-15 11:18 ` BALATON Zoltan
2023-11-15 11:24 ` Gavin Shan
2023-11-15 11:27 ` BALATON Zoltan
2023-11-16 7:09 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 03/31] cpu: Call object_class_dynamic_cast() once in cpu_class_by_name() Gavin Shan
2023-11-15 0:30 ` Richard Henderson
2023-11-16 16:08 ` Philippe Mathieu-Daudé
2023-11-16 23:13 ` Gavin Shan
2023-11-14 23:56 ` [PATCH v5 04/31] target: Remove 'oc == NULL' check Gavin Shan
2023-11-15 0:34 ` Richard Henderson
2023-11-14 23:56 ` [PATCH v5 05/31] cpu: Add helper cpu_model_from_type() Gavin Shan
2023-11-15 0:35 ` Richard Henderson
2023-11-16 7:45 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 06/31] cpu: Add generic cpu_list() Gavin Shan
2023-11-15 0:37 ` Richard Henderson
2023-11-16 7:39 ` Philippe Mathieu-Daudé
2023-11-16 7:51 ` Philippe Mathieu-Daudé
2023-11-16 10:19 ` Philippe Mathieu-Daudé
2023-11-16 10:25 ` Philippe Mathieu-Daudé
2023-11-16 10:37 ` Gavin Shan
2023-11-16 10:34 ` Gavin Shan
2023-11-16 13:22 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 07/31] target/alpha: Use " Gavin Shan
2023-11-15 0:38 ` Richard Henderson
2023-11-16 7:47 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 08/31] target/arm: " Gavin Shan
2023-11-15 0:41 ` Richard Henderson
2023-11-16 7:51 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 09/31] target/avr: " Gavin Shan
2023-11-15 0:42 ` Richard Henderson
2023-11-16 7:51 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 10/31] target/cris: " Gavin Shan
2023-11-15 0:44 ` Richard Henderson
2023-11-16 7:52 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 11/31] target/hexagon: " Gavin Shan
2023-11-15 0:46 ` Richard Henderson
2023-11-16 7:52 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 12/31] target/hppa: " Gavin Shan
2023-11-15 0:57 ` Richard Henderson
2023-11-16 7:52 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 13/31] target/loongarch: " Gavin Shan
2023-11-15 0:59 ` Richard Henderson
2023-11-16 10:27 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 14/31] target/m68k: " Gavin Shan
2023-11-15 1:01 ` Richard Henderson
2023-11-16 10:27 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 15/31] target/mips: " Gavin Shan
2023-11-15 1:02 ` Richard Henderson
2023-11-16 7:53 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 16/31] target/openrisc: " Gavin Shan
2023-11-15 1:04 ` Richard Henderson
2023-11-16 10:28 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 17/31] target/riscv: " Gavin Shan
2023-11-15 1:05 ` Richard Henderson
2023-11-16 10:28 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 18/31] target/rx: " Gavin Shan
2023-11-15 1:07 ` Richard Henderson
2023-11-16 7:54 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 19/31] target/sh4: " Gavin Shan
2023-11-15 1:08 ` Richard Henderson
2023-11-16 7:55 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 20/31] target/tricore: " Gavin Shan
2023-11-15 1:09 ` Richard Henderson
2023-11-16 7:55 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 21/31] target/xtensa: " Gavin Shan
2023-11-15 1:12 ` Richard Henderson
2023-11-16 13:29 ` Philippe Mathieu-Daudé [this message]
2023-11-14 23:56 ` [PATCH v5 22/31] target: Use generic cpu_model_from_type() Gavin Shan
2023-11-15 1:17 ` Richard Henderson
2023-11-16 13:32 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 23/31] machine: Constify MachineClass::valid_cpu_types[i] Gavin Shan
2023-11-15 1:17 ` Richard Henderson
2023-11-16 9:52 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 24/31] machine: Use error handling when CPU type is checked Gavin Shan
2023-11-15 1:21 ` Richard Henderson
2023-11-15 1:26 ` Richard Henderson
2023-11-14 23:56 ` [PATCH v5 25/31] machine: Introduce helper is_cpu_type_supported() Gavin Shan
2023-11-16 9:33 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 26/31] machine: Print CPU model name instead of CPU type name Gavin Shan
2023-11-15 1:32 ` Richard Henderson
2023-11-14 23:56 ` [PATCH v5 27/31] hw/arm/virt: Hide host CPU model for tcg Gavin Shan
2023-11-14 23:56 ` [PATCH v5 28/31] hw/arm/virt: Check CPU type in machine_run_board_init() Gavin Shan
2023-11-14 23:56 ` [PATCH v5 29/31] hw/arm/sbsa-ref: " Gavin Shan
2023-11-14 23:56 ` [PATCH v5 30/31] hw/arm: " Gavin Shan
2023-11-16 8:35 ` Philippe Mathieu-Daudé
2023-11-14 23:56 ` [PATCH v5 31/31] hw/riscv/shakti_c: " Gavin Shan
2023-11-16 10:01 ` [PATCH v5 00/31] Unified CPU type check Philippe Mathieu-Daudé
2023-11-16 10:12 ` Gavin Shan
2023-11-16 13:35 ` Philippe Mathieu-Daudé
2023-11-16 16:20 ` Philippe Mathieu-Daudé
2023-11-16 23:26 ` Gavin Shan
2023-11-17 7:34 ` Philippe Mathieu-Daudé
2023-11-18 6:40 ` Gavin Shan
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