From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57165) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V6dQf-0006Vg-Qb for qemu-devel@nongnu.org; Tue, 06 Aug 2013 05:19:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V6dQZ-0007h8-2N for qemu-devel@nongnu.org; Tue, 06 Aug 2013 05:19:45 -0400 Message-ID: <5200BFA6.1070308@suse.de> Date: Tue, 06 Aug 2013 11:19:34 +0200 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1375777673-20274-1-git-send-email-aik@ozlabs.ru> <1375777673-20274-3-git-send-email-aik@ozlabs.ru> In-Reply-To: <1375777673-20274-3-git-send-email-aik@ozlabs.ru> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 2/6] xics: add pre_save/post_load/cpu_setup dispatchers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexey Kardashevskiy Cc: Anthony Liguori , Alexander Graf , qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Paul Mackerras , David Gibson Am 06.08.2013 10:27, schrieb Alexey Kardashevskiy: > The upcoming support of in-kernel XICS will redefine migration callback= s > for both ICS and ICP so classes and callback pointers are added. >=20 > This adds a cpu_setup callback to the XICS device class (as XICS-KVM > will do it different) and xics_dispatch_cpu_setup(). This also moves > the place where xics_dispatch_cpu_setup() is called a bit further to > have VCPU initialized (required for XICS-KVM). >=20 > Signed-off-by: Alexey Kardashevskiy > --- > hw/intc/xics.c | 61 +++++++++++++++++++++++++++++++++++++++++++= ++++---- > hw/ppc/spapr.c | 4 ++-- > include/hw/ppc/xics.h | 46 +++++++++++++++++++++++++++++++++++++- > 3 files changed, 104 insertions(+), 7 deletions(-) >=20 > diff --git a/hw/intc/xics.c b/hw/intc/xics.c > index 6b3c071..c5dad2f 100644 > --- a/hw/intc/xics.c > +++ b/hw/intc/xics.c > @@ -153,11 +153,35 @@ static void icp_irq(XICSState *icp, int server, i= nt nr, uint8_t priority) > } > } > =20 > +static void icp_dispatch_pre_save(void *opaque) > +{ > + ICPState *ss =3D opaque; > + ICPStateClass *info =3D ICP_GET_CLASS(ss); > + > + if (info->pre_save) { > + info->pre_save(ss); > + } > +} > + > +static int icp_dispatch_post_load(void *opaque, int version_id) > +{ > + ICPState *ss =3D opaque; > + ICPStateClass *info =3D ICP_GET_CLASS(ss); > + > + if (info->post_load) { > + return info->post_load(ss); > + } > + > + return 0; > +} > + > static const VMStateDescription vmstate_icp_server =3D { > .name =3D "icp/server", > .version_id =3D 1, > .minimum_version_id =3D 1, > .minimum_version_id_old =3D 1, > + .pre_save =3D icp_dispatch_pre_save, > + .post_load =3D icp_dispatch_post_load, > .fields =3D (VMStateField []) { > /* Sanity check */ > VMSTATE_UINT32(xirr, ICPState), > @@ -192,6 +216,7 @@ static TypeInfo icp_info =3D { > .parent =3D TYPE_DEVICE, > .instance_size =3D sizeof(ICPState), > .class_init =3D icp_class_init, > + .class_size =3D sizeof(ICPStateClass), > }; > =20 > /* > @@ -353,10 +378,9 @@ static void ics_reset(DeviceState *dev) > } > } > =20 > -static int ics_post_load(void *opaque, int version_id) > +static int ics_post_load(ICSState *ics) > { > int i; > - ICSState *ics =3D opaque; > =20 > for (i =3D 0; i < ics->icp->nr_servers; i++) { > icp_resend(ics->icp, i); > @@ -365,6 +389,28 @@ static int ics_post_load(void *opaque, int version= _id) > return 0; > } > =20 > +static void ics_dispatch_pre_save(void *opaque) > +{ > + ICSState *ics =3D opaque; > + ICSStateClass *info =3D ICS_GET_CLASS(ics); > + > + if (info->pre_save) { > + info->pre_save(ics); > + } > +} > + > +static int ics_dispatch_post_load(void *opaque, int version_id) > +{ > + ICSState *ics =3D opaque; > + ICSStateClass *info =3D ICS_GET_CLASS(ics); > + > + if (info->post_load) { > + return info->post_load(ics); Pass version_id through? > + } > + > + return 0; > +} > + > static const VMStateDescription vmstate_ics_irq =3D { > .name =3D "ics/irq", > .version_id =3D 1, > @@ -384,7 +430,8 @@ static const VMStateDescription vmstate_ics =3D { > .version_id =3D 1, > .minimum_version_id =3D 1, > .minimum_version_id_old =3D 1, > - .post_load =3D ics_post_load, > + .pre_save =3D ics_dispatch_pre_save, > + .post_load =3D ics_dispatch_post_load, > .fields =3D (VMStateField []) { > /* Sanity check */ > VMSTATE_UINT32_EQUAL(nr_irqs, ICSState), > @@ -409,10 +456,12 @@ static int ics_realize(DeviceState *dev) > static void ics_class_init(ObjectClass *klass, void *data) > { > DeviceClass *dc =3D DEVICE_CLASS(klass); > + ICSStateClass *k =3D ICS_CLASS(klass); isc? Otherwise looks fine. Andreas > =20 > dc->init =3D ics_realize; > dc->vmsd =3D &vmstate_ics; > dc->reset =3D ics_reset; > + k->post_load =3D ics_post_load; > } > =20 > static TypeInfo ics_info =3D { > @@ -420,6 +469,7 @@ static TypeInfo ics_info =3D { > .parent =3D TYPE_DEVICE, > .instance_size =3D sizeof(ICSState), > .class_init =3D ics_class_init, > + .class_size =3D sizeof(ICSStateClass), > }; > =20 > /* > @@ -612,7 +662,7 @@ static void xics_reset(DeviceState *d) > device_reset(DEVICE(icp->ics)); > } > =20 > -void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu) > +static void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu) > { > CPUState *cs =3D CPU(cpu); > CPUPPCState *env =3D &cpu->env; > @@ -674,10 +724,12 @@ static Property xics_properties[] =3D { > static void xics_class_init(ObjectClass *oc, void *data) > { > DeviceClass *dc =3D DEVICE_CLASS(oc); > + XICSStateClass *k =3D XICS_CLASS(oc); > =20 > dc->realize =3D xics_realize; > dc->props =3D xics_properties; > dc->reset =3D xics_reset; > + k->cpu_setup =3D xics_cpu_setup; > =20 > spapr_rtas_register("ibm,set-xive", rtas_set_xive); > spapr_rtas_register("ibm,get-xive", rtas_get_xive); > @@ -694,6 +746,7 @@ static const TypeInfo xics_info =3D { > .name =3D TYPE_XICS, > .parent =3D TYPE_SYS_BUS_DEVICE, > .instance_size =3D sizeof(XICSState), > + .class_size =3D sizeof(XICSStateClass), > .class_init =3D xics_class_init, > .instance_init =3D xics_initfn, > }; > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index 16bfab9..432f0d2 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -1155,8 +1155,6 @@ static void ppc_spapr_init(QEMUMachineInitArgs *a= rgs) > } > env =3D &cpu->env; > =20 > - xics_cpu_setup(spapr->icp, cpu); > - > /* Set time-base frequency to 512 MHz */ > cpu_ppc_tb_init(env, TIMEBASE_FREQ); > =20 > @@ -1170,6 +1168,8 @@ static void ppc_spapr_init(QEMUMachineInitArgs *a= rgs) > kvmppc_set_papr(cpu); > } > =20 > + xics_dispatch_cpu_setup(spapr->icp, cpu); > + > qemu_register_reset(spapr_cpu_reset, cpu); > } > =20 > diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h > index 66364c5..90ecaf8 100644 > --- a/include/hw/ppc/xics.h > +++ b/include/hw/ppc/xics.h > @@ -32,6 +32,11 @@ > #define TYPE_XICS "xics" > #define XICS(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS) > =20 > +#define XICS_CLASS(klass) \ > + OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS) > +#define XICS_GET_CLASS(obj) \ > + OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS) > + > #define XICS_IPI 0x2 > #define XICS_BUID 0x1 > #define XICS_IRQ_BASE (XICS_BUID << 12) > @@ -41,11 +46,20 @@ > * (the kernel implementation supports more but we don't exploit > * that yet) > */ > +typedef struct XICSStateClass XICSStateClass; > typedef struct XICSState XICSState; > +typedef struct ICPStateClass ICPStateClass; > typedef struct ICPState ICPState; > +typedef struct ICSStateClass ICSStateClass; > typedef struct ICSState ICSState; > typedef struct ICSIRQState ICSIRQState; > =20 > +struct XICSStateClass { > + DeviceClass parent_class; > + > + void (*cpu_setup)(XICSState *icp, PowerPCCPU *cpu); > +}; > + > struct XICSState { > /*< private >*/ > SysBusDevice parent_obj; > @@ -59,6 +73,18 @@ struct XICSState { > #define TYPE_ICP "icp" > #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP) > =20 > +#define ICP_CLASS(klass) \ > + OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP) > +#define ICP_GET_CLASS(obj) \ > + OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP) > + > +struct ICPStateClass { > + DeviceClass parent_class; > + > + void (*pre_save)(ICPState *s); > + int (*post_load)(ICPState *s); > +}; > + > struct ICPState { > /*< private >*/ > DeviceState parent_obj; > @@ -72,6 +98,18 @@ struct ICPState { > #define TYPE_ICS "ics" > #define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS) > =20 > +#define ICS_CLASS(klass) \ > + OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS) > +#define ICS_GET_CLASS(obj) \ > + OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS) > + > +struct ICSStateClass { > + DeviceClass parent_class; > + > + void (*pre_save)(ICSState *s); > + int (*post_load)(ICSState *s); > +}; > + > struct ICSState { > /*< private >*/ > DeviceState parent_obj; > @@ -98,6 +136,12 @@ struct ICSIRQState { > qemu_irq xics_get_qirq(XICSState *icp, int irq); > void xics_set_irq_type(XICSState *icp, int irq, bool lsi); > =20 > -void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu); > +static inline void xics_dispatch_cpu_setup(XICSState *icp, PowerPCCPU = *cpu) > +{ > + XICSStateClass *info =3D XICS_GET_CLASS(icp); > + > + assert(info->cpu_setup); > + info->cpu_setup(icp, cpu); > +} > =20 > #endif /* __XICS_H__ */ >=20 --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg