From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58612) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V7M2e-0008J2-Bp for qemu-devel@nongnu.org; Thu, 08 Aug 2013 04:58:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V7M2Y-0004s5-3y for qemu-devel@nongnu.org; Thu, 08 Aug 2013 04:57:56 -0400 Received: from mx1.redhat.com ([209.132.183.28]:59540) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V7M2X-0004ry-Sd for qemu-devel@nongnu.org; Thu, 08 Aug 2013 04:57:50 -0400 Message-ID: <52035D88.6040002@redhat.com> Date: Thu, 08 Aug 2013 10:57:44 +0200 From: Gerd Hoffmann MIME-Version: 1.0 References: <20130806165820.GB20305@redhat.com> <5201F763.3030507@redhat.com> <20130807095019.GA26266@redhat.com> <5202218C.70005@redhat.com> <20130807111031.GC3068@redhat.com> <52023A52.6010208@redhat.com> <20130807123509.GA10670@redhat.com> <520257F8.1080501@redhat.com> <20130807145312.GA14308@redhat.com> <52034F73.4040904@redhat.com> <20130808083732.GB26837@redhat.com> In-Reply-To: <20130808083732.GB26837@redhat.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [SeaBIOS] [PATCH] acpi: hide 64-bit PCI hole for Windows XP List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: Paolo Bonzini , seabios@seabios.org, qemu-devel@nongnu.org On 08/08/13 10:37, Michael S. Tsirkin wrote: > On Thu, Aug 08, 2013 at 09:57:39AM +0200, Gerd Hoffmann wrote: >>>> (3) mmconf xbar start (MCFG, q35 only, at 0xb0000000 now). >>>> (4) pmbase (FADT, at 0xb000 now). >>>> >>>> Especially 3+4 tend to be compile-time constants in the firmware as they >>>> are needed very early in the setup process. >>> >>> So we don't need them in pci-config, just stick constant in ACPI. >> >> I don't want them be constant. I want allow the firmware pick them. >> Our mmconfig xbar is 256M and can handle 256 busses. I'd like to have >> the option to reduce that to 64M and place it somewhere else. >> >> Also coreboot and seabios use different values for pmbase. coreboot on >> q35 maps the pmbase below 0x1000. Which surely makes sense. When we >> don't place chipset stuff at 0xb000 we can assign the 0xb000->0xbfff >> window to a pci bridge instead. > > Yes, this might be useful. But I don't think it's required to > use linker to patch ACPI tables for this - we can write ASL code to read > the register back from device configuration, instead. No, we can't, because the address is in the FADT. cheers, Gerd