From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34781) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V7g8U-0002RJ-Ed for qemu-devel@nongnu.org; Fri, 09 Aug 2013 02:25:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V7g8N-0004iL-VS for qemu-devel@nongnu.org; Fri, 09 Aug 2013 02:25:18 -0400 Received: from mx1.redhat.com ([209.132.183.28]:11007) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V7g8N-0004iB-Lp for qemu-devel@nongnu.org; Fri, 09 Aug 2013 02:25:11 -0400 Message-ID: <52048B3C.2030401@redhat.com> Date: Fri, 09 Aug 2013 08:25:00 +0200 From: Gerd Hoffmann MIME-Version: 1.0 References: <20130807123509.GA10670@redhat.com> <520257F8.1080501@redhat.com> <20130807145312.GA14308@redhat.com> <52034F73.4040904@redhat.com> <20130808083732.GB26837@redhat.com> <52035D88.6040002@redhat.com> <20130808095226.GB27298@redhat.com> <5203712C.8090202@redhat.com> <20130808141347.GA30200@redhat.com> <5203B1B7.5000102@redhat.com> <20130809041306.GB6869@morn.localdomain> In-Reply-To: <20130809041306.GB6869@morn.localdomain> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [SeaBIOS] [PATCH] acpi: hide 64-bit PCI hole for Windows XP List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Kevin O'Connor Cc: Paolo Bonzini , seabios@seabios.org, qemu-devel@nongnu.org, "Michael S. Tsirkin" Hi, >> pmbase is a compile-time constant (aka #define) in both seabios and >> coreboot, and making this runtime-configurable is non-trivial. See >> src/smm.c in seabios for one reason why. > Converting src/smm.c to use a runtime value isn't hard - just change > the assembler from: "mov $" __stringify(PORT_ACPI_PM_BASE) " + 0x04, > %dx\n" to: "mov 4(my_acpi_base), %dx\n" and make sure to define the > global variable my_acpi_base as VARFSEG. Ah, good, I give that a try. Need to check how that works out for coreboot though. That leaves the mmconf xbar location. We can continue to have everybody agree this should be mapped @ 0xb0000000 and be done with it. Making this configurable via fw_cfg is no problem for seabios. coreboot can't deal with it though, it sets up the xbar _very_ early because it does the complete pci setup via mmconf. >> In seabios we have fixed 32bit / 64bit width today, from acpi.c: >> >> // store pci io windows >> *(u32*)&ssdt_ptr[acpi_pci32_start[0]] = cpu_to_le32(pcimem_start); >> *(u32*)&ssdt_ptr[acpi_pci32_end[0]] = cpu_to_le32(pcimem_end - 1); >> if (pcimem64_start) { >> ssdt_ptr[acpi_pci64_valid[0]] = 1; >> *(u64*)&ssdt_ptr[acpi_pci64_start[0]] = cpu_to_le64(pcimem64_start); >> *(u64*)&ssdt_ptr[acpi_pci64_end[0]] = cpu_to_le64(pcimem64_end - 1); >> *(u64*)&ssdt_ptr[acpi_pci64_length[0]] = cpu_to_le64( >> pcimem64_end - pcimem64_start); >> } else { >> ssdt_ptr[acpi_pci64_valid[0]] = 0; >> } >> >> Storing fixup instructions for these fields in the linker script >> shouldn't be hard I think. > > I don't think SeaBIOS should continue to do the above once the tables > are moved to QEMU. QEMU has all the info SeaBIOS has, so it can > generate the tables correctly on its own. The loader script provided by qemu has fixup instructions, which is needed to fixup pointers to other acpi tables. The idea is to use that mechanism to also allow th firmware to fixup addresses like pmbase in the qemu-generated tables. cheers, Gerd