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Date: Fri, 09 Aug 2013 08:48:02 -1000
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Subject: Re: [Qemu-devel] [PATCH 1/2] memory: Provide separate handling of
 unassigned io ports accesses
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To: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= <afaerber@suse.de>
Cc: Peter Maydell <peter.maydell@linaro.org>, Paolo Bonzini <pbonzini@redhat.com>, qemu-devel <qemu-devel@nongnu.org>, Jan Kiszka <jan.kiszka@siemens.com>

On 08/09/2013 06:49 AM, Andreas Färber wrote:
> Am 09.08.2013 09:41, schrieb Paolo Bonzini:
>> Il 08/08/2013 17:43, Jan Kiszka ha scritto:
>>> On 2013-08-08 17:33, Peter Maydell wrote:
>>>> On 3 August 2013 09:31, Jan Kiszka <jan.kiszka@web.de> wrote:
>>>>> --- a/ioport.c
>>>>> +++ b/ioport.c
>>>>> @@ -44,6 +44,22 @@ typedef struct MemoryRegionPortioList {
>>>>>      MemoryRegionPortio ports[];
>>>>>  } MemoryRegionPortioList;
>>>>>
>>>>> +static uint64_t unassigned_io_read(void *opaque, hwaddr addr, unsigned size)
>>>>> +{
>>>>> +    return -1UL;
>>>>
>>>> This should probably be "-1ULL", otherwise we'll return
>>>> different values on 32 bit and 64 bit hosts. (Actually
>>>> managing a 64 bit read of the i/o space is pretty
>>>> unlikely, though possibly alpha memory-mapped via the
>>>> PCI space might let you do it.)
>>>
>>> No problem with changing this - but wouldn't 64-bit i/o accesses be a
>>> bug? It's not allowed according to PCI, no device can handle it
>>> (officially), so no arch should forward such requests from mmio, rather
>>> break them up first.
>>
>> Yes, the impl.max_access_size should never be 8.  Though 1ULL would be
>> clearer perhaps.
> 
> Let's CC rth.

At least the CIA and TYPHOON pci host controlers can generate quadword accesses
to all of MEM, IO, and config space.  Whether or not such an access is valid
for any given device is a separate issue.


r~