From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59899) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V7rzX-0000bL-TY for qemu-devel@nongnu.org; Fri, 09 Aug 2013 15:04:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1V7rzR-0003uO-Uz for qemu-devel@nongnu.org; Fri, 09 Aug 2013 15:04:51 -0400 Received: from mail-we0-f170.google.com ([74.125.82.170]:36461) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1V7rzR-0003uA-Oj for qemu-devel@nongnu.org; Fri, 09 Aug 2013 15:04:45 -0400 Received: by mail-we0-f170.google.com with SMTP id w60so3888687wes.15 for ; Fri, 09 Aug 2013 12:04:44 -0700 (PDT) Message-ID: <52053D4B.2030209@virtualopensystems.com> Date: Fri, 09 Aug 2013 21:04:43 +0200 From: "Mian M. Hamayun" MIME-Version: 1.0 References: <1374571996-9228-1-git-send-email-m.hamayun@virtualopensystems.com> <1374571996-9228-8-git-send-email-m.hamayun@virtualopensystems.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 7/7] AARCH64: Use the spin-table method for booting secondary processors in machvirt Reply-To: m.hamayun@virtualopensystems.com List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Marc Zyngier , tech@virtualopensystems.com, qemu-devel@nongnu.org, kvmarm@lists.cs.columbia.edu On 09/08/2013 16:34, Peter Maydell wrote: > On 23 July 2013 10:33, Mian M. Hamayun wrote: >> From: "Mian M. Hamayun" >> >> As the SMP bootloader uses a spin-table to wait for the cpu_release_addr, we >> disable the PSCI method for AArch64 in machvirt and use spin-table instead. > Marc Z says we should be using PSCI for secondary CPU boot for aarch64, > same as for aarch32. > OK, we will look into this as well. Thanks!