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Date: Wed, 21 Aug 2013 16:12:13 +0200
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Subject: Re: [Qemu-devel] [PATCH qom-cpu for-next 1/2] cpu: Use QTAILQ for
 CPU list
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: Anthony Liguori <aliguori@us.ibm.com>, Gleb Natapov <gleb@redhat.com>, kvm <kvm@vger.kernel.org>, Riku Voipio <riku.voipio@iki.fi>, Alexander Graf <agraf@suse.de>, qemu-devel@nongnu.org, qemu-ppc <qemu-ppc@nongnu.org>, Paul Brook <paul@codesourcery.com>, Scott Wood <scottwood@freescale.com>, Paolo Bonzini <pbonzini@redhat.com>, Luiz Capitulino <lcapitulino@redhat.com>, Aurelien Jarno <aurelien@aurel32.net>

Am 30.07.2013 18:55, schrieb Andreas F=C3=A4rber:
> Introduce CPU_FOREACH(), CPU_FOREACH_SAFE() and CPU_NEXT() shorthand
> macros.
>=20
> Signed-off-by: Andreas F=C3=A4rber <afaerber@suse.de>

Needs the following addition now:

diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
index af182da..9d0e27e 100644
--- a/hw/cpu/a15mpcore.c
+++ b/hw/cpu/a15mpcore.c
@@ -72,9 +72,15 @@ static int a15mp_priv_init(SysBusDevice *dev)
     /* Wire the outputs from each CPU's generic timer to the
      * appropriate GIC PPI inputs
      */
-    for (i =3D 0, cpu =3D first_cpu; i < s->num_cpu; i++, cpu =3D
cpu->next_cpu) {
+    i =3D 0;
+    CPU_FOREACH(cpu) {
         DeviceState *cpudev =3D DEVICE(cpu);
         int ppibase =3D s->num_irq - 32 + i * 32;
+
+        if (i < s->num_cpu) {
+            break;
+        }
+
         /* physical timer; we wire it up to the non-secure timer's ID,
          * since a real A15 always has TrustZone but QEMU doesn't.
          */
@@ -83,6 +89,7 @@ static int a15mp_priv_init(SysBusDevice *dev)
         /* virtual timer */
         qdev_connect_gpio_out(cpudev, 1,
                               qdev_get_gpio_in(s->gic, ppibase + 27));
+        i++;
     }

     /* Memory map (addresses are offsets from PERIPHBASE):


--=20
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