From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33670) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VCBLG-0006LU-CX for qemu-devel@nongnu.org; Wed, 21 Aug 2013 12:33:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VCBLA-0007h3-D0 for qemu-devel@nongnu.org; Wed, 21 Aug 2013 12:33:06 -0400 Message-ID: <5214EBB6.7040702@suse.de> Date: Wed, 21 Aug 2013 18:32:54 +0200 From: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= MIME-Version: 1.0 References: <1375203359-17562-1-git-send-email-afaerber@suse.de> <1375203359-17562-2-git-send-email-afaerber@suse.de> <5214CABD.8010509@suse.de> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH qom-cpu for-next 1/2] cpu: Use QTAILQ for CPU list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Anthony Liguori , Gleb Natapov , kvm , Riku Voipio , Alexander Graf , QEMU Developers , qemu-ppc , Paul Brook , Scott Wood , Paolo Bonzini , Luiz Capitulino , Aurelien Jarno Am 21.08.2013 16:36, schrieb Peter Maydell: > On 21 August 2013 15:12, Andreas F=C3=A4rber wrote: >=20 >> - for (i =3D 0, cpu =3D first_cpu; i < s->num_cpu; i++, cpu =3D >> cpu->next_cpu) { >> + i =3D 0; >> + CPU_FOREACH(cpu) { >> DeviceState *cpudev =3D DEVICE(cpu); >> int ppibase =3D s->num_irq - 32 + i * 32; >> + >> + if (i < s->num_cpu) { >> + break; >> + } >> + >> /* physical timer; we wire it up to the non-secure timer's ID= , >> * since a real A15 always has TrustZone but QEMU doesn't. >> */ >> @@ -83,6 +89,7 @@ static int a15mp_priv_init(SysBusDevice *dev) >> /* virtual timer */ >> qdev_connect_gpio_out(cpudev, 1, >> qdev_get_gpio_in(s->gic, ppibase + 27))= ; >> + i++; >> } >=20 > It seems a bit ugly to have to both enumerate the CPUs > via CPU_FOREACH and update an index i simultaneously. Same for the original code. :) > Isn't there any way to either say "give me the CPU pointer for > CPU i" or "give me the index i of this CPU" ? There is: diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index 9d0e27e..1263b12 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -50,7 +50,6 @@ static int a15mp_priv_init(SysBusDevice *dev) SysBusDevice *busdev; const char *gictype =3D "arm_gic"; int i; - CPUState *cpu; if (kvm_irqchip_in_kernel()) { gictype =3D "kvm-arm-gic"; @@ -72,15 +71,10 @@ static int a15mp_priv_init(SysBusDevice *dev) /* Wire the outputs from each CPU's generic timer to the * appropriate GIC PPI inputs */ - i =3D 0; - CPU_FOREACH(cpu) { - DeviceState *cpudev =3D DEVICE(cpu); + for (i =3D 0; i < s->num_cpu; i++) { + DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i)); int ppibase =3D s->num_irq - 32 + i * 32; - if (i < s->num_cpu) { - break; - } - /* physical timer; we wire it up to the non-secure timer's ID, * since a real A15 always has TrustZone but QEMU doesn't. */ @@ -89,7 +83,6 @@ static int a15mp_priv_init(SysBusDevice *dev) /* virtual timer */ qdev_connect_gpio_out(cpudev, 1, qdev_get_gpio_in(s->gic, ppibase + 27)); - i++; } /* Memory map (addresses are offsets from PERIPHBASE): --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=C3=BCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=C3=B6rffer; HRB 16746 AG N=C3=BC= rnberg