From: Alexey Kardashevskiy <aik@ozlabs.ru>
To: Anthony Liguori <anthony@codemonkey.ws>
Cc: David Gibson <david@gibson.dropbear.id.au>,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
Alexander Graf <agraf@suse.de>
Subject: Re: [Qemu-devel] [PATCH] spapr-pci: rework MSI/MSIX
Date: Fri, 23 Aug 2013 13:10:30 +1000 [thread overview]
Message-ID: <5216D2A6.10208@ozlabs.ru> (raw)
In-Reply-To: <877gg61fii.fsf@codemonkey.ws>
On 08/01/2013 09:22 AM, Anthony Liguori wrote:
> Alexey Kardashevskiy <aik@ozlabs.ru> writes:
>
>> On 08/01/2013 04:02 AM, Anthony Liguori wrote:
>>> Alexey Kardashevskiy <aik@ozlabs.ru> writes:
>>>
>>>> On the sPAPR platform a guest allocates MSI/MSIX vectors via RTAS
>>>> hypercalls which return global IRQ numbers to a guest so it only
>>>> operates with those and never touches MSIMessage.
>>>>
>>>> Therefore MSIMessage handling is completely hidden in QEMU.
>>>>
>>>> Previously every sPAPR PCI host bridge implemented its own MSI window
>>>> to catch msi_notify()/msix_notify() calls from QEMU devices (virtio-pci
>>>> or vfio) and route them to the guest via qemu_pulse_irq().
>>>> MSIMessage used to be encoded as:
>>>> .addr - address within the PHB MSI window;
>>>> .data - the device index on PHB plus vector number.
>>>> The MSI MR write function translated this MSIMessage to a global IRQ
>>>> number and called qemu_pulse_irq().
>>>>
>>>> However the total number of IRQs is not really big (at the moment it is
>>>> 1024 IRQs starting from 4096) and even 16bit data field of MSIMessage
>>>> seems to be enough to store an IRQ number there.
>>>>
>>>> This simplifies MSI handling in sPAPR PHB. Specifically, this does:
>>>> 1. remove a MSI window from a PHB;
>>>> 2. add a single memory region for all MSIs to sPAPREnvironment
>>>> and spapr_pci_msi_init() to initialize it;
>>>> 3. encode MSIMessage as:
>>>> * .addr - a fixed address of SPAPR_PCI_MSI_WINDOW==0x40000000000ULL;
>>>> * .data as an IRQ number.
>>>> 4. change IRQ allocator to align first IRQ number in a block for MSI.
>>>> MSI uses lower bits to specify the vector number so the first IRQ has to
>>>> be aligned. MSIX does not need any special allocator though.
>>>>
>>>> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
>>>
>>> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
>>>
>>> Does this actually fix any bug or is this just refactoring? If it's the
>>> later, it'll have to wait until after the 1.7 window opens up.
>>
>>
>> This is refactoring which should make IRQFD enablement on spapr
>> easier.
>
> Okay, I'll apply it after hard freeze then.
Anyone, ping?
--
Alexey
next prev parent reply other threads:[~2013-08-23 3:10 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-12 7:38 [Qemu-devel] [PATCH] spapr-pci: rework MSI/MSIX Alexey Kardashevskiy
2013-07-23 2:54 ` Alexey Kardashevskiy
2013-07-30 2:56 ` Alexey Kardashevskiy
2013-07-31 18:02 ` Anthony Liguori
2013-07-31 22:56 ` Alexey Kardashevskiy
2013-07-31 23:22 ` Anthony Liguori
2013-08-23 3:10 ` Alexey Kardashevskiy [this message]
2013-08-01 9:01 ` Michael S. Tsirkin
2013-08-25 18:31 ` Alexander Graf
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