From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58169) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VCoKl-0006Eo-F8 for qemu-devel@nongnu.org; Fri, 23 Aug 2013 06:11:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VCoKe-0008Tr-2r for qemu-devel@nongnu.org; Fri, 23 Aug 2013 06:11:11 -0400 Received: from cantor2.suse.de ([195.135.220.15]:38400 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VCoKd-0008Tf-Pg for qemu-devel@nongnu.org; Fri, 23 Aug 2013 06:11:04 -0400 Message-ID: <52173531.5080602@suse.de> Date: Fri, 23 Aug 2013 12:10:57 +0200 From: =?ISO-8859-15?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <1377250793-24027-1-git-send-email-pbonzini@redhat.com> <1377250793-24027-2-git-send-email-pbonzini@redhat.com> In-Reply-To: <1377250793-24027-2-git-send-email-pbonzini@redhat.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PULL 1/9] Initialize IA32_FEATURE_CONTROL MSR in reset and migration List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: gleb@redhat.com, Arthur Chunqi Li , qemu-devel@nongnu.org, anthony@codemonkey.ws Am 23.08.2013 11:39, schrieb Paolo Bonzini: > From: Arthur Chunqi Li >=20 > The recent KVM patch adds IA32_FEATURE_CONTROL support. QEMU needs > to clear this MSR when reset vCPU and keep the value of it when > migration. This patch add this feature. >=20 > Signed-off-by: Arthur Chunqi Li > Signed-off-by: Gleb Natapov > --- > target-i386/cpu.h | 2 ++ > target-i386/kvm.c | 4 ++++ > target-i386/machine.c | 22 ++++++++++++++++++++++ > 3 files changed, 28 insertions(+) >=20 > diff --git a/target-i386/cpu.h b/target-i386/cpu.h > index cedefdc..3a52f94 100644 > --- a/target-i386/cpu.h > +++ b/target-i386/cpu.h > @@ -301,6 +301,7 @@ > #define MSR_IA32_APICBASE_BSP (1<<8) > #define MSR_IA32_APICBASE_ENABLE (1<<11) > #define MSR_IA32_APICBASE_BASE (0xfffff<<12) > +#define MSR_IA32_FEATURE_CONTROL 0x0000003a > #define MSR_TSC_ADJUST 0x0000003b > #define MSR_IA32_TSCDEADLINE 0x6e0 > =20 > @@ -813,6 +814,7 @@ typedef struct CPUX86State { > =20 > uint64_t mcg_status; > uint64_t msr_ia32_misc_enable; > + uint64_t msr_ia32_feature_control; > =20 > /* exception/interrupt handling */ > int error_code; > diff --git a/target-i386/kvm.c b/target-i386/kvm.c > index 3c9d10a..84ac00a 100644 > --- a/target-i386/kvm.c > +++ b/target-i386/kvm.c > @@ -1121,6 +1121,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level) > if (hyperv_vapic_recommended()) { > kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE,= 0); > } > + kvm_msr_entry_set(&msrs[n++], MSR_IA32_FEATURE_CONTROL, env->m= sr_ia32_feature_control); > } > if (env->mcg_cap) { > int i; > @@ -1345,6 +1346,7 @@ static int kvm_get_msrs(X86CPU *cpu) > if (has_msr_misc_enable) { > msrs[n++].index =3D MSR_IA32_MISC_ENABLE; > } > + msrs[n++].index =3D MSR_IA32_FEATURE_CONTROL; > =20 > if (!env->tsc_valid) { > msrs[n++].index =3D MSR_IA32_TSC; > @@ -1443,6 +1445,8 @@ static int kvm_get_msrs(X86CPU *cpu) > case MSR_IA32_MISC_ENABLE: > env->msr_ia32_misc_enable =3D msrs[i].data; > break; > + case MSR_IA32_FEATURE_CONTROL: > + env->msr_ia32_feature_control =3D msrs[i].data; Shouldn't this patch be fixed to have the break that is being added in 5/= 9? Andreas > default: > if (msrs[i].index >=3D MSR_MC0_CTL && > msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * = 4) { > diff --git a/target-i386/machine.c b/target-i386/machine.c > index f9ec581..0d2088e 100644 > --- a/target-i386/machine.c > +++ b/target-i386/machine.c > @@ -435,6 +435,14 @@ static bool misc_enable_needed(void *opaque) > return env->msr_ia32_misc_enable !=3D MSR_IA32_MISC_ENABLE_DEFAULT= ; > } > =20 > +static bool feature_control_needed(void *opaque) > +{ > + X86CPU *cpu =3D opaque; > + CPUX86State *env =3D &cpu->env; > + > + return env->msr_ia32_feature_control !=3D 0; > +} > + > static const VMStateDescription vmstate_msr_ia32_misc_enable =3D { > .name =3D "cpu/msr_ia32_misc_enable", > .version_id =3D 1, > @@ -446,6 +454,17 @@ static const VMStateDescription vmstate_msr_ia32_m= isc_enable =3D { > } > }; > =20 > +static const VMStateDescription vmstate_msr_ia32_feature_control =3D { > + .name =3D "cpu/msr_ia32_feature_control", > + .version_id =3D 1, > + .minimum_version_id =3D 1, > + .minimum_version_id_old =3D 1, > + .fields =3D (VMStateField []) { > + VMSTATE_UINT64(env.msr_ia32_feature_control, X86CPU), > + VMSTATE_END_OF_LIST() > + } > +}; > + > const VMStateDescription vmstate_x86_cpu =3D { > .name =3D "cpu", > .version_id =3D 12, > @@ -571,6 +590,9 @@ const VMStateDescription vmstate_x86_cpu =3D { > }, { > .vmsd =3D &vmstate_msr_ia32_misc_enable, > .needed =3D misc_enable_needed, > + }, { > + .vmsd =3D &vmstate_msr_ia32_feature_control, > + .needed =3D feature_control_needed, > } , { > /* empty */ > } >=20 --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg