From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58550) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VCoLo-0007dm-Ox for qemu-devel@nongnu.org; Fri, 23 Aug 2013 06:12:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VCoLi-0000Mi-OI for qemu-devel@nongnu.org; Fri, 23 Aug 2013 06:12:16 -0400 Received: from mx1.redhat.com ([209.132.183.28]:32845) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VCoLi-0000Mb-D9 for qemu-devel@nongnu.org; Fri, 23 Aug 2013 06:12:10 -0400 Message-ID: <5217354B.4000204@redhat.com> Date: Fri, 23 Aug 2013 12:11:23 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: <1377250793-24027-1-git-send-email-pbonzini@redhat.com> <1377250793-24027-2-git-send-email-pbonzini@redhat.com> <52173531.5080602@suse.de> In-Reply-To: <52173531.5080602@suse.de> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PULL 1/9] Initialize IA32_FEATURE_CONTROL MSR in reset and migration List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?ISO-8859-15?Q?Andreas_F=E4rber?= Cc: gleb@redhat.com, Arthur Chunqi Li , qemu-devel@nongnu.org, anthony@codemonkey.ws Il 23/08/2013 12:10, Andreas F=E4rber ha scritto: > Am 23.08.2013 11:39, schrieb Paolo Bonzini: >> From: Arthur Chunqi Li >> >> The recent KVM patch adds IA32_FEATURE_CONTROL support. QEMU needs >> to clear this MSR when reset vCPU and keep the value of it when >> migration. This patch add this feature. >> >> Signed-off-by: Arthur Chunqi Li >> Signed-off-by: Gleb Natapov >> --- >> target-i386/cpu.h | 2 ++ >> target-i386/kvm.c | 4 ++++ >> target-i386/machine.c | 22 ++++++++++++++++++++++ >> 3 files changed, 28 insertions(+) >> >> diff --git a/target-i386/cpu.h b/target-i386/cpu.h >> index cedefdc..3a52f94 100644 >> --- a/target-i386/cpu.h >> +++ b/target-i386/cpu.h >> @@ -301,6 +301,7 @@ >> #define MSR_IA32_APICBASE_BSP (1<<8) >> #define MSR_IA32_APICBASE_ENABLE (1<<11) >> #define MSR_IA32_APICBASE_BASE (0xfffff<<12) >> +#define MSR_IA32_FEATURE_CONTROL 0x0000003a >> #define MSR_TSC_ADJUST 0x0000003b >> #define MSR_IA32_TSCDEADLINE 0x6e0 >> =20 >> @@ -813,6 +814,7 @@ typedef struct CPUX86State { >> =20 >> uint64_t mcg_status; >> uint64_t msr_ia32_misc_enable; >> + uint64_t msr_ia32_feature_control; >> =20 >> /* exception/interrupt handling */ >> int error_code; >> diff --git a/target-i386/kvm.c b/target-i386/kvm.c >> index 3c9d10a..84ac00a 100644 >> --- a/target-i386/kvm.c >> +++ b/target-i386/kvm.c >> @@ -1121,6 +1121,7 @@ static int kvm_put_msrs(X86CPU *cpu, int level) >> if (hyperv_vapic_recommended()) { >> kvm_msr_entry_set(&msrs[n++], HV_X64_MSR_APIC_ASSIST_PAGE= , 0); >> } >> + kvm_msr_entry_set(&msrs[n++], MSR_IA32_FEATURE_CONTROL, env->= msr_ia32_feature_control); >> } >> if (env->mcg_cap) { >> int i; >> @@ -1345,6 +1346,7 @@ static int kvm_get_msrs(X86CPU *cpu) >> if (has_msr_misc_enable) { >> msrs[n++].index =3D MSR_IA32_MISC_ENABLE; >> } >> + msrs[n++].index =3D MSR_IA32_FEATURE_CONTROL; >> =20 >> if (!env->tsc_valid) { >> msrs[n++].index =3D MSR_IA32_TSC; >> @@ -1443,6 +1445,8 @@ static int kvm_get_msrs(X86CPU *cpu) >> case MSR_IA32_MISC_ENABLE: >> env->msr_ia32_misc_enable =3D msrs[i].data; >> break; >> + case MSR_IA32_FEATURE_CONTROL: >> + env->msr_ia32_feature_control =3D msrs[i].data; >=20 > Shouldn't this patch be fixed to have the break that is being added in = 5/9? We try not to rebase uq/master unless there are conflicts that Anthony prefers not to handle. (I did that once and Gleb scolded me... :) perhaps I'll be wrong this time too...). Paolo