From: Richard Henderson <rth@twiddle.net>
To: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: james.hogan@imgtec.com, paul.burton@imgtec.com,
qemu-devel@nongnu.org, markos.chandras@imgtec.com,
leon.alrae@imgtec.com, aurelien@aurel32.net
Subject: Re: [Qemu-devel] [PATCH] mips_malta: support up to 2GiB RAM
Date: Mon, 26 Aug 2013 11:01:51 -0700 [thread overview]
Message-ID: <521B980F.4040208@twiddle.net> (raw)
In-Reply-To: <1377270586-14753-1-git-send-email-yongbok.kim@imgtec.com>
On 08/23/2013 08:09 AM, Yongbok Kim wrote:
> + /* alias for pre IO hole access */
> + memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram",
> + ram_high, 0, MIN(ram_size, (256 << 20)));
> + memory_region_add_subregion(system_memory, 0, ram_low_preio);
> +
> + /* alias for post IO hole access, if there is enough RAM */
> + if (ram_size > (512 << 20)) {
> + ram_low_postio = g_new(MemoryRegion, 1);
> + memory_region_init_alias(ram_low_postio, NULL,
> + "mips_malta_low_postio.ram",
> + ram_high, 512 << 20,
> + ram_size - (512 << 20));
> + memory_region_add_subregion(system_memory, 512 << 20, ram_low_postio);
> + }
This sort of thing is what subregion prioirities are for. Ideally you'd have
one alias region, with lower priority than the IO hole.
Of course, it looks like most of gt64xxx_pci.c needs cleaning up for proper
usage of the memory region infrastructure before that can happen...
r~
next prev parent reply other threads:[~2013-08-26 18:02 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-23 15:09 [Qemu-devel] [PATCH] mips_malta: support up to 2GiB RAM Yongbok Kim
2013-08-26 18:01 ` Richard Henderson [this message]
2013-08-27 8:45 ` Paul Burton
2013-08-27 14:54 ` Richard Henderson
2013-08-27 14:55 ` Richard Henderson
2013-08-27 15:01 ` Paul Burton
2013-08-28 16:44 ` Aurelien Jarno
2013-09-06 12:57 ` [Qemu-devel] [PATCH v2] " Paul Burton
2013-09-09 16:51 ` Aurelien Jarno
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