From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45645) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VEEuy-0000Xu-S9 for qemu-devel@nongnu.org; Tue, 27 Aug 2013 04:46:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VEEur-0002tc-Hh for qemu-devel@nongnu.org; Tue, 27 Aug 2013 04:46:28 -0400 Received: from mail-we0-f170.google.com ([74.125.82.170]:51598) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VEEur-0002tW-Bb for qemu-devel@nongnu.org; Tue, 27 Aug 2013 04:46:21 -0400 Received: by mail-we0-f170.google.com with SMTP id w62so3722116wes.1 for ; Tue, 27 Aug 2013 01:45:45 -0700 (PDT) Sender: Paolo Bonzini Message-ID: <521C6730.8080707@redhat.com> Date: Tue, 27 Aug 2013 10:45:36 +0200 From: Paolo Bonzini MIME-Version: 1.0 References: <1377591046-1944-1-git-send-email-pingfank@linux.vnet.ibm.com> <1377591046-1944-3-git-send-email-pingfank@linux.vnet.ibm.com> In-Reply-To: <1377591046-1944-3-git-send-email-pingfank@linux.vnet.ibm.com> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2 3/3] hpet: entitle more irq pins for hpet List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Liu Ping Fan Cc: Jan Kiszka , qemu-devel@nongnu.org, Anthony Liguori Il 27/08/2013 10:10, Liu Ping Fan ha scritto: > On q35 machine, IRQ2/8 can be reserved for hpet timer 0/1. And pin 16~23 > of ioapic can be dynamically assigned to hpet as guest chooses. First of all, the backwards-compatible q35 machines should also use the old value. Second, the HPET should _not_ know the machine types. You need to add a qdev property as I suggested in my reply to v1. The default value should be 0xFF0104. Then you can add the compatibility value in hw/i386/pc_piix.c and hw/i386/pc_q35.c. Paolo > Signed-off-by: Liu Ping Fan > --- > hw/timer/hpet.c | 14 ++++++++++++-- > 1 file changed, 12 insertions(+), 2 deletions(-) > > diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c > index 1139448..92cd4fa 100644 > --- a/hw/timer/hpet.c > +++ b/hw/timer/hpet.c > @@ -25,6 +25,7 @@ > */ > > #include "hw/hw.h" > +#include "hw/boards.h" > #include "hw/i386/pc.h" > #include "ui/console.h" > #include "qemu/timer.h" > @@ -42,6 +43,11 @@ > > #define HPET_MSI_SUPPORT 0 > > +/* only IRQ2 allowed for pc-1.6 and former */ > +#define HPET_TN_INT_CAP_PC (0x4ULL << 32) > +/* Hpet can use non-legacy IRQ16~23, and an IRQ2 ,IRQ8 */ > +#define HPET_TN_INT_CAP_Q35 (0xff0104ULL << 32) > + > #define TYPE_HPET "hpet" > #define HPET(obj) OBJECT_CHECK(HPETState, (obj), TYPE_HPET) > > @@ -663,8 +669,12 @@ static void hpet_reset(DeviceState *d) > if (s->flags & (1 << HPET_MSI_SUPPORT)) { > timer->config |= HPET_TN_FSB_CAP; > } > - /* advertise availability of ioapic inti2 */ > - timer->config |= 0x00000004ULL << 32; > + /* advertise availability of ioapic int */ > + if (qemu_check_machine("pc-q35")) { > + timer->config |= HPET_TN_INT_CAP_Q35; > + } else { > + timer->config |= HPET_TN_INT_CAP_PC; > + } > timer->period = 0ULL; > timer->wrap_flag = 0; > } >