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Date: Wed, 28 Aug 2013 17:19:44 +0200
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Subject: Re: [Qemu-devel] [PATCH qom-cpu/arm-devs] hw/cpu/a15mpcore: Use
 qemu_get_cpu() for generic timers
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To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>, Paul Brook <paul@codesourcery.com>

Am 21.08.2013 18:45, schrieb Andreas F=C3=A4rber:
> This simplifies the loop and aids with refactoring of CPU list.
>=20
> Requested-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Andreas F=C3=A4rber <afaerber@suse.de>
> ---
>  hw/cpu/a15mpcore.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)

Seeing no objection or pick-up from PMM I've applied this to qom-cpu
now, to move forward with CPU list refactoring.

https://github.com/afaerber/qemu-cpu/commits/qom-cpu

Andreas

>=20
> diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c
> index af182da..9abba67 100644
> --- a/hw/cpu/a15mpcore.c
> +++ b/hw/cpu/a15mpcore.c
> @@ -50,7 +50,6 @@ static int a15mp_priv_init(SysBusDevice *dev)
>      SysBusDevice *busdev;
>      const char *gictype =3D "arm_gic";
>      int i;
> -    CPUState *cpu;
> =20
>      if (kvm_irqchip_in_kernel()) {
>          gictype =3D "kvm-arm-gic";
> @@ -72,8 +71,8 @@ static int a15mp_priv_init(SysBusDevice *dev)
>      /* Wire the outputs from each CPU's generic timer to the
>       * appropriate GIC PPI inputs
>       */
> -    for (i =3D 0, cpu =3D first_cpu; i < s->num_cpu; i++, cpu =3D cpu-=
>next_cpu) {
> -        DeviceState *cpudev =3D DEVICE(cpu);
> +    for (i =3D 0; i < s->num_cpu; i++) {
> +        DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i));
>          int ppibase =3D s->num_irq - 32 + i * 32;
>          /* physical timer; we wire it up to the non-secure timer's ID,
>           * since a real A15 always has TrustZone but QEMU doesn't.
>=20


--=20
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