From: Paolo Bonzini <pbonzini@redhat.com>
To: Oleksandr Tymoshenko <gonzo@bluezbox.com>
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] PCNet-PCI I/O ops byte order
Date: Fri, 30 Aug 2013 07:57:28 +0200 [thread overview]
Message-ID: <52203448.1080101@redhat.com> (raw)
In-Reply-To: <4C818617-784B-4685-B98C-44E9AFFBD8B8@bluezbox.com>
Il 29/08/2013 22:56, Oleksandr Tymoshenko ha scritto:
> Hello,
>
> I'm working on QEMU/mips support for FreeBSD. qemu-system-mipsel works
> just fine but I ran into a problem with qemu-system-mips. There are two
> devices on PCI bus in MALTA machine emulation. ATA IDE controller and
> PCNet NIC: hw/ide/pci.c and hw/net/pcnet-pci.c respectively. Problem is
> I/O ops byte order for these two devices are defined inconsistently.
> It's DEVICE_LITTLE_ENDIAN for bmdma_addr_ioport_ops and
> DEVICE_NATIVE_ENDIAN for pcnet_io_ops. And since byte swapping
> in my case performed by bus driver I can't get consistent behaviour
> for these devices on big-endian system.
>
> I don't have real hardware to run my code on but shouldn't all devices
> on PCI bus treat words as little endian?
>
> Thank you
Yes, you are right. Aurelien Jarno just posted a patch to use
DEVICE_LITTLE_ENDIAN for pcnet_io_ops.
Paolo
prev parent reply other threads:[~2013-08-30 5:57 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-29 20:56 [Qemu-devel] PCNet-PCI I/O ops byte order Oleksandr Tymoshenko
2013-08-30 5:57 ` Paolo Bonzini [this message]
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