From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35026) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VLeDH-00057u-M0 for qemu-devel@nongnu.org; Mon, 16 Sep 2013 15:12:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VLeD9-00057y-8v for qemu-devel@nongnu.org; Mon, 16 Sep 2013 15:11:59 -0400 Received: from mail-ie0-x229.google.com ([2607:f8b0:4001:c03::229]:62457) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VLeD9-00057o-3U for qemu-devel@nongnu.org; Mon, 16 Sep 2013 15:11:51 -0400 Received: by mail-ie0-f169.google.com with SMTP id tp5so8285558ieb.14 for ; Mon, 16 Sep 2013 12:11:50 -0700 (PDT) Sender: Richard Henderson Message-ID: <523757F2.1030003@twiddle.net> Date: Mon, 16 Sep 2013 12:11:46 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1379195690-6509-1-git-send-email-rth@twiddle.net> <1379195690-6509-9-git-send-email-rth@twiddle.net> <5236C44C.7060405@huawei.com> <52372479.3080807@twiddle.net> In-Reply-To: <52372479.3080807@twiddle.net> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v4 08/33] tcg-aarch64: Introduce tcg_fmt_Rdnm and tcg_fmt_Rdnm_lsl List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Claudio Fontana Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org On 09/16/2013 08:32 AM, Richard Henderson wrote: > Nor do we provide ASR or ROR shifts; should we provide those too? Please think > about what situations in which those would be useful. Also think about the one > operation at a time nature of TCG. > > My guess is that, beyond the one explicit use in the tlb, we could only make > use of shifted operations if TCG grew some sort of peephole optimizer so that > we can look across single operations. And I don't ever see that happening. > > Therefore I think adding LSR, ASR and ROR shifts is both a waste of time and > bloats the backend. Unless: one decides NOT to use the alias definitions in the manual: LSR d, n, shift => UBFM d, n, shift, 63 LSL d, n, shift => UBFM d, n, 64 - shift, 63 - shift ASR d, n, shift => SBFN d, n, shift, 63 ROR d, n, shift => EXTR d, n, n, shift and instead use LSR d, n, shift => ORR d, xzr, n, lsr #shift LSL d, n, shift => ORR d, xzr, n, lsl #shift ASR d, n, shift => ORR d, xzr, n, asr #shift ROR d, n, shift => ORR d, xzr, n, ror #shift It's not implausible that using the same (base) insn for all of these could result in more code sharing and therefore smaller code size within the tcg backend. r~ PS: All rather academic, but considering that AArch64 ORR (shifted register) is the preferred implementation for MOV, and AArch32 MOV (shifted register) is the preferred implementation for shift immediates, I'm actually surprised that: there is no AArch64 MOV (shifted register) alias for AArch32 compatibility, and that ORR isn't the preferred implementation of shift immediates for AArch64.