* [Qemu-devel] [RFC qom-cpu 01/41] cpu: Turn cpu_has_work() into a CPUClass hook
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
@ 2013-09-04 9:04 ` Andreas Färber
2013-09-04 12:41 ` Jia Liu
2014-02-05 18:51 ` Andreas Färber
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 02/41] cpu: Turn cpu_mmu_index() " Andreas Färber
` (42 subsequent siblings)
43 siblings, 2 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:04 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Anthony Green, Alexander Graf, Blue Swirl,
Max Filippov, Michael Walle, open list:PowerPC, Paul Brook,
Edgar E. Iglesias, Guan Xuetao, Andreas Färber,
Aurelien Jarno, Richard Henderson
Default to false.
Tidy variable naming and inline cast uses while at it.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cpu-exec.c | 5 -----
cpus.c | 2 +-
include/qom/cpu.h | 12 ++++++++++--
qom/cpu.c | 6 ++++++
target-alpha/cpu.c | 16 ++++++++++++++++
target-alpha/cpu.h | 15 ---------------
target-arm/cpu.c | 7 +++++++
target-arm/cpu.h | 6 ------
target-cris/cpu.c | 6 ++++++
target-cris/cpu.h | 5 -----
target-i386/cpu.c | 15 +++++++++++++++
target-i386/cpu.h | 14 --------------
target-lm32/cpu.c | 6 ++++++
target-lm32/cpu.h | 5 -----
target-m68k/cpu.c | 6 ++++++
target-m68k/cpu.h | 5 -----
target-microblaze/cpu.c | 6 ++++++
target-microblaze/cpu.h | 5 -----
target-mips/cpu.c | 30 ++++++++++++++++++++++++++++++
target-mips/cpu.h | 28 ----------------------------
target-moxie/cpu.c | 6 ++++++
target-moxie/cpu.h | 5 -----
target-openrisc/cpu.c | 7 +++++++
target-openrisc/cpu.h | 5 -----
target-ppc/cpu.h | 8 --------
target-ppc/translate_init.c | 9 +++++++++
target-s390x/cpu.c | 10 ++++++++++
target-s390x/cpu.h | 9 ---------
target-sh4/cpu.c | 6 ++++++
target-sh4/cpu.h | 5 -----
target-sparc/cpu.c | 10 ++++++++++
target-sparc/cpu.h | 9 ---------
target-unicore32/cpu.c | 7 +++++++
target-unicore32/cpu.h | 6 ------
target-xtensa/cpu.c | 8 ++++++++
target-xtensa/cpu.h | 7 -------
36 files changed, 172 insertions(+), 145 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 5a43995..e9866b8 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -23,11 +23,6 @@
#include "qemu/atomic.h"
#include "sysemu/qtest.h"
-bool qemu_cpu_has_work(CPUState *cpu)
-{
- return cpu_has_work(cpu);
-}
-
void cpu_loop_exit(CPUArchState *env)
{
CPUState *cpu = ENV_GET_CPU(env);
diff --git a/cpus.c b/cpus.c
index e566297..5acb98b 100644
--- a/cpus.c
+++ b/cpus.c
@@ -75,7 +75,7 @@ static bool cpu_thread_is_idle(CPUState *cpu)
if (cpu_is_stopped(cpu)) {
return true;
}
- if (!cpu->halted || qemu_cpu_has_work(cpu) ||
+ if (!cpu->halted || cpu_has_work(cpu) ||
kvm_halt_in_kernel()) {
return false;
}
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 7739e00..4d022c3 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -69,6 +69,7 @@ struct TranslationBlock;
* instantiatable CPU type.
* @reset: Callback to reset the #CPUState to its initial state.
* @reset_dump_flags: #CPUDumpFlags to use for reset logging.
+ * @has_work: Callback for checking if there is work to do.
* @do_interrupt: Callback for interrupt handling.
* @do_unassigned_access: Callback for unassigned access handling.
* @memory_rw_debug: Callback for GDB memory access.
@@ -98,6 +99,7 @@ typedef struct CPUClass {
void (*reset)(CPUState *cpu);
int reset_dump_flags;
+ bool (*has_work)(CPUState *cpu);
void (*do_interrupt)(CPUState *cpu);
CPUUnassignedAccess do_unassigned_access;
int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
@@ -344,14 +346,20 @@ void cpu_reset(CPUState *cpu);
ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
/**
- * qemu_cpu_has_work:
+ * cpu_has_work:
* @cpu: The vCPU to check.
*
* Checks whether the CPU has work to do.
*
* Returns: %true if the CPU has work, %false otherwise.
*/
-bool qemu_cpu_has_work(CPUState *cpu);
+static inline bool cpu_has_work(CPUState *cpu)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ g_assert(cc->has_work);
+ return cc->has_work(cpu);
+}
/**
* qemu_cpu_is_self:
diff --git a/qom/cpu.c b/qom/cpu.c
index fa7ec6b..c71fa35 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -200,6 +200,11 @@ static void cpu_common_reset(CPUState *cpu)
cpu->halted = 0;
}
+static bool cpu_common_has_work(CPUState *cs)
+{
+ return false;
+}
+
ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
{
CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
@@ -244,6 +249,7 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->class_by_name = cpu_common_class_by_name;
k->reset = cpu_common_reset;
k->get_arch_id = cpu_common_get_arch_id;
+ k->has_work = cpu_common_has_work;
k->get_paging_enabled = cpu_common_get_paging_enabled;
k->get_memory_mapping = cpu_common_get_memory_mapping;
k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index cfad2ea..053afa2 100644
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -31,6 +31,21 @@ static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static bool alpha_cpu_has_work(CPUState *cs)
+{
+ /* Here we are checking to see if the CPU should wake up from HALT.
+ We will have gotten into this state only for WTINT from PALmode. */
+ /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
+ asleep even if (some) interrupts have been asserted. For now,
+ assume that if a CPU really wants to stay asleep, it will mask
+ interrupts at the chipset level, which will prevent these bits
+ from being set in the first place. */
+ return cs->interrupt_request & (CPU_INTERRUPT_HARD
+ | CPU_INTERRUPT_TIMER
+ | CPU_INTERRUPT_SMP
+ | CPU_INTERRUPT_MCHK);
+}
+
static void alpha_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
@@ -271,6 +286,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
dc->realize = alpha_cpu_realizefn;
cc->class_by_name = alpha_cpu_class_by_name;
+ cc->has_work = alpha_cpu_has_work;
cc->do_interrupt = alpha_cpu_do_interrupt;
cc->dump_state = alpha_cpu_dump_state;
cc->set_pc = alpha_cpu_set_pc;
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index c85dc6e..a172124 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -498,21 +498,6 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
*pflags = flags;
}
-static inline bool cpu_has_work(CPUState *cpu)
-{
- /* Here we are checking to see if the CPU should wake up from HALT.
- We will have gotten into this state only for WTINT from PALmode. */
- /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
- asleep even if (some) interrupts have been asserted. For now,
- assume that if a CPU really wants to stay asleep, it will mask
- interrupts at the chipset level, which will prevent these bits
- from being set in the first place. */
- return cpu->interrupt_request & (CPU_INTERRUPT_HARD
- | CPU_INTERRUPT_TIMER
- | CPU_INTERRUPT_SMP
- | CPU_INTERRUPT_MCHK);
-}
-
#include "exec/exec-all.h"
#endif /* !defined (__CPU_ALPHA_H__) */
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index b2556c6..f38c851 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -34,6 +34,12 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.regs[15] = value;
}
+static bool arm_cpu_has_work(CPUState *cs)
+{
+ return cs->interrupt_request &
+ (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
+}
+
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
{
/* Reset a single ARMCPRegInfo register */
@@ -890,6 +896,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->reset = arm_cpu_reset;
cc->class_by_name = arm_cpu_class_by_name;
+ cc->has_work = arm_cpu_has_work;
cc->do_interrupt = arm_cpu_do_interrupt;
cc->dump_state = arm_cpu_dump_state;
cc->set_pc = arm_cpu_set_pc;
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index f2abdf3..a42822b 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -814,12 +814,6 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
}
}
-static inline bool cpu_has_work(CPUState *cpu)
-{
- return cpu->interrupt_request &
- (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
-}
-
#include "exec/exec-all.h"
/* Load an instruction and return it in the standard little-endian order */
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index 44301a4..998cded 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -33,6 +33,11 @@ static void cris_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static bool cris_cpu_has_work(CPUState *cs)
+{
+ return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
+}
+
/* CPUClass::reset() */
static void cris_cpu_reset(CPUState *s)
{
@@ -257,6 +262,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->reset = cris_cpu_reset;
cc->class_by_name = cris_cpu_class_by_name;
+ cc->has_work = cris_cpu_has_work;
cc->do_interrupt = cris_cpu_do_interrupt;
cc->dump_state = cris_cpu_dump_state;
cc->set_pc = cris_cpu_set_pc;
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 4b9fc4c..15a0497 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -272,11 +272,6 @@ static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
#define cpu_list cris_cpu_list
void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
-static inline bool cpu_has_work(CPUState *cpu)
-{
- return cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
-}
-
#include "exec/exec-all.h"
#endif
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index c36345e..fa92950 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2676,6 +2676,20 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
cpu->env.eip = tb->pc - tb->cs_base;
}
+static bool x86_cpu_has_work(CPUState *cs)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
+ return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
+ CPU_INTERRUPT_POLL)) &&
+ (env->eflags & IF_MASK)) ||
+ (cs->interrupt_request & (CPU_INTERRUPT_NMI |
+ CPU_INTERRUPT_INIT |
+ CPU_INTERRUPT_SIPI |
+ CPU_INTERRUPT_MCE));
+}
+
static Property x86_cpu_properties[] = {
DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
DEFINE_PROP_END_OF_LIST()
@@ -2696,6 +2710,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->reset = x86_cpu_reset;
cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
+ cc->has_work = x86_cpu_has_work;
cc->do_interrupt = x86_cpu_do_interrupt;
cc->dump_state = x86_cpu_dump_state;
cc->set_pc = x86_cpu_set_pc;
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 5723eff..6d46c75 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1161,20 +1161,6 @@ void optimize_flags_init(void);
#include "hw/i386/apic.h"
#endif
-static inline bool cpu_has_work(CPUState *cs)
-{
- X86CPU *cpu = X86_CPU(cs);
- CPUX86State *env = &cpu->env;
-
- return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
- CPU_INTERRUPT_POLL)) &&
- (env->eflags & IF_MASK)) ||
- (cs->interrupt_request & (CPU_INTERRUPT_NMI |
- CPU_INTERRUPT_INIT |
- CPU_INTERRUPT_SIPI |
- CPU_INTERRUPT_MCE));
-}
-
#include "exec/exec-all.h"
static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
index 869878c..4fa8605 100644
--- a/target-lm32/cpu.c
+++ b/target-lm32/cpu.c
@@ -29,6 +29,11 @@ static void lm32_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static bool lm32_cpu_has_work(CPUState *cs)
+{
+ return cs->interrupt_request & CPU_INTERRUPT_HARD;
+}
+
/* CPUClass::reset() */
static void lm32_cpu_reset(CPUState *s)
{
@@ -86,6 +91,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
lcc->parent_reset = cc->reset;
cc->reset = lm32_cpu_reset;
+ cc->has_work = lm32_cpu_has_work;
cc->do_interrupt = lm32_cpu_do_interrupt;
cc->dump_state = lm32_cpu_dump_state;
cc->set_pc = lm32_cpu_set_pc;
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index dbfe043..a251a02 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -225,11 +225,6 @@ static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *pc,
*flags = 0;
}
-static inline bool cpu_has_work(CPUState *cpu)
-{
- return cpu->interrupt_request & CPU_INTERRUPT_HARD;
-}
-
#include "exec/exec-all.h"
#endif
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index 008d8db..7d66ed0 100644
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -30,6 +30,11 @@ static void m68k_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static bool m68k_cpu_has_work(CPUState *cs)
+{
+ return cs->interrupt_request & CPU_INTERRUPT_HARD;
+}
+
static void m68k_set_feature(CPUM68KState *env, int feature)
{
env->features |= (1u << feature);
@@ -189,6 +194,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->reset = m68k_cpu_reset;
cc->class_by_name = m68k_cpu_class_by_name;
+ cc->has_work = m68k_cpu_has_work;
cc->do_interrupt = m68k_cpu_do_interrupt;
cc->dump_state = m68k_cpu_dump_state;
cc->set_pc = m68k_cpu_set_pc;
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index cfd6846..5f79d2a 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -253,11 +253,6 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
| ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
}
-static inline bool cpu_has_work(CPUState *cpu)
-{
- return cpu->interrupt_request & CPU_INTERRUPT_HARD;
-}
-
#include "exec/exec-all.h"
#endif
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 0ef9aa4..6104939 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -33,6 +33,11 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.sregs[SR_PC] = value;
}
+static bool mb_cpu_has_work(CPUState *cs)
+{
+ return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
+}
+
/* CPUClass::reset() */
static void mb_cpu_reset(CPUState *s)
{
@@ -139,6 +144,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
mcc->parent_reset = cc->reset;
cc->reset = mb_cpu_reset;
+ cc->has_work = mb_cpu_has_work;
cc->do_interrupt = mb_cpu_do_interrupt;
cc->dump_state = mb_cpu_dump_state;
cc->set_pc = mb_cpu_set_pc;
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 7508cf5..23f96f8 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -358,11 +358,6 @@ void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
unsigned size);
#endif
-static inline bool cpu_has_work(CPUState *cpu)
-{
- return cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
-}
-
#include "exec/exec-all.h"
#endif
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index 9dd47e8..0a2dc46 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -45,6 +45,35 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
}
+static bool mips_cpu_has_work(CPUState *cs)
+{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+ bool has_work = false;
+
+ /* It is implementation dependent if non-enabled interrupts
+ wake-up the CPU, however most of the implementations only
+ check for interrupts that can be taken. */
+ if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
+ cpu_mips_hw_interrupts_pending(env)) {
+ has_work = true;
+ }
+
+ /* MIPS-MT has the ability to halt the CPU. */
+ if (env->CP0_Config3 & (1 << CP0C3_MT)) {
+ /* The QEMU model will issue an _WAKE request whenever the CPUs
+ should be woken up. */
+ if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
+ has_work = true;
+ }
+
+ if (!mips_vpe_active(env)) {
+ has_work = false;
+ }
+ }
+ return has_work;
+}
+
/* CPUClass::reset() */
static void mips_cpu_reset(CPUState *s)
{
@@ -97,6 +126,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
mcc->parent_reset = cc->reset;
cc->reset = mips_cpu_reset;
+ cc->has_work = mips_cpu_has_work;
cc->do_interrupt = mips_cpu_do_interrupt;
cc->dump_state = mips_cpu_dump_state;
cc->set_pc = mips_cpu_set_pc;
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index a29c82f..dff2836 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -702,34 +702,6 @@ static inline int mips_vpe_active(CPUMIPSState *env)
return active;
}
-static inline bool cpu_has_work(CPUState *cpu)
-{
- CPUMIPSState *env = &MIPS_CPU(cpu)->env;
- bool has_work = false;
-
- /* It is implementation dependent if non-enabled interrupts
- wake-up the CPU, however most of the implementations only
- check for interrupts that can be taken. */
- if ((cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
- cpu_mips_hw_interrupts_pending(env)) {
- has_work = true;
- }
-
- /* MIPS-MT has the ability to halt the CPU. */
- if (env->CP0_Config3 & (1 << CP0C3_MT)) {
- /* The QEMU model will issue an _WAKE request whenever the CPUs
- should be woken up. */
- if (cpu->interrupt_request & CPU_INTERRUPT_WAKE) {
- has_work = true;
- }
-
- if (!mips_vpe_active(env)) {
- has_work = false;
- }
- }
- return has_work;
-}
-
#include "exec/exec-all.h"
static inline void compute_hflags(CPUMIPSState *env)
diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
index d97a091..66f337e 100644
--- a/target-moxie/cpu.c
+++ b/target-moxie/cpu.c
@@ -29,6 +29,11 @@ static void moxie_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static bool moxie_cpu_has_work(CPUState *cs)
+{
+ return cs->interrupt_request & CPU_INTERRUPT_HARD;
+}
+
static void moxie_cpu_reset(CPUState *s)
{
MoxieCPU *cpu = MOXIE_CPU(s);
@@ -99,6 +104,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->class_by_name = moxie_cpu_class_by_name;
+ cc->has_work = moxie_cpu_has_work;
cc->do_interrupt = moxie_cpu_do_interrupt;
cc->dump_state = moxie_cpu_dump_state;
cc->set_pc = moxie_cpu_set_pc;
diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h
index 5ce14b5..778cfc0 100644
--- a/target-moxie/cpu.h
+++ b/target-moxie/cpu.h
@@ -152,11 +152,6 @@ static inline void cpu_get_tb_cpu_state(CPUMoxieState *env, target_ulong *pc,
*flags = 0;
}
-static inline int cpu_has_work(CPUState *cpu)
-{
- return cpu->interrupt_request & CPU_INTERRUPT_HARD;
-}
-
int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address,
int rw, int mmu_idx);
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 075f00a..ca8495f 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -27,6 +27,12 @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static bool openrisc_cpu_has_work(CPUState *cs)
+{
+ return cs->interrupt_request & (CPU_INTERRUPT_HARD |
+ CPU_INTERRUPT_TIMER);
+}
+
/* CPUClass::reset() */
static void openrisc_cpu_reset(CPUState *s)
{
@@ -153,6 +159,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->reset = openrisc_cpu_reset;
cc->class_by_name = openrisc_cpu_class_by_name;
+ cc->has_work = openrisc_cpu_has_work;
cc->do_interrupt = openrisc_cpu_do_interrupt;
cc->dump_state = openrisc_cpu_dump_state;
cc->set_pc = openrisc_cpu_set_pc;
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 8fd0bc0..4a27f22 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -418,11 +418,6 @@ static inline int cpu_mmu_index(CPUOpenRISCState *env)
}
#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
-static inline bool cpu_has_work(CPUState *cpu)
-{
- return cpu->interrupt_request & (CPU_INTERRUPT_HARD |
- CPU_INTERRUPT_TIMER);
-}
#include "exec/exec-all.h"
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 422a6bb..70c1ef5 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -2134,14 +2134,6 @@ static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
-static inline bool cpu_has_work(CPUState *cpu)
-{
- PowerPCCPU *ppc_cpu = POWERPC_CPU(cpu);
- CPUPPCState *env = &ppc_cpu->env;
-
- return msr_ee && (cpu->interrupt_request & CPU_INTERRUPT_HARD);
-}
-
#include "exec/exec-all.h"
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index d2645ba..b552451 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8437,6 +8437,14 @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.nip = value;
}
+static bool ppc_cpu_has_work(CPUState *cs)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
+
+ return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
+}
+
/* CPUClass::reset() */
static void ppc_cpu_reset(CPUState *s)
{
@@ -8561,6 +8569,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->reset = ppc_cpu_reset;
cc->class_by_name = ppc_cpu_class_by_name;
+ cc->has_work = ppc_cpu_has_work;
cc->do_interrupt = ppc_cpu_do_interrupt;
cc->dump_state = ppc_cpu_dump_state;
cc->dump_statistics = ppc_cpu_dump_statistics;
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index 3c89f8a..a4c7a33 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -65,6 +65,15 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.psw.addr = value;
}
+static bool s390_cpu_has_work(CPUState *cs)
+{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
+
+ return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
+ (env->psw.mask & PSW_MASK_EXT);
+}
+
#if !defined(CONFIG_USER_ONLY)
/* S390CPUClass::load_normal() */
static void s390_cpu_load_normal(CPUState *s)
@@ -217,6 +226,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
scc->cpu_reset = s390_cpu_reset;
scc->initial_cpu_reset = s390_cpu_initial_reset;
cc->reset = s390_cpu_full_reset;
+ cc->has_work = s390_cpu_has_work;
cc->do_interrupt = s390_cpu_do_interrupt;
cc->dump_state = s390_cpu_dump_state;
cc->set_pc = s390_cpu_set_pc;
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index 8be5648..3b588af 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -1036,15 +1036,6 @@ static inline void cpu_inject_crw_mchk(S390CPU *cpu)
cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
}
-static inline bool cpu_has_work(CPUState *cpu)
-{
- S390CPU *s390_cpu = S390_CPU(cpu);
- CPUS390XState *env = &s390_cpu->env;
-
- return (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
- (env->psw.mask & PSW_MASK_EXT);
-}
-
/* fpu_helper.c */
uint32_t set_cc_nz_f32(float32 v);
uint32_t set_cc_nz_f64(float64 v);
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index 34b2b57..5bf6d9f 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -39,6 +39,11 @@ static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
cpu->env.flags = tb->flags;
}
+static bool superh_cpu_has_work(CPUState *cs)
+{
+ return cs->interrupt_request & CPU_INTERRUPT_HARD;
+}
+
/* CPUClass::reset() */
static void superh_cpu_reset(CPUState *s)
{
@@ -283,6 +288,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->reset = superh_cpu_reset;
cc->class_by_name = superh_cpu_class_by_name;
+ cc->has_work = superh_cpu_has_work;
cc->do_interrupt = superh_cpu_do_interrupt;
cc->dump_state = superh_cpu_dump_state;
cc->set_pc = superh_cpu_set_pc;
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 276d295..2eafc2d 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -352,11 +352,6 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
| (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
}
-static inline bool cpu_has_work(CPUState *cpu)
-{
- return cpu->interrupt_request & CPU_INTERRUPT_HARD;
-}
-
#include "exec/exec-all.h"
#endif /* _CPU_SH4_H */
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index 47ce60d..ede2c80 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -739,6 +739,15 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
cpu->env.npc = tb->cs_base;
}
+static bool sparc_cpu_has_work(CPUState *cs)
+{
+ SPARCCPU *cpu = SPARC_CPU(cs);
+ CPUSPARCState *env = &cpu->env;
+
+ return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
+ cpu_interrupts_enabled(env);
+}
+
static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
{
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
@@ -782,6 +791,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
scc->parent_reset = cc->reset;
cc->reset = sparc_cpu_reset;
+ cc->has_work = sparc_cpu_has_work;
cc->do_interrupt = sparc_cpu_do_interrupt;
cc->dump_state = sparc_cpu_dump_state;
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 41194ec..adf6557 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -747,15 +747,6 @@ static inline bool tb_am_enabled(int tb_flags)
#endif
}
-static inline bool cpu_has_work(CPUState *cpu)
-{
- SPARCCPU *sparc_cpu = SPARC_CPU(cpu);
- CPUSPARCState *env1 = &sparc_cpu->env;
-
- return (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
- cpu_interrupts_enabled(env1);
-}
-
#include "exec/exec-all.h"
#endif
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index 3f78208..1cfe50a 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -23,6 +23,12 @@ static void uc32_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.regs[31] = value;
}
+static bool uc32_cpu_has_work(CPUState *cs)
+{
+ return cs->interrupt_request &
+ (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
+}
+
static inline void set_feature(CPUUniCore32State *env, int feature)
{
env->features |= feature;
@@ -138,6 +144,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
dc->realize = uc32_cpu_realizefn;
cc->class_by_name = uc32_cpu_class_by_name;
+ cc->has_work = uc32_cpu_has_work;
cc->do_interrupt = uc32_cpu_do_interrupt;
cc->dump_state = uc32_cpu_dump_state;
cc->set_pc = uc32_cpu_set_pc;
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index 967511e..1db7419 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -160,10 +160,4 @@ static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc
void uc32_translate_init(void);
void switch_mode(CPUUniCore32State *, int);
-static inline bool cpu_has_work(CPUState *cpu)
-{
- return cpu->interrupt_request &
- (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
-}
-
#endif /* QEMU_UNICORE32_CPU_H */
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
index c19d17a..46573c6 100644
--- a/target-xtensa/cpu.c
+++ b/target-xtensa/cpu.c
@@ -40,6 +40,13 @@ static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static bool xtensa_cpu_has_work(CPUState *cs)
+{
+ XtensaCPU *cpu = XTENSA_CPU(cs);
+
+ return cpu->env.pending_irq_level;
+}
+
/* CPUClass::reset() */
static void xtensa_cpu_reset(CPUState *s)
{
@@ -132,6 +139,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->reset = xtensa_cpu_reset;
cc->class_by_name = xtensa_cpu_class_by_name;
+ cc->has_work = xtensa_cpu_has_work;
cc->do_interrupt = xtensa_cpu_do_interrupt;
cc->dump_state = xtensa_cpu_dump_state;
cc->set_pc = xtensa_cpu_set_pc;
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 95103e9..de27c8c 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -519,11 +519,4 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
#include "exec/cpu-all.h"
#include "exec/exec-all.h"
-static inline int cpu_has_work(CPUState *cpu)
-{
- CPUXtensaState *env = &XTENSA_CPU(cpu)->env;
-
- return env->pending_irq_level;
-}
-
#endif
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 01/41] cpu: Turn cpu_has_work() into a CPUClass hook
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 01/41] cpu: Turn cpu_has_work() into a CPUClass hook Andreas Färber
@ 2013-09-04 12:41 ` Jia Liu
2014-02-05 18:51 ` Andreas Färber
1 sibling, 0 replies; 68+ messages in thread
From: Jia Liu @ 2013-09-04 12:41 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Anthony Green, qemu-devel@nongnu.org,
Alexander Graf, Blue Swirl, Max Filippov, Michael Walle,
open list:PowerPC, Paul Brook, Edgar E. Iglesias, Guan Xuetao,
Aurelien Jarno, Richard Henderson
On Wed, Sep 4, 2013 at 5:04 PM, Andreas Färber <afaerber@suse.de> wrote:
> Default to false.
>
> Tidy variable naming and inline cast uses while at it.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
> cpu-exec.c | 5 -----
> cpus.c | 2 +-
> include/qom/cpu.h | 12 ++++++++++--
> qom/cpu.c | 6 ++++++
> target-alpha/cpu.c | 16 ++++++++++++++++
> target-alpha/cpu.h | 15 ---------------
> target-arm/cpu.c | 7 +++++++
> target-arm/cpu.h | 6 ------
> target-cris/cpu.c | 6 ++++++
> target-cris/cpu.h | 5 -----
> target-i386/cpu.c | 15 +++++++++++++++
> target-i386/cpu.h | 14 --------------
> target-lm32/cpu.c | 6 ++++++
> target-lm32/cpu.h | 5 -----
> target-m68k/cpu.c | 6 ++++++
> target-m68k/cpu.h | 5 -----
> target-microblaze/cpu.c | 6 ++++++
> target-microblaze/cpu.h | 5 -----
> target-mips/cpu.c | 30 ++++++++++++++++++++++++++++++
> target-mips/cpu.h | 28 ----------------------------
> target-moxie/cpu.c | 6 ++++++
> target-moxie/cpu.h | 5 -----
> target-openrisc/cpu.c | 7 +++++++
> target-openrisc/cpu.h | 5 -----
> target-ppc/cpu.h | 8 --------
> target-ppc/translate_init.c | 9 +++++++++
> target-s390x/cpu.c | 10 ++++++++++
> target-s390x/cpu.h | 9 ---------
> target-sh4/cpu.c | 6 ++++++
> target-sh4/cpu.h | 5 -----
> target-sparc/cpu.c | 10 ++++++++++
> target-sparc/cpu.h | 9 ---------
> target-unicore32/cpu.c | 7 +++++++
> target-unicore32/cpu.h | 6 ------
> target-xtensa/cpu.c | 8 ++++++++
> target-xtensa/cpu.h | 7 -------
> 36 files changed, 172 insertions(+), 145 deletions(-)
>
> diff --git a/cpu-exec.c b/cpu-exec.c
> index 5a43995..e9866b8 100644
> --- a/cpu-exec.c
> +++ b/cpu-exec.c
> @@ -23,11 +23,6 @@
> #include "qemu/atomic.h"
> #include "sysemu/qtest.h"
>
> -bool qemu_cpu_has_work(CPUState *cpu)
> -{
> - return cpu_has_work(cpu);
> -}
> -
> void cpu_loop_exit(CPUArchState *env)
> {
> CPUState *cpu = ENV_GET_CPU(env);
> diff --git a/cpus.c b/cpus.c
> index e566297..5acb98b 100644
> --- a/cpus.c
> +++ b/cpus.c
> @@ -75,7 +75,7 @@ static bool cpu_thread_is_idle(CPUState *cpu)
> if (cpu_is_stopped(cpu)) {
> return true;
> }
> - if (!cpu->halted || qemu_cpu_has_work(cpu) ||
> + if (!cpu->halted || cpu_has_work(cpu) ||
> kvm_halt_in_kernel()) {
> return false;
> }
> diff --git a/include/qom/cpu.h b/include/qom/cpu.h
> index 7739e00..4d022c3 100644
> --- a/include/qom/cpu.h
> +++ b/include/qom/cpu.h
> @@ -69,6 +69,7 @@ struct TranslationBlock;
> * instantiatable CPU type.
> * @reset: Callback to reset the #CPUState to its initial state.
> * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
> + * @has_work: Callback for checking if there is work to do.
> * @do_interrupt: Callback for interrupt handling.
> * @do_unassigned_access: Callback for unassigned access handling.
> * @memory_rw_debug: Callback for GDB memory access.
> @@ -98,6 +99,7 @@ typedef struct CPUClass {
>
> void (*reset)(CPUState *cpu);
> int reset_dump_flags;
> + bool (*has_work)(CPUState *cpu);
> void (*do_interrupt)(CPUState *cpu);
> CPUUnassignedAccess do_unassigned_access;
> int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
> @@ -344,14 +346,20 @@ void cpu_reset(CPUState *cpu);
> ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
>
> /**
> - * qemu_cpu_has_work:
> + * cpu_has_work:
> * @cpu: The vCPU to check.
> *
> * Checks whether the CPU has work to do.
> *
> * Returns: %true if the CPU has work, %false otherwise.
> */
> -bool qemu_cpu_has_work(CPUState *cpu);
> +static inline bool cpu_has_work(CPUState *cpu)
> +{
> + CPUClass *cc = CPU_GET_CLASS(cpu);
> +
> + g_assert(cc->has_work);
> + return cc->has_work(cpu);
> +}
>
> /**
> * qemu_cpu_is_self:
> diff --git a/qom/cpu.c b/qom/cpu.c
> index fa7ec6b..c71fa35 100644
> --- a/qom/cpu.c
> +++ b/qom/cpu.c
> @@ -200,6 +200,11 @@ static void cpu_common_reset(CPUState *cpu)
> cpu->halted = 0;
> }
>
> +static bool cpu_common_has_work(CPUState *cs)
> +{
> + return false;
> +}
> +
> ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model)
> {
> CPUClass *cc = CPU_CLASS(object_class_by_name(typename));
> @@ -244,6 +249,7 @@ static void cpu_class_init(ObjectClass *klass, void *data)
> k->class_by_name = cpu_common_class_by_name;
> k->reset = cpu_common_reset;
> k->get_arch_id = cpu_common_get_arch_id;
> + k->has_work = cpu_common_has_work;
> k->get_paging_enabled = cpu_common_get_paging_enabled;
> k->get_memory_mapping = cpu_common_get_memory_mapping;
> k->write_elf32_qemunote = cpu_common_write_elf32_qemunote;
> diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
> index cfad2ea..053afa2 100644
> --- a/target-alpha/cpu.c
> +++ b/target-alpha/cpu.c
> @@ -31,6 +31,21 @@ static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.pc = value;
> }
>
> +static bool alpha_cpu_has_work(CPUState *cs)
> +{
> + /* Here we are checking to see if the CPU should wake up from HALT.
> + We will have gotten into this state only for WTINT from PALmode. */
> + /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
> + asleep even if (some) interrupts have been asserted. For now,
> + assume that if a CPU really wants to stay asleep, it will mask
> + interrupts at the chipset level, which will prevent these bits
> + from being set in the first place. */
> + return cs->interrupt_request & (CPU_INTERRUPT_HARD
> + | CPU_INTERRUPT_TIMER
> + | CPU_INTERRUPT_SMP
> + | CPU_INTERRUPT_MCHK);
> +}
> +
> static void alpha_cpu_realizefn(DeviceState *dev, Error **errp)
> {
> CPUState *cs = CPU(dev);
> @@ -271,6 +286,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
> dc->realize = alpha_cpu_realizefn;
>
> cc->class_by_name = alpha_cpu_class_by_name;
> + cc->has_work = alpha_cpu_has_work;
> cc->do_interrupt = alpha_cpu_do_interrupt;
> cc->dump_state = alpha_cpu_dump_state;
> cc->set_pc = alpha_cpu_set_pc;
> diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
> index c85dc6e..a172124 100644
> --- a/target-alpha/cpu.h
> +++ b/target-alpha/cpu.h
> @@ -498,21 +498,6 @@ static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
> *pflags = flags;
> }
>
> -static inline bool cpu_has_work(CPUState *cpu)
> -{
> - /* Here we are checking to see if the CPU should wake up from HALT.
> - We will have gotten into this state only for WTINT from PALmode. */
> - /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
> - asleep even if (some) interrupts have been asserted. For now,
> - assume that if a CPU really wants to stay asleep, it will mask
> - interrupts at the chipset level, which will prevent these bits
> - from being set in the first place. */
> - return cpu->interrupt_request & (CPU_INTERRUPT_HARD
> - | CPU_INTERRUPT_TIMER
> - | CPU_INTERRUPT_SMP
> - | CPU_INTERRUPT_MCHK);
> -}
> -
> #include "exec/exec-all.h"
>
> #endif /* !defined (__CPU_ALPHA_H__) */
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index b2556c6..f38c851 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -34,6 +34,12 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.regs[15] = value;
> }
>
> +static bool arm_cpu_has_work(CPUState *cs)
> +{
> + return cs->interrupt_request &
> + (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
> +}
> +
> static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
> {
> /* Reset a single ARMCPRegInfo register */
> @@ -890,6 +896,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
> cc->reset = arm_cpu_reset;
>
> cc->class_by_name = arm_cpu_class_by_name;
> + cc->has_work = arm_cpu_has_work;
> cc->do_interrupt = arm_cpu_do_interrupt;
> cc->dump_state = arm_cpu_dump_state;
> cc->set_pc = arm_cpu_set_pc;
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index f2abdf3..a42822b 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -814,12 +814,6 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
> }
> }
>
> -static inline bool cpu_has_work(CPUState *cpu)
> -{
> - return cpu->interrupt_request &
> - (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
> -}
> -
> #include "exec/exec-all.h"
>
> /* Load an instruction and return it in the standard little-endian order */
> diff --git a/target-cris/cpu.c b/target-cris/cpu.c
> index 44301a4..998cded 100644
> --- a/target-cris/cpu.c
> +++ b/target-cris/cpu.c
> @@ -33,6 +33,11 @@ static void cris_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.pc = value;
> }
>
> +static bool cris_cpu_has_work(CPUState *cs)
> +{
> + return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
> +}
> +
> /* CPUClass::reset() */
> static void cris_cpu_reset(CPUState *s)
> {
> @@ -257,6 +262,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
> cc->reset = cris_cpu_reset;
>
> cc->class_by_name = cris_cpu_class_by_name;
> + cc->has_work = cris_cpu_has_work;
> cc->do_interrupt = cris_cpu_do_interrupt;
> cc->dump_state = cris_cpu_dump_state;
> cc->set_pc = cris_cpu_set_pc;
> diff --git a/target-cris/cpu.h b/target-cris/cpu.h
> index 4b9fc4c..15a0497 100644
> --- a/target-cris/cpu.h
> +++ b/target-cris/cpu.h
> @@ -272,11 +272,6 @@ static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
> #define cpu_list cris_cpu_list
> void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
>
> -static inline bool cpu_has_work(CPUState *cpu)
> -{
> - return cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
> -}
> -
> #include "exec/exec-all.h"
>
> #endif
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index c36345e..fa92950 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -2676,6 +2676,20 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
> cpu->env.eip = tb->pc - tb->cs_base;
> }
>
> +static bool x86_cpu_has_work(CPUState *cs)
> +{
> + X86CPU *cpu = X86_CPU(cs);
> + CPUX86State *env = &cpu->env;
> +
> + return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
> + CPU_INTERRUPT_POLL)) &&
> + (env->eflags & IF_MASK)) ||
> + (cs->interrupt_request & (CPU_INTERRUPT_NMI |
> + CPU_INTERRUPT_INIT |
> + CPU_INTERRUPT_SIPI |
> + CPU_INTERRUPT_MCE));
> +}
> +
> static Property x86_cpu_properties[] = {
> DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
> DEFINE_PROP_END_OF_LIST()
> @@ -2696,6 +2710,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
> cc->reset = x86_cpu_reset;
> cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
>
> + cc->has_work = x86_cpu_has_work;
> cc->do_interrupt = x86_cpu_do_interrupt;
> cc->dump_state = x86_cpu_dump_state;
> cc->set_pc = x86_cpu_set_pc;
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index 5723eff..6d46c75 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -1161,20 +1161,6 @@ void optimize_flags_init(void);
> #include "hw/i386/apic.h"
> #endif
>
> -static inline bool cpu_has_work(CPUState *cs)
> -{
> - X86CPU *cpu = X86_CPU(cs);
> - CPUX86State *env = &cpu->env;
> -
> - return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
> - CPU_INTERRUPT_POLL)) &&
> - (env->eflags & IF_MASK)) ||
> - (cs->interrupt_request & (CPU_INTERRUPT_NMI |
> - CPU_INTERRUPT_INIT |
> - CPU_INTERRUPT_SIPI |
> - CPU_INTERRUPT_MCE));
> -}
> -
> #include "exec/exec-all.h"
>
> static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
> diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
> index 869878c..4fa8605 100644
> --- a/target-lm32/cpu.c
> +++ b/target-lm32/cpu.c
> @@ -29,6 +29,11 @@ static void lm32_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.pc = value;
> }
>
> +static bool lm32_cpu_has_work(CPUState *cs)
> +{
> + return cs->interrupt_request & CPU_INTERRUPT_HARD;
> +}
> +
> /* CPUClass::reset() */
> static void lm32_cpu_reset(CPUState *s)
> {
> @@ -86,6 +91,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
> lcc->parent_reset = cc->reset;
> cc->reset = lm32_cpu_reset;
>
> + cc->has_work = lm32_cpu_has_work;
> cc->do_interrupt = lm32_cpu_do_interrupt;
> cc->dump_state = lm32_cpu_dump_state;
> cc->set_pc = lm32_cpu_set_pc;
> diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
> index dbfe043..a251a02 100644
> --- a/target-lm32/cpu.h
> +++ b/target-lm32/cpu.h
> @@ -225,11 +225,6 @@ static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *pc,
> *flags = 0;
> }
>
> -static inline bool cpu_has_work(CPUState *cpu)
> -{
> - return cpu->interrupt_request & CPU_INTERRUPT_HARD;
> -}
> -
> #include "exec/exec-all.h"
>
> #endif
> diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
> index 008d8db..7d66ed0 100644
> --- a/target-m68k/cpu.c
> +++ b/target-m68k/cpu.c
> @@ -30,6 +30,11 @@ static void m68k_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.pc = value;
> }
>
> +static bool m68k_cpu_has_work(CPUState *cs)
> +{
> + return cs->interrupt_request & CPU_INTERRUPT_HARD;
> +}
> +
> static void m68k_set_feature(CPUM68KState *env, int feature)
> {
> env->features |= (1u << feature);
> @@ -189,6 +194,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
> cc->reset = m68k_cpu_reset;
>
> cc->class_by_name = m68k_cpu_class_by_name;
> + cc->has_work = m68k_cpu_has_work;
> cc->do_interrupt = m68k_cpu_do_interrupt;
> cc->dump_state = m68k_cpu_dump_state;
> cc->set_pc = m68k_cpu_set_pc;
> diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
> index cfd6846..5f79d2a 100644
> --- a/target-m68k/cpu.h
> +++ b/target-m68k/cpu.h
> @@ -253,11 +253,6 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
> | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
> }
>
> -static inline bool cpu_has_work(CPUState *cpu)
> -{
> - return cpu->interrupt_request & CPU_INTERRUPT_HARD;
> -}
> -
> #include "exec/exec-all.h"
>
> #endif
> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
> index 0ef9aa4..6104939 100644
> --- a/target-microblaze/cpu.c
> +++ b/target-microblaze/cpu.c
> @@ -33,6 +33,11 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.sregs[SR_PC] = value;
> }
>
> +static bool mb_cpu_has_work(CPUState *cs)
> +{
> + return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
> +}
> +
> /* CPUClass::reset() */
> static void mb_cpu_reset(CPUState *s)
> {
> @@ -139,6 +144,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
> mcc->parent_reset = cc->reset;
> cc->reset = mb_cpu_reset;
>
> + cc->has_work = mb_cpu_has_work;
> cc->do_interrupt = mb_cpu_do_interrupt;
> cc->dump_state = mb_cpu_dump_state;
> cc->set_pc = mb_cpu_set_pc;
> diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
> index 7508cf5..23f96f8 100644
> --- a/target-microblaze/cpu.h
> +++ b/target-microblaze/cpu.h
> @@ -358,11 +358,6 @@ void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
> unsigned size);
> #endif
>
> -static inline bool cpu_has_work(CPUState *cpu)
> -{
> - return cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
> -}
> -
> #include "exec/exec-all.h"
>
> #endif
> diff --git a/target-mips/cpu.c b/target-mips/cpu.c
> index 9dd47e8..0a2dc46 100644
> --- a/target-mips/cpu.c
> +++ b/target-mips/cpu.c
> @@ -45,6 +45,35 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
> env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
> }
>
> +static bool mips_cpu_has_work(CPUState *cs)
> +{
> + MIPSCPU *cpu = MIPS_CPU(cs);
> + CPUMIPSState *env = &cpu->env;
> + bool has_work = false;
> +
> + /* It is implementation dependent if non-enabled interrupts
> + wake-up the CPU, however most of the implementations only
> + check for interrupts that can be taken. */
> + if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
> + cpu_mips_hw_interrupts_pending(env)) {
> + has_work = true;
> + }
> +
> + /* MIPS-MT has the ability to halt the CPU. */
> + if (env->CP0_Config3 & (1 << CP0C3_MT)) {
> + /* The QEMU model will issue an _WAKE request whenever the CPUs
> + should be woken up. */
> + if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
> + has_work = true;
> + }
> +
> + if (!mips_vpe_active(env)) {
> + has_work = false;
> + }
> + }
> + return has_work;
> +}
> +
> /* CPUClass::reset() */
> static void mips_cpu_reset(CPUState *s)
> {
> @@ -97,6 +126,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
> mcc->parent_reset = cc->reset;
> cc->reset = mips_cpu_reset;
>
> + cc->has_work = mips_cpu_has_work;
> cc->do_interrupt = mips_cpu_do_interrupt;
> cc->dump_state = mips_cpu_dump_state;
> cc->set_pc = mips_cpu_set_pc;
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index a29c82f..dff2836 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -702,34 +702,6 @@ static inline int mips_vpe_active(CPUMIPSState *env)
> return active;
> }
>
> -static inline bool cpu_has_work(CPUState *cpu)
> -{
> - CPUMIPSState *env = &MIPS_CPU(cpu)->env;
> - bool has_work = false;
> -
> - /* It is implementation dependent if non-enabled interrupts
> - wake-up the CPU, however most of the implementations only
> - check for interrupts that can be taken. */
> - if ((cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
> - cpu_mips_hw_interrupts_pending(env)) {
> - has_work = true;
> - }
> -
> - /* MIPS-MT has the ability to halt the CPU. */
> - if (env->CP0_Config3 & (1 << CP0C3_MT)) {
> - /* The QEMU model will issue an _WAKE request whenever the CPUs
> - should be woken up. */
> - if (cpu->interrupt_request & CPU_INTERRUPT_WAKE) {
> - has_work = true;
> - }
> -
> - if (!mips_vpe_active(env)) {
> - has_work = false;
> - }
> - }
> - return has_work;
> -}
> -
> #include "exec/exec-all.h"
>
> static inline void compute_hflags(CPUMIPSState *env)
> diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
> index d97a091..66f337e 100644
> --- a/target-moxie/cpu.c
> +++ b/target-moxie/cpu.c
> @@ -29,6 +29,11 @@ static void moxie_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.pc = value;
> }
>
> +static bool moxie_cpu_has_work(CPUState *cs)
> +{
> + return cs->interrupt_request & CPU_INTERRUPT_HARD;
> +}
> +
> static void moxie_cpu_reset(CPUState *s)
> {
> MoxieCPU *cpu = MOXIE_CPU(s);
> @@ -99,6 +104,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
>
> cc->class_by_name = moxie_cpu_class_by_name;
>
> + cc->has_work = moxie_cpu_has_work;
> cc->do_interrupt = moxie_cpu_do_interrupt;
> cc->dump_state = moxie_cpu_dump_state;
> cc->set_pc = moxie_cpu_set_pc;
> diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h
> index 5ce14b5..778cfc0 100644
> --- a/target-moxie/cpu.h
> +++ b/target-moxie/cpu.h
> @@ -152,11 +152,6 @@ static inline void cpu_get_tb_cpu_state(CPUMoxieState *env, target_ulong *pc,
> *flags = 0;
> }
>
> -static inline int cpu_has_work(CPUState *cpu)
> -{
> - return cpu->interrupt_request & CPU_INTERRUPT_HARD;
> -}
> -
> int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address,
> int rw, int mmu_idx);
>
> diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
> index 075f00a..ca8495f 100644
> --- a/target-openrisc/cpu.c
> +++ b/target-openrisc/cpu.c
> @@ -27,6 +27,12 @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.pc = value;
> }
>
> +static bool openrisc_cpu_has_work(CPUState *cs)
> +{
> + return cs->interrupt_request & (CPU_INTERRUPT_HARD |
> + CPU_INTERRUPT_TIMER);
> +}
> +
> /* CPUClass::reset() */
> static void openrisc_cpu_reset(CPUState *s)
> {
> @@ -153,6 +159,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
> cc->reset = openrisc_cpu_reset;
>
> cc->class_by_name = openrisc_cpu_class_by_name;
> + cc->has_work = openrisc_cpu_has_work;
> cc->do_interrupt = openrisc_cpu_do_interrupt;
> cc->dump_state = openrisc_cpu_dump_state;
> cc->set_pc = openrisc_cpu_set_pc;
> diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
> index 8fd0bc0..4a27f22 100644
> --- a/target-openrisc/cpu.h
> +++ b/target-openrisc/cpu.h
> @@ -418,11 +418,6 @@ static inline int cpu_mmu_index(CPUOpenRISCState *env)
> }
>
> #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
> -static inline bool cpu_has_work(CPUState *cpu)
> -{
> - return cpu->interrupt_request & (CPU_INTERRUPT_HARD |
> - CPU_INTERRUPT_TIMER);
> -}
>
> #include "exec/exec-all.h"
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 422a6bb..70c1ef5 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -2134,14 +2134,6 @@ static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
>
> extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
>
> -static inline bool cpu_has_work(CPUState *cpu)
> -{
> - PowerPCCPU *ppc_cpu = POWERPC_CPU(cpu);
> - CPUPPCState *env = &ppc_cpu->env;
> -
> - return msr_ee && (cpu->interrupt_request & CPU_INTERRUPT_HARD);
> -}
> -
> #include "exec/exec-all.h"
>
> void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index d2645ba..b552451 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8437,6 +8437,14 @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.nip = value;
> }
>
> +static bool ppc_cpu_has_work(CPUState *cs)
> +{
> + PowerPCCPU *cpu = POWERPC_CPU(cs);
> + CPUPPCState *env = &cpu->env;
> +
> + return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
> +}
> +
> /* CPUClass::reset() */
> static void ppc_cpu_reset(CPUState *s)
> {
> @@ -8561,6 +8569,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
> cc->reset = ppc_cpu_reset;
>
> cc->class_by_name = ppc_cpu_class_by_name;
> + cc->has_work = ppc_cpu_has_work;
> cc->do_interrupt = ppc_cpu_do_interrupt;
> cc->dump_state = ppc_cpu_dump_state;
> cc->dump_statistics = ppc_cpu_dump_statistics;
> diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
> index 3c89f8a..a4c7a33 100644
> --- a/target-s390x/cpu.c
> +++ b/target-s390x/cpu.c
> @@ -65,6 +65,15 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.psw.addr = value;
> }
>
> +static bool s390_cpu_has_work(CPUState *cs)
> +{
> + S390CPU *cpu = S390_CPU(cs);
> + CPUS390XState *env = &cpu->env;
> +
> + return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
> + (env->psw.mask & PSW_MASK_EXT);
> +}
> +
> #if !defined(CONFIG_USER_ONLY)
> /* S390CPUClass::load_normal() */
> static void s390_cpu_load_normal(CPUState *s)
> @@ -217,6 +226,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
> scc->cpu_reset = s390_cpu_reset;
> scc->initial_cpu_reset = s390_cpu_initial_reset;
> cc->reset = s390_cpu_full_reset;
> + cc->has_work = s390_cpu_has_work;
> cc->do_interrupt = s390_cpu_do_interrupt;
> cc->dump_state = s390_cpu_dump_state;
> cc->set_pc = s390_cpu_set_pc;
> diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
> index 8be5648..3b588af 100644
> --- a/target-s390x/cpu.h
> +++ b/target-s390x/cpu.h
> @@ -1036,15 +1036,6 @@ static inline void cpu_inject_crw_mchk(S390CPU *cpu)
> cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> }
>
> -static inline bool cpu_has_work(CPUState *cpu)
> -{
> - S390CPU *s390_cpu = S390_CPU(cpu);
> - CPUS390XState *env = &s390_cpu->env;
> -
> - return (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
> - (env->psw.mask & PSW_MASK_EXT);
> -}
> -
> /* fpu_helper.c */
> uint32_t set_cc_nz_f32(float32 v);
> uint32_t set_cc_nz_f64(float64 v);
> diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
> index 34b2b57..5bf6d9f 100644
> --- a/target-sh4/cpu.c
> +++ b/target-sh4/cpu.c
> @@ -39,6 +39,11 @@ static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
> cpu->env.flags = tb->flags;
> }
>
> +static bool superh_cpu_has_work(CPUState *cs)
> +{
> + return cs->interrupt_request & CPU_INTERRUPT_HARD;
> +}
> +
> /* CPUClass::reset() */
> static void superh_cpu_reset(CPUState *s)
> {
> @@ -283,6 +288,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
> cc->reset = superh_cpu_reset;
>
> cc->class_by_name = superh_cpu_class_by_name;
> + cc->has_work = superh_cpu_has_work;
> cc->do_interrupt = superh_cpu_do_interrupt;
> cc->dump_state = superh_cpu_dump_state;
> cc->set_pc = superh_cpu_set_pc;
> diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
> index 276d295..2eafc2d 100644
> --- a/target-sh4/cpu.h
> +++ b/target-sh4/cpu.h
> @@ -352,11 +352,6 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
> | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
> }
>
> -static inline bool cpu_has_work(CPUState *cpu)
> -{
> - return cpu->interrupt_request & CPU_INTERRUPT_HARD;
> -}
> -
> #include "exec/exec-all.h"
>
> #endif /* _CPU_SH4_H */
> diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
> index 47ce60d..ede2c80 100644
> --- a/target-sparc/cpu.c
> +++ b/target-sparc/cpu.c
> @@ -739,6 +739,15 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
> cpu->env.npc = tb->cs_base;
> }
>
> +static bool sparc_cpu_has_work(CPUState *cs)
> +{
> + SPARCCPU *cpu = SPARC_CPU(cs);
> + CPUSPARCState *env = &cpu->env;
> +
> + return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
> + cpu_interrupts_enabled(env);
> +}
> +
> static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
> {
> SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
> @@ -782,6 +791,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
> scc->parent_reset = cc->reset;
> cc->reset = sparc_cpu_reset;
>
> + cc->has_work = sparc_cpu_has_work;
> cc->do_interrupt = sparc_cpu_do_interrupt;
> cc->dump_state = sparc_cpu_dump_state;
> #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
> index 41194ec..adf6557 100644
> --- a/target-sparc/cpu.h
> +++ b/target-sparc/cpu.h
> @@ -747,15 +747,6 @@ static inline bool tb_am_enabled(int tb_flags)
> #endif
> }
>
> -static inline bool cpu_has_work(CPUState *cpu)
> -{
> - SPARCCPU *sparc_cpu = SPARC_CPU(cpu);
> - CPUSPARCState *env1 = &sparc_cpu->env;
> -
> - return (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
> - cpu_interrupts_enabled(env1);
> -}
> -
> #include "exec/exec-all.h"
>
> #endif
> diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
> index 3f78208..1cfe50a 100644
> --- a/target-unicore32/cpu.c
> +++ b/target-unicore32/cpu.c
> @@ -23,6 +23,12 @@ static void uc32_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.regs[31] = value;
> }
>
> +static bool uc32_cpu_has_work(CPUState *cs)
> +{
> + return cs->interrupt_request &
> + (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
> +}
> +
> static inline void set_feature(CPUUniCore32State *env, int feature)
> {
> env->features |= feature;
> @@ -138,6 +144,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
> dc->realize = uc32_cpu_realizefn;
>
> cc->class_by_name = uc32_cpu_class_by_name;
> + cc->has_work = uc32_cpu_has_work;
> cc->do_interrupt = uc32_cpu_do_interrupt;
> cc->dump_state = uc32_cpu_dump_state;
> cc->set_pc = uc32_cpu_set_pc;
> diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
> index 967511e..1db7419 100644
> --- a/target-unicore32/cpu.h
> +++ b/target-unicore32/cpu.h
> @@ -160,10 +160,4 @@ static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc
> void uc32_translate_init(void);
> void switch_mode(CPUUniCore32State *, int);
>
> -static inline bool cpu_has_work(CPUState *cpu)
> -{
> - return cpu->interrupt_request &
> - (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
> -}
> -
> #endif /* QEMU_UNICORE32_CPU_H */
> diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
> index c19d17a..46573c6 100644
> --- a/target-xtensa/cpu.c
> +++ b/target-xtensa/cpu.c
> @@ -40,6 +40,13 @@ static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.pc = value;
> }
>
> +static bool xtensa_cpu_has_work(CPUState *cs)
> +{
> + XtensaCPU *cpu = XTENSA_CPU(cs);
> +
> + return cpu->env.pending_irq_level;
> +}
> +
> /* CPUClass::reset() */
> static void xtensa_cpu_reset(CPUState *s)
> {
> @@ -132,6 +139,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
> cc->reset = xtensa_cpu_reset;
>
> cc->class_by_name = xtensa_cpu_class_by_name;
> + cc->has_work = xtensa_cpu_has_work;
> cc->do_interrupt = xtensa_cpu_do_interrupt;
> cc->dump_state = xtensa_cpu_dump_state;
> cc->set_pc = xtensa_cpu_set_pc;
> diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
> index 95103e9..de27c8c 100644
> --- a/target-xtensa/cpu.h
> +++ b/target-xtensa/cpu.h
> @@ -519,11 +519,4 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
> #include "exec/cpu-all.h"
> #include "exec/exec-all.h"
>
> -static inline int cpu_has_work(CPUState *cpu)
> -{
> - CPUXtensaState *env = &XTENSA_CPU(cpu)->env;
> -
> - return env->pending_irq_level;
> -}
> -
> #endif
target-openrisc: Tested-by: Jia Liu <proljc@gmail.com>
> --
> 1.8.1.4
>
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 01/41] cpu: Turn cpu_has_work() into a CPUClass hook
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 01/41] cpu: Turn cpu_has_work() into a CPUClass hook Andreas Färber
2013-09-04 12:41 ` Jia Liu
@ 2014-02-05 18:51 ` Andreas Färber
1 sibling, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2014-02-05 18:51 UTC (permalink / raw)
To: qemu-devel, Paolo Bonzini
Cc: Peter Maydell, Jia Liu, Anthony Green, Alexander Graf, Blue Swirl,
Max Filippov, Michael Walle, qemu-ppc, Edgar E. Iglesias,
Guan Xuetao, Aurelien Jarno, Richard Henderson
Am 04.09.2013 11:04, schrieb Andreas Färber:
> Default to false.
>
> Tidy variable naming and inline cast uses while at it.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
If I've re-read the IRC transcript correctly, Paolo objected to patch
03/41 and had doubts about 02/41. I have therefore applied this 01/41 to
qom-cpu to crack down on functions new targets need to implement in cpu.h:
https://github.com/afaerber/qemu-cpu/commits/qom-cpu
Regards,
Andreas
> ---
> cpu-exec.c | 5 -----
> cpus.c | 2 +-
> include/qom/cpu.h | 12 ++++++++++--
> qom/cpu.c | 6 ++++++
> target-alpha/cpu.c | 16 ++++++++++++++++
> target-alpha/cpu.h | 15 ---------------
> target-arm/cpu.c | 7 +++++++
> target-arm/cpu.h | 6 ------
> target-cris/cpu.c | 6 ++++++
> target-cris/cpu.h | 5 -----
> target-i386/cpu.c | 15 +++++++++++++++
> target-i386/cpu.h | 14 --------------
> target-lm32/cpu.c | 6 ++++++
> target-lm32/cpu.h | 5 -----
> target-m68k/cpu.c | 6 ++++++
> target-m68k/cpu.h | 5 -----
> target-microblaze/cpu.c | 6 ++++++
> target-microblaze/cpu.h | 5 -----
> target-mips/cpu.c | 30 ++++++++++++++++++++++++++++++
> target-mips/cpu.h | 28 ----------------------------
> target-moxie/cpu.c | 6 ++++++
> target-moxie/cpu.h | 5 -----
> target-openrisc/cpu.c | 7 +++++++
> target-openrisc/cpu.h | 5 -----
> target-ppc/cpu.h | 8 --------
> target-ppc/translate_init.c | 9 +++++++++
> target-s390x/cpu.c | 10 ++++++++++
> target-s390x/cpu.h | 9 ---------
> target-sh4/cpu.c | 6 ++++++
> target-sh4/cpu.h | 5 -----
> target-sparc/cpu.c | 10 ++++++++++
> target-sparc/cpu.h | 9 ---------
> target-unicore32/cpu.c | 7 +++++++
> target-unicore32/cpu.h | 6 ------
> target-xtensa/cpu.c | 8 ++++++++
> target-xtensa/cpu.h | 7 -------
> 36 files changed, 172 insertions(+), 145 deletions(-)
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [RFC qom-cpu 02/41] cpu: Turn cpu_mmu_index() into a CPUClass hook
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 01/41] cpu: Turn cpu_has_work() into a CPUClass hook Andreas Färber
@ 2013-09-04 9:04 ` Andreas Färber
2013-09-04 12:42 ` Jia Liu
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 03/41] cpu: Turn cpu_get_tb_cpu_state() " Andreas Färber
` (41 subsequent siblings)
43 siblings, 1 reply; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:04 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Anthony Green, Alexander Graf, Blue Swirl,
Max Filippov, Michael Walle, open list:PowerPC, Paul Brook,
Edgar E. Iglesias, Guan Xuetao, Andreas Färber,
Aurelien Jarno, Richard Henderson
Default to 0.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cputlb.c | 7 +++----
| 4 ++--
include/qom/cpu.h | 15 +++++++++++++++
qom/cpu.c | 6 ++++++
target-alpha/cpu.c | 14 ++++++++++++++
target-alpha/cpu.h | 11 -----------
target-alpha/translate.c | 2 +-
target-arm/cpu.c | 8 ++++++++
target-arm/cpu.h | 4 ----
target-cris/cpu.c | 8 ++++++++
target-cris/cpu.h | 4 ----
target-cris/translate.c | 6 +++---
target-cris/translate_v10.c | 2 +-
target-i386/cpu.c | 11 +++++++++++
target-i386/cpu.h | 6 ------
target-i386/translate.c | 2 +-
target-lm32/cpu.h | 4 ----
target-m68k/cpu.c | 8 ++++++++
target-m68k/cpu.h | 4 ----
target-microblaze/cpu.c | 15 +++++++++++++++
target-microblaze/cpu.h | 11 -----------
target-microblaze/mmu.c | 3 ++-
target-microblaze/translate.c | 14 +++++++-------
target-mips/cpu.c | 8 ++++++++
target-mips/cpu.h | 4 ----
target-moxie/cpu.h | 5 -----
target-openrisc/cpu.c | 11 +++++++++++
target-openrisc/cpu.h | 8 --------
target-openrisc/translate.c | 2 +-
target-ppc/cpu.h | 4 ----
target-ppc/translate_init.c | 8 ++++++++
target-s390x/cpu.c | 12 ++++++++++++
target-s390x/cpu.h | 9 ---------
target-sh4/cpu.c | 8 ++++++++
target-sh4/cpu.h | 4 ----
target-sparc/cpu.c | 25 +++++++++++++++++++++++++
target-sparc/cpu.h | 19 -------------------
target-sparc/mmu_helper.c | 2 +-
target-sparc/translate.c | 2 +-
target-unicore32/cpu.c | 8 ++++++++
target-unicore32/cpu.h | 4 ----
target-xtensa/cpu.c | 8 ++++++++
target-xtensa/cpu.h | 5 -----
43 files changed, 196 insertions(+), 129 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index fff0afb..85a028f 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -316,12 +316,14 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
*/
tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
{
+ CPUState *cpu = ENV_GET_CPU(env1);
+ CPUClass *cc = CPU_GET_CLASS(cpu);
int mmu_idx, page_index, pd;
void *p;
MemoryRegion *mr;
page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
- mmu_idx = cpu_mmu_index(env1);
+ mmu_idx = cc->mmu_index(cpu);
if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
(addr & TARGET_PAGE_MASK))) {
cpu_ldub_code(env1, addr);
@@ -329,9 +331,6 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
mr = iotlb_to_region(pd);
if (memory_region_is_unassigned(mr)) {
- CPUState *cpu = ENV_GET_CPU(env1);
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
if (cc->do_unassigned_access) {
cc->do_unassigned_access(cpu, addr, false, true, 0, 4);
} else {
--git a/include/exec/softmmu_header.h b/include/exec/softmmu_header.h
index d8d9c81..e138b87 100644
--- a/include/exec/softmmu_header.h
+++ b/include/exec/softmmu_header.h
@@ -54,12 +54,12 @@
#elif ACCESS_TYPE == (NB_MMU_MODES)
-#define CPU_MMU_INDEX (cpu_mmu_index(env))
+#define CPU_MMU_INDEX (cpu_mmu_index(ENV_GET_CPU(env)))
#define MMUSUFFIX _mmu
#elif ACCESS_TYPE == (NB_MMU_MODES + 1)
-#define CPU_MMU_INDEX (cpu_mmu_index(env))
+#define CPU_MMU_INDEX (cpu_mmu_index(ENV_GET_CPU(env)))
#define MMUSUFFIX _cmmu
#else
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 4d022c3..c78d572 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -76,6 +76,7 @@ struct TranslationBlock;
* @dump_state: Callback for dumping state.
* @dump_statistics: Callback for dumping statistics.
* @get_arch_id: Callback for getting architecture-dependent CPU ID.
+ * @mmu_index: Callback for obtaining MMU index.
* @get_paging_enabled: Callback for inquiring whether paging is enabled.
* @get_memory_mapping: Callback for obtaining the memory mappings.
* @set_pc: Callback for setting the Program Counter register.
@@ -109,6 +110,7 @@ typedef struct CPUClass {
void (*dump_statistics)(CPUState *cpu, FILE *f,
fprintf_function cpu_fprintf, int flags);
int64_t (*get_arch_id)(CPUState *cpu);
+ int (*mmu_index)(const CPUState *cpu);
bool (*get_paging_enabled)(const CPUState *cpu);
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
@@ -217,6 +219,19 @@ DECLARE_TLS(CPUState *, current_cpu);
#define current_cpu tls_var(current_cpu)
/**
+ * cpu_mmu_index:
+ * @cpu: The CPU whose MMU index is to be obtained.
+ *
+ * Returns: MMU index for @cpu.
+ */
+static inline int cpu_mmu_index(CPUState *cpu)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ return cc->mmu_index(cpu);
+}
+
+/**
* cpu_paging_enabled:
* @cpu: The CPU whose state is to be inspected.
*
diff --git a/qom/cpu.c b/qom/cpu.c
index c71fa35..9b9c2c6 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -200,6 +200,11 @@ static void cpu_common_reset(CPUState *cpu)
cpu->halted = 0;
}
+static int cpu_common_mmu_index(const CPUState *cs)
+{
+ return 0;
+}
+
static bool cpu_common_has_work(CPUState *cs)
{
return false;
@@ -249,6 +254,7 @@ static void cpu_class_init(ObjectClass *klass, void *data)
k->class_by_name = cpu_common_class_by_name;
k->reset = cpu_common_reset;
k->get_arch_id = cpu_common_get_arch_id;
+ k->mmu_index = cpu_common_mmu_index;
k->has_work = cpu_common_has_work;
k->get_paging_enabled = cpu_common_get_paging_enabled;
k->get_memory_mapping = cpu_common_get_memory_mapping;
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index 053afa2..15d6f1f 100644
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -31,6 +31,19 @@ static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static int alpha_cpu_mmu_index(const CPUState *cs)
+{
+ AlphaCPU *cpu = ALPHA_CPU(cs);
+
+ if (cpu->env.pal_mode) {
+ return MMU_KERNEL_IDX;
+ } else if (cpu->env.ps & PS_USER_MODE) {
+ return MMU_USER_IDX;
+ } else {
+ return MMU_KERNEL_IDX;
+ }
+}
+
static bool alpha_cpu_has_work(CPUState *cs)
{
/* Here we are checking to see if the CPU should wake up from HALT.
@@ -289,6 +302,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = alpha_cpu_has_work;
cc->do_interrupt = alpha_cpu_do_interrupt;
cc->dump_state = alpha_cpu_dump_state;
+ cc->mmu_index = alpha_cpu_mmu_index;
cc->set_pc = alpha_cpu_set_pc;
cc->gdb_read_register = alpha_cpu_gdb_read_register;
cc->gdb_write_register = alpha_cpu_gdb_write_register;
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index a172124..808fe53 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -378,17 +378,6 @@ enum {
PS_USER_MODE = 8
};
-static inline int cpu_mmu_index(CPUAlphaState *env)
-{
- if (env->pal_mode) {
- return MMU_KERNEL_IDX;
- } else if (env->ps & PS_USER_MODE) {
- return MMU_USER_IDX;
- } else {
- return MMU_KERNEL_IDX;
- }
-}
-
enum {
IR_V0 = 0,
IR_T0 = 1,
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 28ce436..50b4339 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -3458,7 +3458,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
ctx.tb = tb;
ctx.pc = pc_start;
- ctx.mem_idx = cpu_mmu_index(env);
+ ctx.mem_idx = cpu_mmu_index(cs);
ctx.implver = env->implver;
ctx.singlestep_enabled = cs->singlestep_enabled;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index f38c851..6032a2c 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -34,6 +34,13 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.regs[15] = value;
}
+static int arm_cpu_mmu_index(const CPUState *cs)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+
+ return (cpu->env.uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
+}
+
static bool arm_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request &
@@ -899,6 +906,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = arm_cpu_has_work;
cc->do_interrupt = arm_cpu_do_interrupt;
cc->dump_state = arm_cpu_dump_state;
+ cc->mmu_index = arm_cpu_mmu_index;
cc->set_pc = arm_cpu_set_pc;
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index a42822b..19fa4ee 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -750,10 +750,6 @@ static inline CPUARMState *cpu_init(const char *cpu_model)
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUARMState *env)
-{
- return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
-}
#include "exec/cpu-all.h"
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index 998cded..1e5b425 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -33,6 +33,13 @@ static void cris_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static int cris_cpu_mmu_index(const CPUState *cs)
+{
+ CRISCPU *cpu = CRIS_CPU(cs);
+
+ return (cpu->env.pregs[PR_CCS] & U_FLAG) ? 1 : 0;
+}
+
static bool cris_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
@@ -265,6 +272,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = cris_cpu_has_work;
cc->do_interrupt = cris_cpu_do_interrupt;
cc->dump_state = cris_cpu_dump_state;
+ cc->mmu_index = cris_cpu_mmu_index;
cc->set_pc = cris_cpu_set_pc;
cc->gdb_read_register = cris_cpu_gdb_read_register;
cc->gdb_write_register = cris_cpu_gdb_write_register;
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 15a0497..0914103 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -238,10 +238,6 @@ static inline CPUCRISState *cpu_init(const char *cpu_model)
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUCRISState *env)
-{
- return !!(env->pregs[PR_CCS] & U_FLAG);
-}
int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
int mmu_idx);
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 617e1b4..29e9f63 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -1125,7 +1125,7 @@ static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
{
- int mem_index = cpu_mmu_index(dc->env);
+ int mem_index = cpu_mmu_index(CPU(cris_env_get_cpu(dc->env)));
/* If we get a fault on a delayslot we must keep the jmp state in
the cpu-state to be able to re-execute the jmp. */
@@ -1139,7 +1139,7 @@ static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
unsigned int size, int sign)
{
- int mem_index = cpu_mmu_index(dc->env);
+ int mem_index = cpu_mmu_index(CPU(cris_env_get_cpu(dc->env)));
/* If we get a fault on a delayslot we must keep the jmp state in
the cpu-state to be able to re-execute the jmp. */
@@ -1169,7 +1169,7 @@ static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
unsigned int size)
{
- int mem_index = cpu_mmu_index(dc->env);
+ int mem_index = cpu_mmu_index(CPU(cris_env_get_cpu(dc->env)));
/* If we get a fault on a delayslot we must keep the jmp state in
the cpu-state to be able to re-execute the jmp. */
diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
index d6ef084..0ade05b 100644
--- a/target-cris/translate_v10.c
+++ b/target-cris/translate_v10.c
@@ -96,7 +96,7 @@ static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val,
static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val,
unsigned int size)
{
- int mem_index = cpu_mmu_index(dc->env);
+ int mem_index = cpu_mmu_index(CPU(cris_env_get_cpu(dc->env)));
/* If we get a fault on a delayslot we must keep the jmp state in
the cpu-state to be able to re-execute the jmp. */
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index fa92950..a623383 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2676,6 +2676,16 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
cpu->env.eip = tb->pc - tb->cs_base;
}
+static int x86_cpu_mmu_index(const CPUState *cs)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
+ return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
+ ((env->hflags & HF_SMAP_MASK) && (env->eflags & AC_MASK))
+ ? MMU_KSMAP_IDX : MMU_KERNEL_IDX;
+}
+
static bool x86_cpu_has_work(CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs);
@@ -2713,6 +2723,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->has_work = x86_cpu_has_work;
cc->do_interrupt = x86_cpu_do_interrupt;
cc->dump_state = x86_cpu_dump_state;
+ cc->mmu_index = x86_cpu_mmu_index;
cc->set_pc = x86_cpu_set_pc;
cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
cc->gdb_read_register = x86_cpu_gdb_read_register;
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 6d46c75..fd16f20 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1123,12 +1123,6 @@ static inline CPUX86State *cpu_init(const char *cpu_model)
#define MMU_KERNEL_IDX 0
#define MMU_USER_IDX 1
#define MMU_KSMAP_IDX 2
-static inline int cpu_mmu_index (CPUX86State *env)
-{
- return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
- ((env->hflags & HF_SMAP_MASK) && (env->eflags & AC_MASK))
- ? MMU_KSMAP_IDX : MMU_KERNEL_IDX;
-}
#define CC_DST (env->cc_dst)
#define CC_SRC (env->cc_src)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 6d87900..2e8e8d5 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -8291,7 +8291,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
/* select memory access functions */
dc->mem_index = 0;
if (flags & HF_SOFTMMU_MASK) {
- dc->mem_index = (cpu_mmu_index(env) + 1) << 2;
+ dc->mem_index = (cpu_mmu_index(cs) + 1) << 2;
}
dc->cpuid_features = env->features[FEAT_1_EDX];
dc->cpuid_ext_features = env->features[FEAT_1_ECX];
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index a251a02..11f54e7 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -36,10 +36,6 @@ typedef struct CPULM32State CPULM32State;
#define NB_MMU_MODES 1
#define TARGET_PAGE_BITS 12
-static inline int cpu_mmu_index(CPULM32State *env)
-{
- return 0;
-}
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index 7d66ed0..00454ab 100644
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -30,6 +30,13 @@ static void m68k_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static int m68k_cpu_mmu_index(const CPUState *cs)
+{
+ M68kCPU *cpu = M68K_CPU(cs);
+
+ return (cpu->env.sr & SR_S) == 0 ? MMU_USER_IDX : 0;
+}
+
static bool m68k_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request & CPU_INTERRUPT_HARD;
@@ -197,6 +204,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->has_work = m68k_cpu_has_work;
cc->do_interrupt = m68k_cpu_do_interrupt;
cc->dump_state = m68k_cpu_dump_state;
+ cc->mmu_index = m68k_cpu_mmu_index;
cc->set_pc = m68k_cpu_set_pc;
cc->gdb_read_register = m68k_cpu_gdb_read_register;
cc->gdb_write_register = m68k_cpu_gdb_write_register;
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 5f79d2a..d1291d8 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -232,10 +232,6 @@ static inline CPUM68KState *cpu_init(const char *cpu_model)
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUM68KState *env)
-{
- return (env->sr & SR_S) == 0 ? 1 : 0;
-}
int cpu_m68k_handle_mmu_fault(CPUM68KState *env, target_ulong address, int rw,
int mmu_idx);
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 6104939..929efd8 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -33,6 +33,20 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.sregs[SR_PC] = value;
}
+static int mb_cpu_mmu_index(const CPUState *cs)
+{
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+
+ /* Are we in nommu mode?. */
+ if (!(cpu->env.sregs[SR_MSR] & MSR_VM)) {
+ return MMU_NOMMU_IDX;
+ }
+ if (cpu->env.sregs[SR_MSR] & MSR_UM) {
+ return MMU_USER_IDX;
+ }
+ return MMU_KERNEL_IDX;
+}
+
static bool mb_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
@@ -147,6 +161,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = mb_cpu_has_work;
cc->do_interrupt = mb_cpu_do_interrupt;
cc->dump_state = mb_cpu_dump_state;
+ cc->mmu_index = mb_cpu_mmu_index;
cc->set_pc = mb_cpu_set_pc;
cc->gdb_read_register = mb_cpu_gdb_read_register;
cc->gdb_write_register = mb_cpu_gdb_write_register;
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 23f96f8..a81f899 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -316,17 +316,6 @@ static inline CPUMBState *cpu_init(const char *cpu_model)
#define MMU_USER_IDX 2
/* See NB_MMU_MODES further up the file. */
-static inline int cpu_mmu_index (CPUMBState *env)
-{
- /* Are we in nommu mode?. */
- if (!(env->sregs[SR_MSR] & MSR_VM))
- return MMU_NOMMU_IDX;
-
- if (env->sregs[SR_MSR] & MSR_UM)
- return MMU_USER_IDX;
- return MMU_KERNEL_IDX;
-}
-
int cpu_mb_handle_mmu_fault(CPUMBState *env, target_ulong address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
diff --git a/target-microblaze/mmu.c b/target-microblaze/mmu.c
index 73bf805..9182934 100644
--- a/target-microblaze/mmu.c
+++ b/target-microblaze/mmu.c
@@ -218,6 +218,7 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn)
void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
{
+ MicroBlazeCPU *cpu = mb_env_get_cpu(env);
unsigned int i;
D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]));
@@ -277,7 +278,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
}
hit = mmu_translate(&env->mmu, &lu,
- v & TLB_EPN_MASK, 0, cpu_mmu_index(env));
+ v & TLB_EPN_MASK, 0, cpu_mmu_index(CPU(cpu)));
if (hit) {
env->mmu.regs[MMU_R_TLBX] = lu.idx;
} else
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 0673176..f4dbe11 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -440,7 +440,7 @@ static void dec_msr(DisasContext *dc)
{
TCGv t0, t1;
unsigned int sr, to, rn;
- int mem_index = cpu_mmu_index(dc->env);
+ int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
sr = dc->imm & ((1 << 14) - 1);
to = dc->imm & (1 << 14);
@@ -751,7 +751,7 @@ static void dec_bit(DisasContext *dc)
{
TCGv t0, t1;
unsigned int op;
- int mem_index = cpu_mmu_index(dc->env);
+ int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
op = dc->ir & ((1 << 9) - 1);
switch (op) {
@@ -874,7 +874,7 @@ static void dec_imm(DisasContext *dc)
static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
unsigned int size)
{
- int mem_index = cpu_mmu_index(dc->env);
+ int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
if (size == 1) {
tcg_gen_qemu_ld8u(dst, addr, mem_index);
@@ -1093,7 +1093,7 @@ static void dec_load(DisasContext *dc)
static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
unsigned int size)
{
- int mem_index = cpu_mmu_index(dc->env);
+ int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
if (size == 1)
tcg_gen_qemu_st8(val, addr, mem_index);
@@ -1308,7 +1308,7 @@ static void dec_bcc(DisasContext *dc)
static void dec_br(DisasContext *dc)
{
unsigned int dslot, link, abs, mbar;
- int mem_index = cpu_mmu_index(dc->env);
+ int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
dslot = dc->ir & (1 << 20);
abs = dc->ir & (1 << 19);
@@ -1440,7 +1440,7 @@ static inline void do_rte(DisasContext *dc)
static void dec_rts(DisasContext *dc)
{
unsigned int b_bit, i_bit, e_bit;
- int mem_index = cpu_mmu_index(dc->env);
+ int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
i_bit = dc->ir & (1 << 21);
b_bit = dc->ir & (1 << 22);
@@ -1616,7 +1616,7 @@ static void dec_null(DisasContext *dc)
/* Insns connected to FSL or AXI stream attached devices. */
static void dec_stream(DisasContext *dc)
{
- int mem_index = cpu_mmu_index(dc->env);
+ int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
TCGv_i32 t_id, t_ctrl;
int ctrl;
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index 0a2dc46..cb916f3 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -45,6 +45,13 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
}
+static int mips_cpu_mmu_index(const CPUState *cs)
+{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+
+ return cpu->env.hflags & MIPS_HFLAG_KSU;
+}
+
static bool mips_cpu_has_work(CPUState *cs)
{
MIPSCPU *cpu = MIPS_CPU(cs);
@@ -129,6 +136,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->has_work = mips_cpu_has_work;
cc->do_interrupt = mips_cpu_do_interrupt;
cc->dump_state = mips_cpu_dump_state;
+ cc->mmu_index = mips_cpu_mmu_index;
cc->set_pc = mips_cpu_set_pc;
cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->gdb_read_register = mips_cpu_gdb_read_register;
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index dff2836..22643ff 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -516,10 +516,6 @@ extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
#define MMU_MODE1_SUFFIX _super
#define MMU_MODE2_SUFFIX _user
#define MMU_USER_IDX 2
-static inline int cpu_mmu_index (CPUMIPSState *env)
-{
- return env->hflags & MIPS_HFLAG_KSU;
-}
static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
{
diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h
index 778cfc0..affcfca 100644
--- a/target-moxie/cpu.h
+++ b/target-moxie/cpu.h
@@ -136,11 +136,6 @@ static inline CPUMoxieState *cpu_init(const char *cpu_model)
#define cpu_gen_code cpu_moxie_gen_code
#define cpu_signal_handler cpu_moxie_signal_handler
-static inline int cpu_mmu_index(CPUMoxieState *env)
-{
- return 0;
-}
-
#include "exec/cpu-all.h"
#include "exec/exec-all.h"
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index ca8495f..4872fcf 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -27,6 +27,16 @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static int openrisc_cpu_mmu_index(const CPUState *cs)
+{
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+
+ if (!(cpu->env.sr & SR_IME)) {
+ return MMU_NOMMU_IDX;
+ }
+ return (cpu->env.sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX;
+}
+
static bool openrisc_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request & (CPU_INTERRUPT_HARD |
@@ -162,6 +172,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = openrisc_cpu_has_work;
cc->do_interrupt = openrisc_cpu_do_interrupt;
cc->dump_state = openrisc_cpu_dump_state;
+ cc->mmu_index = openrisc_cpu_mmu_index;
cc->set_pc = openrisc_cpu_set_pc;
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 4a27f22..2a1ca92 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -409,14 +409,6 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
*flags = (env->flags & D_FLAG);
}
-static inline int cpu_mmu_index(CPUOpenRISCState *env)
-{
- if (!(env->sr & SR_IME)) {
- return MMU_NOMMU_IDX;
- }
- return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX;
-}
-
#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
#include "exec/exec-all.h"
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 723b77d..ea242da 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -1679,7 +1679,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
dc->ppc = pc_start;
dc->pc = pc_start;
dc->flags = cpu->env.cpucfgr;
- dc->mem_idx = cpu_mmu_index(&cpu->env);
+ dc->mem_idx = cpu_mmu_index(cs);
dc->synced_flags = dc->tb_flags = tb->flags;
dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
dc->singlestep_enabled = cs->singlestep_enabled;
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 70c1ef5..9c99f0d 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1183,10 +1183,6 @@ static inline CPUPPCState *cpu_init(const char *cpu_model)
#define MMU_MODE1_SUFFIX _kernel
#define MMU_MODE2_SUFFIX _hypv
#define MMU_USER_IDX 0
-static inline int cpu_mmu_index (CPUPPCState *env)
-{
- return env->mmu_idx;
-}
#include "exec/cpu-all.h"
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index b552451..e4bcf74 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8437,6 +8437,13 @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.nip = value;
}
+static int ppc_cpu_mmu_index(const CPUState *cs)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+
+ return cpu->env.mmu_idx;
+}
+
static bool ppc_cpu_has_work(CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -8573,6 +8580,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = ppc_cpu_do_interrupt;
cc->dump_state = ppc_cpu_dump_state;
cc->dump_statistics = ppc_cpu_dump_statistics;
+ cc->mmu_index = ppc_cpu_mmu_index;
cc->set_pc = ppc_cpu_set_pc;
cc->gdb_read_register = ppc_cpu_gdb_read_register;
cc->gdb_write_register = ppc_cpu_gdb_write_register;
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index a4c7a33..6b200fe 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -65,6 +65,17 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.psw.addr = value;
}
+static int s390_cpu_mmu_index(const CPUState *cs)
+{
+ S390CPU *cpu = S390_CPU(cs);
+
+ if (cpu->env.psw.mask & PSW_MASK_PSTATE) {
+ return 1;
+ }
+
+ return 0;
+}
+
static bool s390_cpu_has_work(CPUState *cs)
{
S390CPU *cpu = S390_CPU(cs);
@@ -229,6 +240,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = s390_cpu_has_work;
cc->do_interrupt = s390_cpu_do_interrupt;
cc->dump_state = s390_cpu_dump_state;
+ cc->mmu_index = s390_cpu_mmu_index;
cc->set_pc = s390_cpu_set_pc;
cc->gdb_read_register = s390_cpu_gdb_read_register;
cc->gdb_write_register = s390_cpu_gdb_write_register;
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index 3b588af..d7970e6 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -273,15 +273,6 @@ typedef struct CPUS390XState {
#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
#define FLAG_MASK_32 0x00001000
-static inline int cpu_mmu_index (CPUS390XState *env)
-{
- if (env->psw.mask & PSW_MASK_PSTATE) {
- return 1;
- }
-
- return 0;
-}
-
static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index 5bf6d9f..df1c0e8 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -39,6 +39,13 @@ static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
cpu->env.flags = tb->flags;
}
+static int superh_cpu_mmu_index(const CPUState *cs)
+{
+ SuperHCPU *cpu = SUPERH_CPU(cs);
+
+ return (cpu->env.sr & SR_MD) == 0 ? 1 : 0;
+}
+
static bool superh_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request & CPU_INTERRUPT_HARD;
@@ -291,6 +298,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = superh_cpu_has_work;
cc->do_interrupt = superh_cpu_do_interrupt;
cc->dump_state = superh_cpu_dump_state;
+ cc->mmu_index = superh_cpu_mmu_index;
cc->set_pc = superh_cpu_set_pc;
cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
cc->gdb_read_register = superh_cpu_gdb_read_register;
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 2eafc2d..6125c20 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -240,10 +240,6 @@ static inline CPUSH4State *cpu_init(const char *cpu_model)
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUSH4State *env)
-{
- return (env->sr & SR_MD) == 0 ? 1 : 0;
-}
#include "exec/cpu-all.h"
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index ede2c80..1d27f9e 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -739,6 +739,30 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
cpu->env.npc = tb->cs_base;
}
+static int sparc_cpu_mmu_index(const CPUState *cs)
+{
+#if defined(CONFIG_USER_ONLY)
+ return MMU_USER_IDX;
+#else
+ SPARCCPU *cpu = SPARC_CPU(cs);
+ CPUSPARCState *env = &cpu->env;
+
+#if !defined(TARGET_SPARC64)
+ return env->psrs;
+#else
+ if (env->tl > 0) {
+ return MMU_NUCLEUS_IDX;
+ } else if (cpu_hypervisor_mode(env)) {
+ return MMU_HYPV_IDX;
+ } else if (cpu_supervisor_mode(env)) {
+ return MMU_KERNEL_IDX;
+ } else {
+ return MMU_USER_IDX;
+ }
+#endif
+#endif
+}
+
static bool sparc_cpu_has_work(CPUState *cs)
{
SPARCCPU *cpu = SPARC_CPU(cs);
@@ -797,6 +821,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
#endif
+ cc->mmu_index = sparc_cpu_mmu_index;
cc->set_pc = sparc_cpu_set_pc;
cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb;
cc->gdb_read_register = sparc_cpu_gdb_read_register;
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index adf6557..93590b8 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -647,25 +647,6 @@ static inline int cpu_supervisor_mode(CPUSPARCState *env1)
}
#endif
-static inline int cpu_mmu_index(CPUSPARCState *env1)
-{
-#if defined(CONFIG_USER_ONLY)
- return MMU_USER_IDX;
-#elif !defined(TARGET_SPARC64)
- return env1->psrs;
-#else
- if (env1->tl > 0) {
- return MMU_NUCLEUS_IDX;
- } else if (cpu_hypervisor_mode(env1)) {
- return MMU_HYPV_IDX;
- } else if (cpu_supervisor_mode(env1)) {
- return MMU_KERNEL_IDX;
- } else {
- return MMU_USER_IDX;
- }
-#endif
-}
-
static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
{
#if !defined (TARGET_SPARC64)
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index ef12a0a..9eb096e 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -842,7 +842,7 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
SPARCCPU *cpu = SPARC_CPU(cs);
CPUSPARCState *env = &cpu->env;
hwaddr phys_addr;
- int mmu_idx = cpu_mmu_index(env);
+ int mmu_idx = cpu_mmu_index(cs);
MemoryRegionSection section;
if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 2, mmu_idx) != 0) {
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 36615f1..73f8b9c 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -5241,7 +5241,7 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
last_pc = dc->pc;
dc->npc = (target_ulong) tb->cs_base;
dc->cc_op = CC_OP_DYNAMIC;
- dc->mem_idx = cpu_mmu_index(env);
+ dc->mem_idx = cpu_mmu_index(cs);
dc->def = env->def;
dc->fpu_enabled = tb_fpu_enabled(tb->flags);
dc->address_mask_32bit = tb_am_enabled(tb->flags);
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index 1cfe50a..3ed9ea3 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -23,6 +23,13 @@ static void uc32_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.regs[31] = value;
}
+static int uc32_cpu_mmu_index(const CPUState *cs)
+{
+ UniCore32CPU *cpu = UNICORE32_CPU(cs);
+
+ return (cpu->env.uncached_asr & ASR_M) == ASR_MODE_USER ? MMU_USER_IDX : 0;
+}
+
static bool uc32_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request &
@@ -147,6 +154,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = uc32_cpu_has_work;
cc->do_interrupt = uc32_cpu_do_interrupt;
cc->dump_state = uc32_cpu_dump_state;
+ cc->mmu_index = uc32_cpu_mmu_index;
cc->set_pc = uc32_cpu_set_pc;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index 1db7419..07693d5 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -137,10 +137,6 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index(CPUUniCore32State *env)
-{
- return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0;
-}
#include "exec/cpu-all.h"
#include "cpu-qom.h"
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
index 46573c6..f99feaa 100644
--- a/target-xtensa/cpu.c
+++ b/target-xtensa/cpu.c
@@ -40,6 +40,13 @@ static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static int xtensa_cpu_mmu_index(const CPUState *cs)
+{
+ XtensaCPU *cpu = XTENSA_CPU(cs);
+
+ return xtensa_get_cring(&cpu->env);
+}
+
static bool xtensa_cpu_has_work(CPUState *cs)
{
XtensaCPU *cpu = XTENSA_CPU(cs);
@@ -142,6 +149,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->has_work = xtensa_cpu_has_work;
cc->do_interrupt = xtensa_cpu_do_interrupt;
cc->dump_state = xtensa_cpu_dump_state;
+ cc->mmu_index = xtensa_cpu_mmu_index;
cc->set_pc = xtensa_cpu_set_pc;
cc->gdb_read_register = xtensa_cpu_gdb_read_register;
cc->gdb_write_register = xtensa_cpu_gdb_write_register;
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index de27c8c..4fdaf20 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -472,11 +472,6 @@ static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
#define MMU_MODE2_SUFFIX _ring2
#define MMU_MODE3_SUFFIX _ring3
-static inline int cpu_mmu_index(CPUXtensaState *env)
-{
- return xtensa_get_cring(env);
-}
-
#define XTENSA_TBFLAG_RING_MASK 0x3
#define XTENSA_TBFLAG_EXCM 0x4
#define XTENSA_TBFLAG_LITBASE 0x8
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 02/41] cpu: Turn cpu_mmu_index() into a CPUClass hook
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 02/41] cpu: Turn cpu_mmu_index() " Andreas Färber
@ 2013-09-04 12:42 ` Jia Liu
2013-09-04 12:55 ` Andreas Färber
0 siblings, 1 reply; 68+ messages in thread
From: Jia Liu @ 2013-09-04 12:42 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Anthony Green, qemu-devel@nongnu.org,
Alexander Graf, Blue Swirl, Max Filippov, Michael Walle,
open list:PowerPC, Paul Brook, Edgar E. Iglesias, Guan Xuetao,
Aurelien Jarno, Richard Henderson
On Wed, Sep 4, 2013 at 5:04 PM, Andreas Färber <afaerber@suse.de> wrote:
> Default to 0.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
> cputlb.c | 7 +++----
> include/exec/softmmu_header.h | 4 ++--
> include/qom/cpu.h | 15 +++++++++++++++
> qom/cpu.c | 6 ++++++
> target-alpha/cpu.c | 14 ++++++++++++++
> target-alpha/cpu.h | 11 -----------
> target-alpha/translate.c | 2 +-
> target-arm/cpu.c | 8 ++++++++
> target-arm/cpu.h | 4 ----
> target-cris/cpu.c | 8 ++++++++
> target-cris/cpu.h | 4 ----
> target-cris/translate.c | 6 +++---
> target-cris/translate_v10.c | 2 +-
> target-i386/cpu.c | 11 +++++++++++
> target-i386/cpu.h | 6 ------
> target-i386/translate.c | 2 +-
> target-lm32/cpu.h | 4 ----
> target-m68k/cpu.c | 8 ++++++++
> target-m68k/cpu.h | 4 ----
> target-microblaze/cpu.c | 15 +++++++++++++++
> target-microblaze/cpu.h | 11 -----------
> target-microblaze/mmu.c | 3 ++-
> target-microblaze/translate.c | 14 +++++++-------
> target-mips/cpu.c | 8 ++++++++
> target-mips/cpu.h | 4 ----
> target-moxie/cpu.h | 5 -----
> target-openrisc/cpu.c | 11 +++++++++++
> target-openrisc/cpu.h | 8 --------
> target-openrisc/translate.c | 2 +-
> target-ppc/cpu.h | 4 ----
> target-ppc/translate_init.c | 8 ++++++++
> target-s390x/cpu.c | 12 ++++++++++++
> target-s390x/cpu.h | 9 ---------
> target-sh4/cpu.c | 8 ++++++++
> target-sh4/cpu.h | 4 ----
> target-sparc/cpu.c | 25 +++++++++++++++++++++++++
> target-sparc/cpu.h | 19 -------------------
> target-sparc/mmu_helper.c | 2 +-
> target-sparc/translate.c | 2 +-
> target-unicore32/cpu.c | 8 ++++++++
> target-unicore32/cpu.h | 4 ----
> target-xtensa/cpu.c | 8 ++++++++
> target-xtensa/cpu.h | 5 -----
> 43 files changed, 196 insertions(+), 129 deletions(-)
>
> diff --git a/cputlb.c b/cputlb.c
> index fff0afb..85a028f 100644
> --- a/cputlb.c
> +++ b/cputlb.c
> @@ -316,12 +316,14 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
> */
> tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
> {
> + CPUState *cpu = ENV_GET_CPU(env1);
> + CPUClass *cc = CPU_GET_CLASS(cpu);
> int mmu_idx, page_index, pd;
> void *p;
> MemoryRegion *mr;
>
> page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
> - mmu_idx = cpu_mmu_index(env1);
> + mmu_idx = cc->mmu_index(cpu);
> if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
> (addr & TARGET_PAGE_MASK))) {
> cpu_ldub_code(env1, addr);
> @@ -329,9 +331,6 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
> pd = env1->iotlb[mmu_idx][page_index] & ~TARGET_PAGE_MASK;
> mr = iotlb_to_region(pd);
> if (memory_region_is_unassigned(mr)) {
> - CPUState *cpu = ENV_GET_CPU(env1);
> - CPUClass *cc = CPU_GET_CLASS(cpu);
> -
> if (cc->do_unassigned_access) {
> cc->do_unassigned_access(cpu, addr, false, true, 0, 4);
> } else {
> diff --git a/include/exec/softmmu_header.h b/include/exec/softmmu_header.h
> index d8d9c81..e138b87 100644
> --- a/include/exec/softmmu_header.h
> +++ b/include/exec/softmmu_header.h
> @@ -54,12 +54,12 @@
>
> #elif ACCESS_TYPE == (NB_MMU_MODES)
>
> -#define CPU_MMU_INDEX (cpu_mmu_index(env))
> +#define CPU_MMU_INDEX (cpu_mmu_index(ENV_GET_CPU(env)))
> #define MMUSUFFIX _mmu
>
> #elif ACCESS_TYPE == (NB_MMU_MODES + 1)
>
> -#define CPU_MMU_INDEX (cpu_mmu_index(env))
> +#define CPU_MMU_INDEX (cpu_mmu_index(ENV_GET_CPU(env)))
> #define MMUSUFFIX _cmmu
>
> #else
> diff --git a/include/qom/cpu.h b/include/qom/cpu.h
> index 4d022c3..c78d572 100644
> --- a/include/qom/cpu.h
> +++ b/include/qom/cpu.h
> @@ -76,6 +76,7 @@ struct TranslationBlock;
> * @dump_state: Callback for dumping state.
> * @dump_statistics: Callback for dumping statistics.
> * @get_arch_id: Callback for getting architecture-dependent CPU ID.
> + * @mmu_index: Callback for obtaining MMU index.
> * @get_paging_enabled: Callback for inquiring whether paging is enabled.
> * @get_memory_mapping: Callback for obtaining the memory mappings.
> * @set_pc: Callback for setting the Program Counter register.
> @@ -109,6 +110,7 @@ typedef struct CPUClass {
> void (*dump_statistics)(CPUState *cpu, FILE *f,
> fprintf_function cpu_fprintf, int flags);
> int64_t (*get_arch_id)(CPUState *cpu);
> + int (*mmu_index)(const CPUState *cpu);
> bool (*get_paging_enabled)(const CPUState *cpu);
> void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
> Error **errp);
> @@ -217,6 +219,19 @@ DECLARE_TLS(CPUState *, current_cpu);
> #define current_cpu tls_var(current_cpu)
>
> /**
> + * cpu_mmu_index:
> + * @cpu: The CPU whose MMU index is to be obtained.
> + *
> + * Returns: MMU index for @cpu.
> + */
> +static inline int cpu_mmu_index(CPUState *cpu)
> +{
> + CPUClass *cc = CPU_GET_CLASS(cpu);
> +
> + return cc->mmu_index(cpu);
> +}
> +
> +/**
> * cpu_paging_enabled:
> * @cpu: The CPU whose state is to be inspected.
> *
> diff --git a/qom/cpu.c b/qom/cpu.c
> index c71fa35..9b9c2c6 100644
> --- a/qom/cpu.c
> +++ b/qom/cpu.c
> @@ -200,6 +200,11 @@ static void cpu_common_reset(CPUState *cpu)
> cpu->halted = 0;
> }
>
> +static int cpu_common_mmu_index(const CPUState *cs)
> +{
> + return 0;
> +}
> +
> static bool cpu_common_has_work(CPUState *cs)
> {
> return false;
> @@ -249,6 +254,7 @@ static void cpu_class_init(ObjectClass *klass, void *data)
> k->class_by_name = cpu_common_class_by_name;
> k->reset = cpu_common_reset;
> k->get_arch_id = cpu_common_get_arch_id;
> + k->mmu_index = cpu_common_mmu_index;
> k->has_work = cpu_common_has_work;
> k->get_paging_enabled = cpu_common_get_paging_enabled;
> k->get_memory_mapping = cpu_common_get_memory_mapping;
> diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
> index 053afa2..15d6f1f 100644
> --- a/target-alpha/cpu.c
> +++ b/target-alpha/cpu.c
> @@ -31,6 +31,19 @@ static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.pc = value;
> }
>
> +static int alpha_cpu_mmu_index(const CPUState *cs)
> +{
> + AlphaCPU *cpu = ALPHA_CPU(cs);
> +
> + if (cpu->env.pal_mode) {
> + return MMU_KERNEL_IDX;
> + } else if (cpu->env.ps & PS_USER_MODE) {
> + return MMU_USER_IDX;
> + } else {
> + return MMU_KERNEL_IDX;
> + }
> +}
> +
> static bool alpha_cpu_has_work(CPUState *cs)
> {
> /* Here we are checking to see if the CPU should wake up from HALT.
> @@ -289,6 +302,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
> cc->has_work = alpha_cpu_has_work;
> cc->do_interrupt = alpha_cpu_do_interrupt;
> cc->dump_state = alpha_cpu_dump_state;
> + cc->mmu_index = alpha_cpu_mmu_index;
> cc->set_pc = alpha_cpu_set_pc;
> cc->gdb_read_register = alpha_cpu_gdb_read_register;
> cc->gdb_write_register = alpha_cpu_gdb_write_register;
> diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
> index a172124..808fe53 100644
> --- a/target-alpha/cpu.h
> +++ b/target-alpha/cpu.h
> @@ -378,17 +378,6 @@ enum {
> PS_USER_MODE = 8
> };
>
> -static inline int cpu_mmu_index(CPUAlphaState *env)
> -{
> - if (env->pal_mode) {
> - return MMU_KERNEL_IDX;
> - } else if (env->ps & PS_USER_MODE) {
> - return MMU_USER_IDX;
> - } else {
> - return MMU_KERNEL_IDX;
> - }
> -}
> -
> enum {
> IR_V0 = 0,
> IR_T0 = 1,
> diff --git a/target-alpha/translate.c b/target-alpha/translate.c
> index 28ce436..50b4339 100644
> --- a/target-alpha/translate.c
> +++ b/target-alpha/translate.c
> @@ -3458,7 +3458,7 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
>
> ctx.tb = tb;
> ctx.pc = pc_start;
> - ctx.mem_idx = cpu_mmu_index(env);
> + ctx.mem_idx = cpu_mmu_index(cs);
> ctx.implver = env->implver;
> ctx.singlestep_enabled = cs->singlestep_enabled;
>
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index f38c851..6032a2c 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -34,6 +34,13 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.regs[15] = value;
> }
>
> +static int arm_cpu_mmu_index(const CPUState *cs)
> +{
> + ARMCPU *cpu = ARM_CPU(cs);
> +
> + return (cpu->env.uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
> +}
> +
> static bool arm_cpu_has_work(CPUState *cs)
> {
> return cs->interrupt_request &
> @@ -899,6 +906,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
> cc->has_work = arm_cpu_has_work;
> cc->do_interrupt = arm_cpu_do_interrupt;
> cc->dump_state = arm_cpu_dump_state;
> + cc->mmu_index = arm_cpu_mmu_index;
> cc->set_pc = arm_cpu_set_pc;
> cc->gdb_read_register = arm_cpu_gdb_read_register;
> cc->gdb_write_register = arm_cpu_gdb_write_register;
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index a42822b..19fa4ee 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -750,10 +750,6 @@ static inline CPUARMState *cpu_init(const char *cpu_model)
> #define MMU_MODE0_SUFFIX _kernel
> #define MMU_MODE1_SUFFIX _user
> #define MMU_USER_IDX 1
> -static inline int cpu_mmu_index (CPUARMState *env)
> -{
> - return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
> -}
>
> #include "exec/cpu-all.h"
>
> diff --git a/target-cris/cpu.c b/target-cris/cpu.c
> index 998cded..1e5b425 100644
> --- a/target-cris/cpu.c
> +++ b/target-cris/cpu.c
> @@ -33,6 +33,13 @@ static void cris_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.pc = value;
> }
>
> +static int cris_cpu_mmu_index(const CPUState *cs)
> +{
> + CRISCPU *cpu = CRIS_CPU(cs);
> +
> + return (cpu->env.pregs[PR_CCS] & U_FLAG) ? 1 : 0;
> +}
> +
> static bool cris_cpu_has_work(CPUState *cs)
> {
> return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
> @@ -265,6 +272,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
> cc->has_work = cris_cpu_has_work;
> cc->do_interrupt = cris_cpu_do_interrupt;
> cc->dump_state = cris_cpu_dump_state;
> + cc->mmu_index = cris_cpu_mmu_index;
> cc->set_pc = cris_cpu_set_pc;
> cc->gdb_read_register = cris_cpu_gdb_read_register;
> cc->gdb_write_register = cris_cpu_gdb_write_register;
> diff --git a/target-cris/cpu.h b/target-cris/cpu.h
> index 15a0497..0914103 100644
> --- a/target-cris/cpu.h
> +++ b/target-cris/cpu.h
> @@ -238,10 +238,6 @@ static inline CPUCRISState *cpu_init(const char *cpu_model)
> #define MMU_MODE0_SUFFIX _kernel
> #define MMU_MODE1_SUFFIX _user
> #define MMU_USER_IDX 1
> -static inline int cpu_mmu_index (CPUCRISState *env)
> -{
> - return !!(env->pregs[PR_CCS] & U_FLAG);
> -}
>
> int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
> int mmu_idx);
> diff --git a/target-cris/translate.c b/target-cris/translate.c
> index 617e1b4..29e9f63 100644
> --- a/target-cris/translate.c
> +++ b/target-cris/translate.c
> @@ -1125,7 +1125,7 @@ static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
>
> static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
> {
> - int mem_index = cpu_mmu_index(dc->env);
> + int mem_index = cpu_mmu_index(CPU(cris_env_get_cpu(dc->env)));
>
> /* If we get a fault on a delayslot we must keep the jmp state in
> the cpu-state to be able to re-execute the jmp. */
> @@ -1139,7 +1139,7 @@ static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
> static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
> unsigned int size, int sign)
> {
> - int mem_index = cpu_mmu_index(dc->env);
> + int mem_index = cpu_mmu_index(CPU(cris_env_get_cpu(dc->env)));
>
> /* If we get a fault on a delayslot we must keep the jmp state in
> the cpu-state to be able to re-execute the jmp. */
> @@ -1169,7 +1169,7 @@ static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
> static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
> unsigned int size)
> {
> - int mem_index = cpu_mmu_index(dc->env);
> + int mem_index = cpu_mmu_index(CPU(cris_env_get_cpu(dc->env)));
>
> /* If we get a fault on a delayslot we must keep the jmp state in
> the cpu-state to be able to re-execute the jmp. */
> diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
> index d6ef084..0ade05b 100644
> --- a/target-cris/translate_v10.c
> +++ b/target-cris/translate_v10.c
> @@ -96,7 +96,7 @@ static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val,
> static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val,
> unsigned int size)
> {
> - int mem_index = cpu_mmu_index(dc->env);
> + int mem_index = cpu_mmu_index(CPU(cris_env_get_cpu(dc->env)));
>
> /* If we get a fault on a delayslot we must keep the jmp state in
> the cpu-state to be able to re-execute the jmp. */
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index fa92950..a623383 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -2676,6 +2676,16 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
> cpu->env.eip = tb->pc - tb->cs_base;
> }
>
> +static int x86_cpu_mmu_index(const CPUState *cs)
> +{
> + X86CPU *cpu = X86_CPU(cs);
> + CPUX86State *env = &cpu->env;
> +
> + return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
> + ((env->hflags & HF_SMAP_MASK) && (env->eflags & AC_MASK))
> + ? MMU_KSMAP_IDX : MMU_KERNEL_IDX;
> +}
> +
> static bool x86_cpu_has_work(CPUState *cs)
> {
> X86CPU *cpu = X86_CPU(cs);
> @@ -2713,6 +2723,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
> cc->has_work = x86_cpu_has_work;
> cc->do_interrupt = x86_cpu_do_interrupt;
> cc->dump_state = x86_cpu_dump_state;
> + cc->mmu_index = x86_cpu_mmu_index;
> cc->set_pc = x86_cpu_set_pc;
> cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
> cc->gdb_read_register = x86_cpu_gdb_read_register;
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index 6d46c75..fd16f20 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -1123,12 +1123,6 @@ static inline CPUX86State *cpu_init(const char *cpu_model)
> #define MMU_KERNEL_IDX 0
> #define MMU_USER_IDX 1
> #define MMU_KSMAP_IDX 2
> -static inline int cpu_mmu_index (CPUX86State *env)
> -{
> - return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
> - ((env->hflags & HF_SMAP_MASK) && (env->eflags & AC_MASK))
> - ? MMU_KSMAP_IDX : MMU_KERNEL_IDX;
> -}
>
> #define CC_DST (env->cc_dst)
> #define CC_SRC (env->cc_src)
> diff --git a/target-i386/translate.c b/target-i386/translate.c
> index 6d87900..2e8e8d5 100644
> --- a/target-i386/translate.c
> +++ b/target-i386/translate.c
> @@ -8291,7 +8291,7 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
> /* select memory access functions */
> dc->mem_index = 0;
> if (flags & HF_SOFTMMU_MASK) {
> - dc->mem_index = (cpu_mmu_index(env) + 1) << 2;
> + dc->mem_index = (cpu_mmu_index(cs) + 1) << 2;
> }
> dc->cpuid_features = env->features[FEAT_1_EDX];
> dc->cpuid_ext_features = env->features[FEAT_1_ECX];
> diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
> index a251a02..11f54e7 100644
> --- a/target-lm32/cpu.h
> +++ b/target-lm32/cpu.h
> @@ -36,10 +36,6 @@ typedef struct CPULM32State CPULM32State;
>
> #define NB_MMU_MODES 1
> #define TARGET_PAGE_BITS 12
> -static inline int cpu_mmu_index(CPULM32State *env)
> -{
> - return 0;
> -}
>
> #define TARGET_PHYS_ADDR_SPACE_BITS 32
> #define TARGET_VIRT_ADDR_SPACE_BITS 32
> diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
> index 7d66ed0..00454ab 100644
> --- a/target-m68k/cpu.c
> +++ b/target-m68k/cpu.c
> @@ -30,6 +30,13 @@ static void m68k_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.pc = value;
> }
>
> +static int m68k_cpu_mmu_index(const CPUState *cs)
> +{
> + M68kCPU *cpu = M68K_CPU(cs);
> +
> + return (cpu->env.sr & SR_S) == 0 ? MMU_USER_IDX : 0;
> +}
> +
> static bool m68k_cpu_has_work(CPUState *cs)
> {
> return cs->interrupt_request & CPU_INTERRUPT_HARD;
> @@ -197,6 +204,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
> cc->has_work = m68k_cpu_has_work;
> cc->do_interrupt = m68k_cpu_do_interrupt;
> cc->dump_state = m68k_cpu_dump_state;
> + cc->mmu_index = m68k_cpu_mmu_index;
> cc->set_pc = m68k_cpu_set_pc;
> cc->gdb_read_register = m68k_cpu_gdb_read_register;
> cc->gdb_write_register = m68k_cpu_gdb_write_register;
> diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
> index 5f79d2a..d1291d8 100644
> --- a/target-m68k/cpu.h
> +++ b/target-m68k/cpu.h
> @@ -232,10 +232,6 @@ static inline CPUM68KState *cpu_init(const char *cpu_model)
> #define MMU_MODE0_SUFFIX _kernel
> #define MMU_MODE1_SUFFIX _user
> #define MMU_USER_IDX 1
> -static inline int cpu_mmu_index (CPUM68KState *env)
> -{
> - return (env->sr & SR_S) == 0 ? 1 : 0;
> -}
>
> int cpu_m68k_handle_mmu_fault(CPUM68KState *env, target_ulong address, int rw,
> int mmu_idx);
> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
> index 6104939..929efd8 100644
> --- a/target-microblaze/cpu.c
> +++ b/target-microblaze/cpu.c
> @@ -33,6 +33,20 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.sregs[SR_PC] = value;
> }
>
> +static int mb_cpu_mmu_index(const CPUState *cs)
> +{
> + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
> +
> + /* Are we in nommu mode?. */
> + if (!(cpu->env.sregs[SR_MSR] & MSR_VM)) {
> + return MMU_NOMMU_IDX;
> + }
> + if (cpu->env.sregs[SR_MSR] & MSR_UM) {
> + return MMU_USER_IDX;
> + }
> + return MMU_KERNEL_IDX;
> +}
> +
> static bool mb_cpu_has_work(CPUState *cs)
> {
> return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
> @@ -147,6 +161,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
> cc->has_work = mb_cpu_has_work;
> cc->do_interrupt = mb_cpu_do_interrupt;
> cc->dump_state = mb_cpu_dump_state;
> + cc->mmu_index = mb_cpu_mmu_index;
> cc->set_pc = mb_cpu_set_pc;
> cc->gdb_read_register = mb_cpu_gdb_read_register;
> cc->gdb_write_register = mb_cpu_gdb_write_register;
> diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
> index 23f96f8..a81f899 100644
> --- a/target-microblaze/cpu.h
> +++ b/target-microblaze/cpu.h
> @@ -316,17 +316,6 @@ static inline CPUMBState *cpu_init(const char *cpu_model)
> #define MMU_USER_IDX 2
> /* See NB_MMU_MODES further up the file. */
>
> -static inline int cpu_mmu_index (CPUMBState *env)
> -{
> - /* Are we in nommu mode?. */
> - if (!(env->sregs[SR_MSR] & MSR_VM))
> - return MMU_NOMMU_IDX;
> -
> - if (env->sregs[SR_MSR] & MSR_UM)
> - return MMU_USER_IDX;
> - return MMU_KERNEL_IDX;
> -}
> -
> int cpu_mb_handle_mmu_fault(CPUMBState *env, target_ulong address, int rw,
> int mmu_idx);
> #define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
> diff --git a/target-microblaze/mmu.c b/target-microblaze/mmu.c
> index 73bf805..9182934 100644
> --- a/target-microblaze/mmu.c
> +++ b/target-microblaze/mmu.c
> @@ -218,6 +218,7 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn)
>
> void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
> {
> + MicroBlazeCPU *cpu = mb_env_get_cpu(env);
> unsigned int i;
> D(qemu_log("%s rn=%d=%x old=%x\n", __func__, rn, v, env->mmu.regs[rn]));
>
> @@ -277,7 +278,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
> }
>
> hit = mmu_translate(&env->mmu, &lu,
> - v & TLB_EPN_MASK, 0, cpu_mmu_index(env));
> + v & TLB_EPN_MASK, 0, cpu_mmu_index(CPU(cpu)));
> if (hit) {
> env->mmu.regs[MMU_R_TLBX] = lu.idx;
> } else
> diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
> index 0673176..f4dbe11 100644
> --- a/target-microblaze/translate.c
> +++ b/target-microblaze/translate.c
> @@ -440,7 +440,7 @@ static void dec_msr(DisasContext *dc)
> {
> TCGv t0, t1;
> unsigned int sr, to, rn;
> - int mem_index = cpu_mmu_index(dc->env);
> + int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
>
> sr = dc->imm & ((1 << 14) - 1);
> to = dc->imm & (1 << 14);
> @@ -751,7 +751,7 @@ static void dec_bit(DisasContext *dc)
> {
> TCGv t0, t1;
> unsigned int op;
> - int mem_index = cpu_mmu_index(dc->env);
> + int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
>
> op = dc->ir & ((1 << 9) - 1);
> switch (op) {
> @@ -874,7 +874,7 @@ static void dec_imm(DisasContext *dc)
> static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
> unsigned int size)
> {
> - int mem_index = cpu_mmu_index(dc->env);
> + int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
>
> if (size == 1) {
> tcg_gen_qemu_ld8u(dst, addr, mem_index);
> @@ -1093,7 +1093,7 @@ static void dec_load(DisasContext *dc)
> static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
> unsigned int size)
> {
> - int mem_index = cpu_mmu_index(dc->env);
> + int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
>
> if (size == 1)
> tcg_gen_qemu_st8(val, addr, mem_index);
> @@ -1308,7 +1308,7 @@ static void dec_bcc(DisasContext *dc)
> static void dec_br(DisasContext *dc)
> {
> unsigned int dslot, link, abs, mbar;
> - int mem_index = cpu_mmu_index(dc->env);
> + int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
>
> dslot = dc->ir & (1 << 20);
> abs = dc->ir & (1 << 19);
> @@ -1440,7 +1440,7 @@ static inline void do_rte(DisasContext *dc)
> static void dec_rts(DisasContext *dc)
> {
> unsigned int b_bit, i_bit, e_bit;
> - int mem_index = cpu_mmu_index(dc->env);
> + int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
>
> i_bit = dc->ir & (1 << 21);
> b_bit = dc->ir & (1 << 22);
> @@ -1616,7 +1616,7 @@ static void dec_null(DisasContext *dc)
> /* Insns connected to FSL or AXI stream attached devices. */
> static void dec_stream(DisasContext *dc)
> {
> - int mem_index = cpu_mmu_index(dc->env);
> + int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
> TCGv_i32 t_id, t_ctrl;
> int ctrl;
>
> diff --git a/target-mips/cpu.c b/target-mips/cpu.c
> index 0a2dc46..cb916f3 100644
> --- a/target-mips/cpu.c
> +++ b/target-mips/cpu.c
> @@ -45,6 +45,13 @@ static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
> env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
> }
>
> +static int mips_cpu_mmu_index(const CPUState *cs)
> +{
> + MIPSCPU *cpu = MIPS_CPU(cs);
> +
> + return cpu->env.hflags & MIPS_HFLAG_KSU;
> +}
> +
> static bool mips_cpu_has_work(CPUState *cs)
> {
> MIPSCPU *cpu = MIPS_CPU(cs);
> @@ -129,6 +136,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
> cc->has_work = mips_cpu_has_work;
> cc->do_interrupt = mips_cpu_do_interrupt;
> cc->dump_state = mips_cpu_dump_state;
> + cc->mmu_index = mips_cpu_mmu_index;
> cc->set_pc = mips_cpu_set_pc;
> cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
> cc->gdb_read_register = mips_cpu_gdb_read_register;
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index dff2836..22643ff 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -516,10 +516,6 @@ extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
> #define MMU_MODE1_SUFFIX _super
> #define MMU_MODE2_SUFFIX _user
> #define MMU_USER_IDX 2
> -static inline int cpu_mmu_index (CPUMIPSState *env)
> -{
> - return env->hflags & MIPS_HFLAG_KSU;
> -}
>
> static inline int cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
> {
> diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h
> index 778cfc0..affcfca 100644
> --- a/target-moxie/cpu.h
> +++ b/target-moxie/cpu.h
> @@ -136,11 +136,6 @@ static inline CPUMoxieState *cpu_init(const char *cpu_model)
> #define cpu_gen_code cpu_moxie_gen_code
> #define cpu_signal_handler cpu_moxie_signal_handler
>
> -static inline int cpu_mmu_index(CPUMoxieState *env)
> -{
> - return 0;
> -}
> -
> #include "exec/cpu-all.h"
> #include "exec/exec-all.h"
>
> diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
> index ca8495f..4872fcf 100644
> --- a/target-openrisc/cpu.c
> +++ b/target-openrisc/cpu.c
> @@ -27,6 +27,16 @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.pc = value;
> }
>
> +static int openrisc_cpu_mmu_index(const CPUState *cs)
> +{
> + OpenRISCCPU *cpu = OPENRISC_CPU(cs);
> +
> + if (!(cpu->env.sr & SR_IME)) {
> + return MMU_NOMMU_IDX;
> + }
> + return (cpu->env.sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX;
> +}
> +
> static bool openrisc_cpu_has_work(CPUState *cs)
> {
> return cs->interrupt_request & (CPU_INTERRUPT_HARD |
> @@ -162,6 +172,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
> cc->has_work = openrisc_cpu_has_work;
> cc->do_interrupt = openrisc_cpu_do_interrupt;
> cc->dump_state = openrisc_cpu_dump_state;
> + cc->mmu_index = openrisc_cpu_mmu_index;
> cc->set_pc = openrisc_cpu_set_pc;
> cc->gdb_read_register = openrisc_cpu_gdb_read_register;
> cc->gdb_write_register = openrisc_cpu_gdb_write_register;
> diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
> index 4a27f22..2a1ca92 100644
> --- a/target-openrisc/cpu.h
> +++ b/target-openrisc/cpu.h
> @@ -409,14 +409,6 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
> *flags = (env->flags & D_FLAG);
> }
>
> -static inline int cpu_mmu_index(CPUOpenRISCState *env)
> -{
> - if (!(env->sr & SR_IME)) {
> - return MMU_NOMMU_IDX;
> - }
> - return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX;
> -}
> -
> #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
>
> #include "exec/exec-all.h"
> diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
> index 723b77d..ea242da 100644
> --- a/target-openrisc/translate.c
> +++ b/target-openrisc/translate.c
> @@ -1679,7 +1679,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
> dc->ppc = pc_start;
> dc->pc = pc_start;
> dc->flags = cpu->env.cpucfgr;
> - dc->mem_idx = cpu_mmu_index(&cpu->env);
> + dc->mem_idx = cpu_mmu_index(cs);
> dc->synced_flags = dc->tb_flags = tb->flags;
> dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
> dc->singlestep_enabled = cs->singlestep_enabled;
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 70c1ef5..9c99f0d 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1183,10 +1183,6 @@ static inline CPUPPCState *cpu_init(const char *cpu_model)
> #define MMU_MODE1_SUFFIX _kernel
> #define MMU_MODE2_SUFFIX _hypv
> #define MMU_USER_IDX 0
> -static inline int cpu_mmu_index (CPUPPCState *env)
> -{
> - return env->mmu_idx;
> -}
>
> #include "exec/cpu-all.h"
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index b552451..e4bcf74 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8437,6 +8437,13 @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.nip = value;
> }
>
> +static int ppc_cpu_mmu_index(const CPUState *cs)
> +{
> + PowerPCCPU *cpu = POWERPC_CPU(cs);
> +
> + return cpu->env.mmu_idx;
> +}
> +
> static bool ppc_cpu_has_work(CPUState *cs)
> {
> PowerPCCPU *cpu = POWERPC_CPU(cs);
> @@ -8573,6 +8580,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
> cc->do_interrupt = ppc_cpu_do_interrupt;
> cc->dump_state = ppc_cpu_dump_state;
> cc->dump_statistics = ppc_cpu_dump_statistics;
> + cc->mmu_index = ppc_cpu_mmu_index;
> cc->set_pc = ppc_cpu_set_pc;
> cc->gdb_read_register = ppc_cpu_gdb_read_register;
> cc->gdb_write_register = ppc_cpu_gdb_write_register;
> diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
> index a4c7a33..6b200fe 100644
> --- a/target-s390x/cpu.c
> +++ b/target-s390x/cpu.c
> @@ -65,6 +65,17 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.psw.addr = value;
> }
>
> +static int s390_cpu_mmu_index(const CPUState *cs)
> +{
> + S390CPU *cpu = S390_CPU(cs);
> +
> + if (cpu->env.psw.mask & PSW_MASK_PSTATE) {
> + return 1;
> + }
> +
> + return 0;
> +}
> +
> static bool s390_cpu_has_work(CPUState *cs)
> {
> S390CPU *cpu = S390_CPU(cs);
> @@ -229,6 +240,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
> cc->has_work = s390_cpu_has_work;
> cc->do_interrupt = s390_cpu_do_interrupt;
> cc->dump_state = s390_cpu_dump_state;
> + cc->mmu_index = s390_cpu_mmu_index;
> cc->set_pc = s390_cpu_set_pc;
> cc->gdb_read_register = s390_cpu_gdb_read_register;
> cc->gdb_write_register = s390_cpu_gdb_write_register;
> diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
> index 3b588af..d7970e6 100644
> --- a/target-s390x/cpu.h
> +++ b/target-s390x/cpu.h
> @@ -273,15 +273,6 @@ typedef struct CPUS390XState {
> #define FLAG_MASK_64 (PSW_MASK_64 >> 32)
> #define FLAG_MASK_32 0x00001000
>
> -static inline int cpu_mmu_index (CPUS390XState *env)
> -{
> - if (env->psw.mask & PSW_MASK_PSTATE) {
> - return 1;
> - }
> -
> - return 0;
> -}
> -
> static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
> target_ulong *cs_base, int *flags)
> {
> diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
> index 5bf6d9f..df1c0e8 100644
> --- a/target-sh4/cpu.c
> +++ b/target-sh4/cpu.c
> @@ -39,6 +39,13 @@ static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
> cpu->env.flags = tb->flags;
> }
>
> +static int superh_cpu_mmu_index(const CPUState *cs)
> +{
> + SuperHCPU *cpu = SUPERH_CPU(cs);
> +
> + return (cpu->env.sr & SR_MD) == 0 ? 1 : 0;
> +}
> +
> static bool superh_cpu_has_work(CPUState *cs)
> {
> return cs->interrupt_request & CPU_INTERRUPT_HARD;
> @@ -291,6 +298,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
> cc->has_work = superh_cpu_has_work;
> cc->do_interrupt = superh_cpu_do_interrupt;
> cc->dump_state = superh_cpu_dump_state;
> + cc->mmu_index = superh_cpu_mmu_index;
> cc->set_pc = superh_cpu_set_pc;
> cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
> cc->gdb_read_register = superh_cpu_gdb_read_register;
> diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
> index 2eafc2d..6125c20 100644
> --- a/target-sh4/cpu.h
> +++ b/target-sh4/cpu.h
> @@ -240,10 +240,6 @@ static inline CPUSH4State *cpu_init(const char *cpu_model)
> #define MMU_MODE0_SUFFIX _kernel
> #define MMU_MODE1_SUFFIX _user
> #define MMU_USER_IDX 1
> -static inline int cpu_mmu_index (CPUSH4State *env)
> -{
> - return (env->sr & SR_MD) == 0 ? 1 : 0;
> -}
>
> #include "exec/cpu-all.h"
>
> diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
> index ede2c80..1d27f9e 100644
> --- a/target-sparc/cpu.c
> +++ b/target-sparc/cpu.c
> @@ -739,6 +739,30 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
> cpu->env.npc = tb->cs_base;
> }
>
> +static int sparc_cpu_mmu_index(const CPUState *cs)
> +{
> +#if defined(CONFIG_USER_ONLY)
> + return MMU_USER_IDX;
> +#else
> + SPARCCPU *cpu = SPARC_CPU(cs);
> + CPUSPARCState *env = &cpu->env;
> +
> +#if !defined(TARGET_SPARC64)
> + return env->psrs;
> +#else
> + if (env->tl > 0) {
> + return MMU_NUCLEUS_IDX;
> + } else if (cpu_hypervisor_mode(env)) {
> + return MMU_HYPV_IDX;
> + } else if (cpu_supervisor_mode(env)) {
> + return MMU_KERNEL_IDX;
> + } else {
> + return MMU_USER_IDX;
> + }
> +#endif
> +#endif
> +}
> +
> static bool sparc_cpu_has_work(CPUState *cs)
> {
> SPARCCPU *cpu = SPARC_CPU(cs);
> @@ -797,6 +821,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
> #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
> cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
> #endif
> + cc->mmu_index = sparc_cpu_mmu_index;
> cc->set_pc = sparc_cpu_set_pc;
> cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb;
> cc->gdb_read_register = sparc_cpu_gdb_read_register;
> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
> index adf6557..93590b8 100644
> --- a/target-sparc/cpu.h
> +++ b/target-sparc/cpu.h
> @@ -647,25 +647,6 @@ static inline int cpu_supervisor_mode(CPUSPARCState *env1)
> }
> #endif
>
> -static inline int cpu_mmu_index(CPUSPARCState *env1)
> -{
> -#if defined(CONFIG_USER_ONLY)
> - return MMU_USER_IDX;
> -#elif !defined(TARGET_SPARC64)
> - return env1->psrs;
> -#else
> - if (env1->tl > 0) {
> - return MMU_NUCLEUS_IDX;
> - } else if (cpu_hypervisor_mode(env1)) {
> - return MMU_HYPV_IDX;
> - } else if (cpu_supervisor_mode(env1)) {
> - return MMU_KERNEL_IDX;
> - } else {
> - return MMU_USER_IDX;
> - }
> -#endif
> -}
> -
> static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
> {
> #if !defined (TARGET_SPARC64)
> diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
> index ef12a0a..9eb096e 100644
> --- a/target-sparc/mmu_helper.c
> +++ b/target-sparc/mmu_helper.c
> @@ -842,7 +842,7 @@ hwaddr sparc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
> SPARCCPU *cpu = SPARC_CPU(cs);
> CPUSPARCState *env = &cpu->env;
> hwaddr phys_addr;
> - int mmu_idx = cpu_mmu_index(env);
> + int mmu_idx = cpu_mmu_index(cs);
> MemoryRegionSection section;
>
> if (cpu_sparc_get_phys_page(env, &phys_addr, addr, 2, mmu_idx) != 0) {
> diff --git a/target-sparc/translate.c b/target-sparc/translate.c
> index 36615f1..73f8b9c 100644
> --- a/target-sparc/translate.c
> +++ b/target-sparc/translate.c
> @@ -5241,7 +5241,7 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
> last_pc = dc->pc;
> dc->npc = (target_ulong) tb->cs_base;
> dc->cc_op = CC_OP_DYNAMIC;
> - dc->mem_idx = cpu_mmu_index(env);
> + dc->mem_idx = cpu_mmu_index(cs);
> dc->def = env->def;
> dc->fpu_enabled = tb_fpu_enabled(tb->flags);
> dc->address_mask_32bit = tb_am_enabled(tb->flags);
> diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
> index 1cfe50a..3ed9ea3 100644
> --- a/target-unicore32/cpu.c
> +++ b/target-unicore32/cpu.c
> @@ -23,6 +23,13 @@ static void uc32_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.regs[31] = value;
> }
>
> +static int uc32_cpu_mmu_index(const CPUState *cs)
> +{
> + UniCore32CPU *cpu = UNICORE32_CPU(cs);
> +
> + return (cpu->env.uncached_asr & ASR_M) == ASR_MODE_USER ? MMU_USER_IDX : 0;
> +}
> +
> static bool uc32_cpu_has_work(CPUState *cs)
> {
> return cs->interrupt_request &
> @@ -147,6 +154,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
> cc->has_work = uc32_cpu_has_work;
> cc->do_interrupt = uc32_cpu_do_interrupt;
> cc->dump_state = uc32_cpu_dump_state;
> + cc->mmu_index = uc32_cpu_mmu_index;
> cc->set_pc = uc32_cpu_set_pc;
> #ifndef CONFIG_USER_ONLY
> cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
> diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
> index 1db7419..07693d5 100644
> --- a/target-unicore32/cpu.h
> +++ b/target-unicore32/cpu.h
> @@ -137,10 +137,6 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int
> #define MMU_MODE0_SUFFIX _kernel
> #define MMU_MODE1_SUFFIX _user
> #define MMU_USER_IDX 1
> -static inline int cpu_mmu_index(CPUUniCore32State *env)
> -{
> - return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0;
> -}
>
> #include "exec/cpu-all.h"
> #include "cpu-qom.h"
> diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
> index 46573c6..f99feaa 100644
> --- a/target-xtensa/cpu.c
> +++ b/target-xtensa/cpu.c
> @@ -40,6 +40,13 @@ static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
> cpu->env.pc = value;
> }
>
> +static int xtensa_cpu_mmu_index(const CPUState *cs)
> +{
> + XtensaCPU *cpu = XTENSA_CPU(cs);
> +
> + return xtensa_get_cring(&cpu->env);
> +}
> +
> static bool xtensa_cpu_has_work(CPUState *cs)
> {
> XtensaCPU *cpu = XTENSA_CPU(cs);
> @@ -142,6 +149,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
> cc->has_work = xtensa_cpu_has_work;
> cc->do_interrupt = xtensa_cpu_do_interrupt;
> cc->dump_state = xtensa_cpu_dump_state;
> + cc->mmu_index = xtensa_cpu_mmu_index;
> cc->set_pc = xtensa_cpu_set_pc;
> cc->gdb_read_register = xtensa_cpu_gdb_read_register;
> cc->gdb_write_register = xtensa_cpu_gdb_write_register;
> diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
> index de27c8c..4fdaf20 100644
> --- a/target-xtensa/cpu.h
> +++ b/target-xtensa/cpu.h
> @@ -472,11 +472,6 @@ static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
> #define MMU_MODE2_SUFFIX _ring2
> #define MMU_MODE3_SUFFIX _ring3
>
> -static inline int cpu_mmu_index(CPUXtensaState *env)
> -{
> - return xtensa_get_cring(env);
> -}
> -
> #define XTENSA_TBFLAG_RING_MASK 0x3
> #define XTENSA_TBFLAG_EXCM 0x4
> #define XTENSA_TBFLAG_LITBASE 0x8
target-openrisc: Tested-by: Jia Liu <proljc@gmail.com>
> --
> 1.8.1.4
>
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 02/41] cpu: Turn cpu_mmu_index() into a CPUClass hook
2013-09-04 12:42 ` Jia Liu
@ 2013-09-04 12:55 ` Andreas Färber
0 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 12:55 UTC (permalink / raw)
To: Jia Liu, qemu-devel@nongnu.org
Cc: Peter Maydell, Anthony Green, Alexander Graf, Blue Swirl,
Max Filippov, Michael Walle, qemu-ppc, Paolo Bonzini,
Edgar E. Iglesias, Guan Xuetao, Aurelien Jarno, Richard Henderson
Am 04.09.2013 14:42, schrieb Jia Liu:
> On Wed, Sep 4, 2013 at 5:04 PM, Andreas Färber <afaerber@suse.de> wrote:
>> Default to 0.
>>
>> Signed-off-by: Andreas Färber <afaerber@suse.de>
Paolo has indicated that patches 2 and 3 shouldn't be applied since they
touch on TCG hot paths, replacing an inline function with a dispatched
one, thereby possibly leading to performance regressions.
Unfortunately that still means for me that I need to write a boilerplate
inline function returning MMU index 0 for each of my new microcontroller
targets... :/
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [RFC qom-cpu 03/41] cpu: Turn cpu_get_tb_cpu_state() into a CPUClass hook
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 01/41] cpu: Turn cpu_has_work() into a CPUClass hook Andreas Färber
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 02/41] cpu: Turn cpu_mmu_index() " Andreas Färber
@ 2013-09-04 9:04 ` Andreas Färber
2013-09-04 10:26 ` Paolo Bonzini
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 04/41] cpu: Turn cpu_handle_mmu_fault() " Andreas Färber
` (40 subsequent siblings)
43 siblings, 1 reply; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:04 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Anthony Green, Alexander Graf, Blue Swirl,
Max Filippov, Michael Walle, open list:PowerPC, Paul Brook,
Edgar E. Iglesias, Guan Xuetao, Andreas Färber,
Aurelien Jarno, Richard Henderson
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cpu-exec.c | 6 ++++--
exec.c | 10 ++++++----
hw/i386/kvmvapic.c | 8 +++++---
include/qom/cpu.h | 4 ++++
target-alpha/cpu.c | 24 ++++++++++++++++++++++++
target-alpha/cpu.h | 21 ---------------------
target-arm/cpu.c | 28 ++++++++++++++++++++++++++++
target-arm/cpu.h | 24 ------------------------
target-cris/cpu.c | 14 ++++++++++++++
target-cris/cpu.h | 10 ----------
target-i386/cpu.c | 13 +++++++++++++
target-i386/cpu.h | 9 ---------
target-lm32/cpu.c | 11 +++++++++++
target-lm32/cpu.h | 9 ---------
target-m68k/cpu.c | 14 ++++++++++++++
target-m68k/cpu.h | 11 -----------
target-microblaze/cpu.c | 13 +++++++++++++
target-microblaze/cpu.h | 9 ---------
target-mips/cpu.c | 12 ++++++++++++
target-mips/cpu.h | 8 --------
target-moxie/cpu.c | 11 +++++++++++
target-moxie/cpu.h | 8 --------
target-openrisc/cpu.c | 12 ++++++++++++
target-openrisc/cpu.h | 10 ----------
target-ppc/cpu.h | 8 --------
target-ppc/translate_init.c | 11 +++++++++++
target-s390x/cpu.c | 13 +++++++++++++
target-s390x/cpu.h | 9 ---------
target-sh4/cpu.c | 17 +++++++++++++++++
target-sh4/cpu.h | 13 -------------
target-sparc/cpu.c | 31 +++++++++++++++++++++++++++++++
target-sparc/cpu.h | 27 ---------------------------
target-unicore32/cpu.c | 14 ++++++++++++++
target-unicore32/cpu.h | 11 -----------
target-xtensa/cpu.c | 34 ++++++++++++++++++++++++++++++++++
target-xtensa/cpu.h | 30 ------------------------------
translate-all.c | 18 ++++++++++++------
37 files changed, 303 insertions(+), 232 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index e9866b8..c839f80 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -153,14 +153,16 @@ static TranslationBlock *tb_find_slow(CPUArchState *env,
static inline TranslationBlock *tb_find_fast(CPUArchState *env)
{
+ CPUState *cpu = ENV_GET_CPU(env);
+ CPUClass *cc = CPU_GET_CLASS(cpu);
TranslationBlock *tb;
- target_ulong cs_base, pc;
+ vaddr cs_base, pc;
int flags;
/* we record a subset of the CPU state. It will
always be the same before a given translated block
is executed. */
- cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
+ cc->get_tb_cpu_state(cpu, &pc, &cs_base, &flags);
tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
tb->flags != flags)) {
diff --git a/exec.c b/exec.c
index 87b0b39..4354eac 100644
--- a/exec.c
+++ b/exec.c
@@ -1478,8 +1478,10 @@ static const MemoryRegionOps notdirty_mem_ops = {
/* Generate a debug exception if a watchpoint has been hit. */
static void check_watchpoint(int offset, int len_mask, int flags)
{
- CPUArchState *env = current_cpu->env_ptr;
- target_ulong pc, cs_base;
+ CPUState *cpu = current_cpu;
+ CPUArchState *env = cpu->env_ptr;
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+ vaddr pc, cs_base;
target_ulong vaddr;
CPUWatchpoint *wp;
int cpu_flags;
@@ -1488,7 +1490,7 @@ static void check_watchpoint(int offset, int len_mask, int flags)
/* We re-entered the check after replacing the TB. Now raise
* the debug interrupt so that is will trigger after the
* current instruction. */
- cpu_interrupt(ENV_GET_CPU(env), CPU_INTERRUPT_DEBUG);
+ cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
return;
}
vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
@@ -1503,7 +1505,7 @@ static void check_watchpoint(int offset, int len_mask, int flags)
env->exception_index = EXCP_DEBUG;
cpu_loop_exit(env);
} else {
- cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
+ cc->get_tb_cpu_state(cpu, &pc, &cs_base, &cpu_flags);
tb_gen_code(env, pc, cs_base, cpu_flags, 1);
cpu_resume_from_signal(env, NULL);
}
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index d3a6fbe..7295e5b 100644
--- a/hw/i386/kvmvapic.c
+++ b/hw/i386/kvmvapic.c
@@ -395,8 +395,8 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
VAPICHandlers *handlers;
uint8_t opcode[2];
uint32_t imm32;
- target_ulong current_pc = 0;
- target_ulong current_cs_base = 0;
+ vaddr current_pc = 0;
+ vaddr current_cs_base = 0;
int current_flags = 0;
if (smp_cpus == 1) {
@@ -406,8 +406,10 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
}
if (!kvm_enabled()) {
+ CPUClass *cc = CPU_GET_CLASS(cs);
+
cpu_restore_state(env, env->mem_io_pc);
- cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base,
+ cc->get_tb_cpu_state(cs, ¤t_pc, ¤t_cs_base,
¤t_flags);
}
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index c78d572..3d6b66e 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -80,6 +80,8 @@ struct TranslationBlock;
* @get_paging_enabled: Callback for inquiring whether paging is enabled.
* @get_memory_mapping: Callback for obtaining the memory mappings.
* @set_pc: Callback for setting the Program Counter register.
+ * @get_tb_cpu_state: Callback for obtaining state for a TCG
+ * #TranslationBlock.
* @synchronize_from_tb: Callback for synchronizing state from a TCG
* #TranslationBlock.
* @get_phys_page_debug: Callback for obtaining a physical address.
@@ -115,6 +117,8 @@ typedef struct CPUClass {
void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
Error **errp);
void (*set_pc)(CPUState *cpu, vaddr value);
+ void (*get_tb_cpu_state)(const CPUState *cpu, vaddr *pc, vaddr *cs_base,
+ int *flags);
void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index 15d6f1f..bb1eddc 100644
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -31,6 +31,29 @@ static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static void alpha_cpu_get_tb_cpu_state(const CPUState *cs, vaddr *pc,
+ vaddr *cs_base, int *pflags)
+{
+ AlphaCPU *cpu = ALPHA_CPU(cs);
+ CPUAlphaState *env = &cpu->env;
+ int flags = 0;
+
+ *pc = env->pc;
+ *cs_base = 0;
+
+ if (env->pal_mode) {
+ flags = TB_FLAGS_PAL_MODE;
+ } else {
+ flags = env->ps & PS_USER_MODE;
+ }
+ if (env->fen) {
+ flags |= TB_FLAGS_FEN;
+ }
+ flags |= env->amask << TB_FLAGS_AMASK_SHIFT;
+
+ *pflags = flags;
+}
+
static int alpha_cpu_mmu_index(const CPUState *cs)
{
AlphaCPU *cpu = ALPHA_CPU(cs);
@@ -304,6 +327,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = alpha_cpu_dump_state;
cc->mmu_index = alpha_cpu_mmu_index;
cc->set_pc = alpha_cpu_set_pc;
+ cc->get_tb_cpu_state = alpha_cpu_get_tb_cpu_state;
cc->gdb_read_register = alpha_cpu_gdb_read_register;
cc->gdb_write_register = alpha_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index 808fe53..a4abce8 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -466,27 +466,6 @@ enum {
TB_FLAGS_AMASK_PREFETCH = AMASK_PREFETCH << TB_FLAGS_AMASK_SHIFT,
};
-static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
- target_ulong *cs_base, int *pflags)
-{
- int flags = 0;
-
- *pc = env->pc;
- *cs_base = 0;
-
- if (env->pal_mode) {
- flags = TB_FLAGS_PAL_MODE;
- } else {
- flags = env->ps & PS_USER_MODE;
- }
- if (env->fen) {
- flags |= TB_FLAGS_FEN;
- }
- flags |= env->amask << TB_FLAGS_AMASK_SHIFT;
-
- *pflags = flags;
-}
-
#include "exec/exec-all.h"
#endif /* !defined (__CPU_ALPHA_H__) */
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 6032a2c..53bf337 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -34,6 +34,33 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.regs[15] = value;
}
+static void arm_cpu_get_tb_cpu_state(const CPUState *cs, vaddr *pc,
+ vaddr *cs_base, int *flags)
+{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+ int privmode;
+
+ *pc = env->regs[15];
+ *cs_base = 0;
+ *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
+ | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
+ | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
+ | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
+ | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
+ if (arm_feature(env, ARM_FEATURE_M)) {
+ privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
+ } else {
+ privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
+ }
+ if (privmode) {
+ *flags |= ARM_TBFLAG_PRIV_MASK;
+ }
+ if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
+ *flags |= ARM_TBFLAG_VFPEN_MASK;
+ }
+}
+
static int arm_cpu_mmu_index(const CPUState *cs)
{
ARMCPU *cpu = ARM_CPU(cs);
@@ -908,6 +935,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = arm_cpu_dump_state;
cc->mmu_index = arm_cpu_mmu_index;
cc->set_pc = arm_cpu_set_pc;
+ cc->get_tb_cpu_state = arm_cpu_get_tb_cpu_state;
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 19fa4ee..161b9fd 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -786,30 +786,6 @@ static inline CPUARMState *cpu_init(const char *cpu_model)
#define ARM_TBFLAG_BSWAP_CODE(F) \
(((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
-static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
- target_ulong *cs_base, int *flags)
-{
- int privmode;
- *pc = env->regs[15];
- *cs_base = 0;
- *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT)
- | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT)
- | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT)
- | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT)
- | (env->bswap_code << ARM_TBFLAG_BSWAP_CODE_SHIFT);
- if (arm_feature(env, ARM_FEATURE_M)) {
- privmode = !((env->v7m.exception == 0) && (env->v7m.control & 1));
- } else {
- privmode = (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR;
- }
- if (privmode) {
- *flags |= ARM_TBFLAG_PRIV_MASK;
- }
- if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
- *flags |= ARM_TBFLAG_VFPEN_MASK;
- }
-}
-
#include "exec/exec-all.h"
/* Load an instruction and return it in the standard little-endian order */
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index 1e5b425..39a25ed 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -33,6 +33,19 @@ static void cris_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static void cris_cpu_get_tb_cpu_state(const CPUState *cs, vaddr *pc,
+ vaddr *cs_base, int *flags)
+{
+ CRISCPU *cpu = CRIS_CPU(cs);
+ CPUCRISState *env = &cpu->env;
+
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = env->dslot |
+ (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG |
+ X_FLAG | PFIX_FLAG));
+}
+
static int cris_cpu_mmu_index(const CPUState *cs)
{
CRISCPU *cpu = CRIS_CPU(cs);
@@ -274,6 +287,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = cris_cpu_dump_state;
cc->mmu_index = cris_cpu_mmu_index;
cc->set_pc = cris_cpu_set_pc;
+ cc->get_tb_cpu_state = cris_cpu_get_tb_cpu_state;
cc->gdb_read_register = cris_cpu_gdb_read_register;
cc->gdb_write_register = cris_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 0914103..9f1fa38 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -255,16 +255,6 @@ int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
#include "exec/cpu-all.h"
-static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
- target_ulong *cs_base, int *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *flags = env->dslot |
- (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
- | X_FLAG | PFIX_FLAG));
-}
-
#define cpu_list cris_cpu_list
void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index a623383..995d5ff 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2669,6 +2669,18 @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.eip = value;
}
+static void x86_cpu_get_tb_cpu_state(const CPUState *cs, vaddr *pc,
+ vaddr *cs_base, int *flags)
+{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
+ *cs_base = env->segs[R_CS].base;
+ *pc = *cs_base + env->eip;
+ *flags = env->hflags |
+ (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
+}
+
static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
{
X86CPU *cpu = X86_CPU(cs);
@@ -2725,6 +2737,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->dump_state = x86_cpu_dump_state;
cc->mmu_index = x86_cpu_mmu_index;
cc->set_pc = x86_cpu_set_pc;
+ cc->get_tb_cpu_state = x86_cpu_get_tb_cpu_state;
cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
cc->gdb_read_register = x86_cpu_gdb_read_register;
cc->gdb_write_register = x86_cpu_gdb_write_register;
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index fd16f20..999a46c 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1157,15 +1157,6 @@ void optimize_flags_init(void);
#include "exec/exec-all.h"
-static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
- target_ulong *cs_base, int *flags)
-{
- *cs_base = env->segs[R_CS].base;
- *pc = *cs_base + env->eip;
- *flags = env->hflags |
- (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
-}
-
void do_cpu_init(X86CPU *cpu);
void do_cpu_sipi(X86CPU *cpu);
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
index 4fa8605..7976d39 100644
--- a/target-lm32/cpu.c
+++ b/target-lm32/cpu.c
@@ -29,6 +29,16 @@ static void lm32_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static void lm32_cpu_get_tb_cpu_state(const CPUState *cs, vaddr *pc,
+ vaddr *cs_base, int *flags)
+{
+ LM32CPU *cpu = LM32_CPU(cs);
+
+ *pc = cpu->env.pc;
+ *cs_base = 0;
+ *flags = 0;
+}
+
static bool lm32_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request & CPU_INTERRUPT_HARD;
@@ -95,6 +105,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = lm32_cpu_do_interrupt;
cc->dump_state = lm32_cpu_dump_state;
cc->set_pc = lm32_cpu_set_pc;
+ cc->get_tb_cpu_state = lm32_cpu_get_tb_cpu_state;
cc->gdb_read_register = lm32_cpu_gdb_read_register;
cc->gdb_write_register = lm32_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index 11f54e7..a34f047 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -212,15 +212,6 @@ int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
#define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault
#include "exec/cpu-all.h"
-
-static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *pc,
- target_ulong *cs_base, int *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *flags = 0;
-}
-
#include "exec/exec-all.h"
#endif
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index 00454ab..6dbfe89 100644
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -30,6 +30,19 @@ static void m68k_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static void m68k_cpu_get_tb_cpu_state(const CPUState *cs, vaddr *pc,
+ vaddr *cs_base, int *flags)
+{
+ M68kCPU *cpu = M68K_CPU(cs);
+ CPUM68KState *env = &cpu->env;
+
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
+ | (env->sr & SR_S) /* Bit 13 */
+ | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
+}
+
static int m68k_cpu_mmu_index(const CPUState *cs)
{
M68kCPU *cpu = M68K_CPU(cs);
@@ -206,6 +219,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = m68k_cpu_dump_state;
cc->mmu_index = m68k_cpu_mmu_index;
cc->set_pc = m68k_cpu_set_pc;
+ cc->get_tb_cpu_state = m68k_cpu_get_tb_cpu_state;
cc->gdb_read_register = m68k_cpu_gdb_read_register;
cc->gdb_write_register = m68k_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index d1291d8..5c7992e 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -238,17 +238,6 @@ int cpu_m68k_handle_mmu_fault(CPUM68KState *env, target_ulong address, int rw,
#define cpu_handle_mmu_fault cpu_m68k_handle_mmu_fault
#include "exec/cpu-all.h"
-
-static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc,
- target_ulong *cs_base, int *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *flags = (env->fpcr & M68K_FPCR_PREC) /* Bit 6 */
- | (env->sr & SR_S) /* Bit 13 */
- | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
-}
-
#include "exec/exec-all.h"
#endif
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 929efd8..fbcdcc4 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -33,6 +33,18 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.sregs[SR_PC] = value;
}
+static void mb_cpu_get_tb_cpu_state(const CPUState *cs, vaddr *pc,
+ vaddr *cs_base, int *flags)
+{
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+ CPUMBState *env = &cpu->env;
+
+ *pc = env->sregs[SR_PC];
+ *cs_base = 0;
+ *flags = (env->iflags & IFLAGS_TB_MASK) |
+ (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
+}
+
static int mb_cpu_mmu_index(const CPUState *cs)
{
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
@@ -163,6 +175,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = mb_cpu_dump_state;
cc->mmu_index = mb_cpu_mmu_index;
cc->set_pc = mb_cpu_set_pc;
+ cc->get_tb_cpu_state = mb_cpu_get_tb_cpu_state;
cc->gdb_read_register = mb_cpu_gdb_read_register;
cc->gdb_write_register = mb_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index a81f899..d80f812 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -332,15 +332,6 @@ static inline target_ulong cpu_get_pc(CPUMBState *env)
return env->sregs[SR_PC];
}
-static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
- target_ulong *cs_base, int *flags)
-{
- *pc = env->sregs[SR_PC];
- *cs_base = 0;
- *flags = (env->iflags & IFLAGS_TB_MASK) |
- (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
-}
-
#if !defined(CONFIG_USER_ONLY)
void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
bool is_write, bool is_exec, int is_asi,
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index cb916f3..4aa06bb 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -35,6 +35,17 @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value)
}
}
+static void mips_cpu_get_tb_cpu_state(const CPUState *cs, vaddr *pc,
+ vaddr *cs_base, int *flags)
+{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+
+ *pc = env->active_tc.PC;
+ *cs_base = 0;
+ *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
+}
+
static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
{
MIPSCPU *cpu = MIPS_CPU(cs);
@@ -138,6 +149,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->dump_state = mips_cpu_dump_state;
cc->mmu_index = mips_cpu_mmu_index;
cc->set_pc = mips_cpu_set_pc;
+ cc->get_tb_cpu_state = mips_cpu_get_tb_cpu_state;
cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 22643ff..91217ed 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -659,14 +659,6 @@ hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
#endif
target_ulong exception_resume_pc (CPUMIPSState *env);
-static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
- target_ulong *cs_base, int *flags)
-{
- *pc = env->active_tc.PC;
- *cs_base = 0;
- *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
-}
-
static inline int mips_vpe_active(CPUMIPSState *env)
{
int active = 1;
diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
index 66f337e..9983c99 100644
--- a/target-moxie/cpu.c
+++ b/target-moxie/cpu.c
@@ -29,6 +29,16 @@ static void moxie_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static void moxie_cpu_get_tb_cpu_state(const CPUState *cs, vaddr *pc,
+ vaddr *cs_base, int *flags)
+{
+ MoxieCPU *cpu = MOXIE_CPU(cs);
+
+ *pc = cpu->env.pc;
+ *cs_base = 0;
+ *flags = 0;
+}
+
static bool moxie_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request & CPU_INTERRUPT_HARD;
@@ -108,6 +118,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->do_interrupt = moxie_cpu_do_interrupt;
cc->dump_state = moxie_cpu_dump_state;
cc->set_pc = moxie_cpu_set_pc;
+ cc->get_tb_cpu_state = moxie_cpu_get_tb_cpu_state;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_moxie_cpu;
diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h
index affcfca..7e33efe 100644
--- a/target-moxie/cpu.h
+++ b/target-moxie/cpu.h
@@ -139,14 +139,6 @@ static inline CPUMoxieState *cpu_init(const char *cpu_model)
#include "exec/cpu-all.h"
#include "exec/exec-all.h"
-static inline void cpu_get_tb_cpu_state(CPUMoxieState *env, target_ulong *pc,
- target_ulong *cs_base, int *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *flags = 0;
-}
-
int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address,
int rw, int mmu_idx);
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 4872fcf..107e5f9 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -27,6 +27,17 @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static void openrisc_cpu_get_tb_cpu_state(const CPUState *cs, vaddr *pc,
+ vaddr *cs_base, int *flags)
+{
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+
+ *pc = cpu->env.pc;
+ *cs_base = 0;
+ /* D_FLAG -- branch instruction exception */
+ *flags = (cpu->env.flags & D_FLAG);
+}
+
static int openrisc_cpu_mmu_index(const CPUState *cs)
{
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
@@ -174,6 +185,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = openrisc_cpu_dump_state;
cc->mmu_index = openrisc_cpu_mmu_index;
cc->set_pc = openrisc_cpu_set_pc;
+ cc->get_tb_cpu_state = openrisc_cpu_get_tb_cpu_state;
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 2a1ca92..a41c271 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -399,16 +399,6 @@ static inline CPUOpenRISCState *cpu_init(const char *cpu_model)
#include "exec/cpu-all.h"
-static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
- target_ulong *pc,
- target_ulong *cs_base, int *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- /* D_FLAG -- branch instruction exception */
- *flags = (env->flags & D_FLAG);
-}
-
#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
#include "exec/exec-all.h"
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 9c99f0d..2ebf0a1 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -2015,14 +2015,6 @@ static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
}
-static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
- target_ulong *cs_base, int *flags)
-{
- *pc = env->nip;
- *cs_base = 0;
- *flags = env->hflags;
-}
-
#if !defined(CONFIG_USER_ONLY)
static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
{
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index e4bcf74..338d8fe 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8437,6 +8437,16 @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.nip = value;
}
+static void ppc_cpu_get_tb_cpu_state(const CPUState *cs, vaddr *pc,
+ vaddr *cs_base, int *flags)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+
+ *pc = cpu->env.nip;
+ *cs_base = 0;
+ *flags = cpu->env.hflags;
+}
+
static int ppc_cpu_mmu_index(const CPUState *cs)
{
PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -8582,6 +8592,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_statistics = ppc_cpu_dump_statistics;
cc->mmu_index = ppc_cpu_mmu_index;
cc->set_pc = ppc_cpu_set_pc;
+ cc->get_tb_cpu_state = ppc_cpu_get_tb_cpu_state;
cc->gdb_read_register = ppc_cpu_gdb_read_register;
cc->gdb_write_register = ppc_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index 6b200fe..a4a5370 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -65,6 +65,18 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.psw.addr = value;
}
+static void s390_cpu_get_tb_cpu_state(const CPUState *cs, vaddr *pc,
+ vaddr *cs_base, int *flags)
+{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
+
+ *pc = env->psw.addr;
+ *cs_base = 0;
+ *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
+ ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
+}
+
static int s390_cpu_mmu_index(const CPUState *cs)
{
S390CPU *cpu = S390_CPU(cs);
@@ -242,6 +254,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = s390_cpu_dump_state;
cc->mmu_index = s390_cpu_mmu_index;
cc->set_pc = s390_cpu_set_pc;
+ cc->get_tb_cpu_state = s390_cpu_get_tb_cpu_state;
cc->gdb_read_register = s390_cpu_gdb_read_register;
cc->gdb_write_register = s390_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index d7970e6..cad092b 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -273,15 +273,6 @@ typedef struct CPUS390XState {
#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
#define FLAG_MASK_32 0x00001000
-static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
- target_ulong *cs_base, int *flags)
-{
- *pc = env->psw.addr;
- *cs_base = 0;
- *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
- ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
-}
-
/* While the PoO talks about ILC (a number between 1-3) what is actually
stored in LowCore is shifted left one bit (an even between 2-6). As
this is the actual length of the insn and therefore more useful, that
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index df1c0e8..647a527 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -31,6 +31,22 @@ static void superh_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static void superh_cpu_get_tb_cpu_state(const CPUState *cs, vaddr *pc,
+ vaddr *cs_base, int *flags)
+{
+ SuperHCPU *cpu = SUPERH_CPU(cs);
+ CPUSH4State *env = &cpu->env;
+
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL |
+ DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME)) /* Bits 0-3 */
+ | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */
+ | (env->sr & (SR_MD | SR_RB)) /* Bits 29-30 */
+ | (env->sr & SR_FD) /* Bit 15 */
+ | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
+}
+
static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
{
SuperHCPU *cpu = SUPERH_CPU(cs);
@@ -300,6 +316,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = superh_cpu_dump_state;
cc->mmu_index = superh_cpu_mmu_index;
cc->set_pc = superh_cpu_set_pc;
+ cc->get_tb_cpu_state = superh_cpu_get_tb_cpu_state;
cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
cc->gdb_read_register = superh_cpu_gdb_read_register;
cc->gdb_write_register = superh_cpu_gdb_write_register;
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 6125c20..42ecdd7 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -335,19 +335,6 @@ static inline int cpu_ptel_pr (uint32_t ptel)
#define TB_FLAG_PENDING_MOVCA (1 << 4)
-static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
- target_ulong *cs_base, int *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL
- | DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME)) /* Bits 0- 3 */
- | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */
- | (env->sr & (SR_MD | SR_RB)) /* Bits 29-30 */
- | (env->sr & SR_FD) /* Bit 15 */
- | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
-}
-
#include "exec/exec-all.h"
#endif /* _CPU_SH4_H */
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index 1d27f9e..49a4469 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -731,6 +731,36 @@ static void sparc_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.npc = value + 4;
}
+static void sparc_cpu_get_tb_cpu_state(const CPUState *cs, vaddr *pc,
+ vaddr *cs_base, int *flags)
+{
+ SPARCCPU *cpu = SPARC_CPU(cs);
+ CPUSPARCState *env = &cpu->env;
+
+ *pc = env->pc;
+ *cs_base = env->npc;
+#ifdef TARGET_SPARC64
+ /* AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled */
+ *flags = (env->pstate & PS_PRIV) /* 2 */
+ | ((env->lsu & (DMMU_E | IMMU_E)) >> 2) /* 1, 0 */
+ | ((env->tl & 0xff) << 8)
+ | (env->dmmu.mmu_primary_context << 16); /* 16... */
+ if (env->pstate & PS_AM) {
+ *flags |= TB_FLAG_AM_ENABLED;
+ }
+ if ((env->def->features & CPU_FEATURE_FLOAT) && (env->pstate & PS_PEF)
+ && (env->fprs & FPRS_FEF)) {
+ *flags |= TB_FLAG_FPU_ENABLED;
+ }
+#else
+ /* FPU enable . Supervisor */
+ *flags = env->psrs;
+ if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) {
+ *flags |= TB_FLAG_FPU_ENABLED;
+ }
+#endif
+}
+
static void sparc_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
{
SPARCCPU *cpu = SPARC_CPU(cs);
@@ -823,6 +853,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
#endif
cc->mmu_index = sparc_cpu_mmu_index;
cc->set_pc = sparc_cpu_set_pc;
+ cc->get_tb_cpu_state = sparc_cpu_get_tb_cpu_state;
cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb;
cc->gdb_read_register = sparc_cpu_gdb_read_register;
cc->gdb_write_register = sparc_cpu_gdb_write_register;
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 93590b8..f078851 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -683,33 +683,6 @@ trap_state* cpu_tsptr(CPUSPARCState* env);
#define TB_FLAG_FPU_ENABLED (1 << 4)
#define TB_FLAG_AM_ENABLED (1 << 5)
-static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
- target_ulong *cs_base, int *flags)
-{
- *pc = env->pc;
- *cs_base = env->npc;
-#ifdef TARGET_SPARC64
- // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
- *flags = (env->pstate & PS_PRIV) /* 2 */
- | ((env->lsu & (DMMU_E | IMMU_E)) >> 2) /* 1, 0 */
- | ((env->tl & 0xff) << 8)
- | (env->dmmu.mmu_primary_context << 16); /* 16... */
- if (env->pstate & PS_AM) {
- *flags |= TB_FLAG_AM_ENABLED;
- }
- if ((env->def->features & CPU_FEATURE_FLOAT) && (env->pstate & PS_PEF)
- && (env->fprs & FPRS_FEF)) {
- *flags |= TB_FLAG_FPU_ENABLED;
- }
-#else
- // FPU enable . Supervisor
- *flags = env->psrs;
- if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) {
- *flags |= TB_FLAG_FPU_ENABLED;
- }
-#endif
-}
-
static inline bool tb_fpu_enabled(int tb_flags)
{
#if defined(CONFIG_USER_ONLY)
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index 3ed9ea3..e5fddcf 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -23,6 +23,19 @@ static void uc32_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.regs[31] = value;
}
+static void uc32_cpu_get_tb_cpu_state(const CPUState *cs, vaddr *pc,
+ vaddr *cs_base, int *flags)
+{
+ UniCore32CPU *cpu = UNICORE32_CPU(cs);
+
+ *pc = cpu->env.regs[31];
+ *cs_base = 0;
+ *flags = 0;
+ if ((cpu->env.uncached_asr & ASR_M) != ASR_MODE_USER) {
+ *flags |= (1 << 6);
+ }
+}
+
static int uc32_cpu_mmu_index(const CPUState *cs)
{
UniCore32CPU *cpu = UNICORE32_CPU(cs);
@@ -156,6 +169,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = uc32_cpu_dump_state;
cc->mmu_index = uc32_cpu_mmu_index;
cc->set_pc = uc32_cpu_set_pc;
+ cc->get_tb_cpu_state = uc32_cpu_get_tb_cpu_state;
#ifndef CONFIG_USER_ONLY
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
#endif
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index 07693d5..75f5fa9 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -142,17 +142,6 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int
#include "cpu-qom.h"
#include "exec/exec-all.h"
-static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc,
- target_ulong *cs_base, int *flags)
-{
- *pc = env->regs[31];
- *cs_base = 0;
- *flags = 0;
- if ((env->uncached_asr & ASR_M) != ASR_MODE_USER) {
- *flags |= (1 << 6);
- }
-}
-
void uc32_translate_init(void);
void switch_mode(CPUUniCore32State *, int);
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
index f99feaa..2b47d13 100644
--- a/target-xtensa/cpu.c
+++ b/target-xtensa/cpu.c
@@ -40,6 +40,39 @@ static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.pc = value;
}
+static void xtensa_cpu_get_tb_cpu_state(const CPUState *cs, vaddr *pc,
+ vaddr *cs_base, int *flags)
+{
+ XtensaCPU *cpu = XTENSA_CPU(cs);
+ CPUXtensaState *env = &cpu->env;
+
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = 0;
+ *flags |= xtensa_get_ring(env);
+ if (env->sregs[PS] & PS_EXCM) {
+ *flags |= XTENSA_TBFLAG_EXCM;
+ }
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
+ (env->sregs[LITBASE] & 1)) {
+ *flags |= XTENSA_TBFLAG_LITBASE;
+ }
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
+ if (xtensa_get_cintlevel(env) < env->config->debug_level) {
+ *flags |= XTENSA_TBFLAG_DEBUG;
+ }
+ if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
+ *flags |= XTENSA_TBFLAG_ICOUNT;
+ }
+ }
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
+ *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
+ }
+ if (cs->singlestep_enabled && env->exception_taken) {
+ *flags |= XTENSA_TBFLAG_EXCEPTION;
+ }
+}
+
static int xtensa_cpu_mmu_index(const CPUState *cs)
{
XtensaCPU *cpu = XTENSA_CPU(cs);
@@ -151,6 +184,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = xtensa_cpu_dump_state;
cc->mmu_index = xtensa_cpu_mmu_index;
cc->set_pc = xtensa_cpu_set_pc;
+ cc->get_tb_cpu_state = xtensa_cpu_get_tb_cpu_state;
cc->gdb_read_register = xtensa_cpu_gdb_read_register;
cc->gdb_write_register = xtensa_cpu_gdb_write_register;
#ifndef CONFIG_USER_ONLY
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 4fdaf20..5d2a059 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -481,36 +481,6 @@ static inline xtensa_tlb_entry *xtensa_tlb_get_entry(CPUXtensaState *env,
#define XTENSA_TBFLAG_CPENABLE_SHIFT 6
#define XTENSA_TBFLAG_EXCEPTION 0x4000
-static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc,
- target_ulong *cs_base, int *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *flags = 0;
- *flags |= xtensa_get_ring(env);
- if (env->sregs[PS] & PS_EXCM) {
- *flags |= XTENSA_TBFLAG_EXCM;
- }
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
- (env->sregs[LITBASE] & 1)) {
- *flags |= XTENSA_TBFLAG_LITBASE;
- }
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
- if (xtensa_get_cintlevel(env) < env->config->debug_level) {
- *flags |= XTENSA_TBFLAG_DEBUG;
- }
- if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
- *flags |= XTENSA_TBFLAG_ICOUNT;
- }
- }
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
- *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
- }
- if (ENV_GET_CPU(env)->singlestep_enabled && env->exception_taken) {
- *flags |= XTENSA_TBFLAG_EXCEPTION;
- }
-}
-
#include "exec/cpu-all.h"
#include "exec/exec-all.h"
diff --git a/translate-all.c b/translate-all.c
index 2c923c6..6000d4a 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1011,11 +1011,12 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
PageDesc *p;
int n;
#ifdef TARGET_HAS_PRECISE_SMC
+ CPUClass *cc = NULL;
int current_tb_not_found = is_cpu_write_access;
TranslationBlock *current_tb = NULL;
int current_tb_modified = 0;
- target_ulong current_pc = 0;
- target_ulong current_cs_base = 0;
+ vaddr current_pc = 0;
+ vaddr current_cs_base = 0;
int current_flags = 0;
#endif /* TARGET_HAS_PRECISE_SMC */
@@ -1032,6 +1033,9 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
#if defined(TARGET_HAS_PRECISE_SMC) || !defined(CONFIG_USER_ONLY)
if (cpu != NULL) {
env = cpu->env_ptr;
+#ifdef TARGET_HAS_PRECISE_SMC
+ cc = CPU_GET_CLASS(cpu);
+#endif
}
#endif
@@ -1073,7 +1077,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
current_tb_modified = 1;
cpu_restore_state_from_tb(current_tb, env, env->mem_io_pc);
- cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base,
+ cc->get_tb_cpu_state(cpu, ¤t_pc, ¤t_cs_base,
¤t_flags);
}
#endif /* TARGET_HAS_PRECISE_SMC */
@@ -1157,10 +1161,11 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr,
#ifdef TARGET_HAS_PRECISE_SMC
TranslationBlock *current_tb = NULL;
CPUState *cpu = current_cpu;
+ CPUClass *cc = NULL;
CPUArchState *env = NULL;
int current_tb_modified = 0;
- target_ulong current_pc = 0;
- target_ulong current_cs_base = 0;
+ vaddr current_pc = 0;
+ vaddr current_cs_base = 0;
int current_flags = 0;
#endif
@@ -1176,6 +1181,7 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr,
}
if (cpu != NULL) {
env = cpu->env_ptr;
+ cc = CPU_GET_CLASS(cpu);
}
#endif
while (tb != NULL) {
@@ -1192,7 +1198,7 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr,
current_tb_modified = 1;
cpu_restore_state_from_tb(current_tb, env, pc);
- cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base,
+ cc->get_tb_cpu_state(cpu, ¤t_pc, ¤t_cs_base,
¤t_flags);
}
#endif /* TARGET_HAS_PRECISE_SMC */
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 03/41] cpu: Turn cpu_get_tb_cpu_state() into a CPUClass hook
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 03/41] cpu: Turn cpu_get_tb_cpu_state() " Andreas Färber
@ 2013-09-04 10:26 ` Paolo Bonzini
2013-09-04 11:02 ` Andreas Färber
0 siblings, 1 reply; 68+ messages in thread
From: Paolo Bonzini @ 2013-09-04 10:26 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Jia Liu, Anthony Green, qemu-devel, Alexander Graf,
Blue Swirl, Max Filippov, Michael Walle, PowerPC, Paul Brook,
Edgar E. Iglesias, Guan Xuetao, Aurelien Jarno, Richard Henderson
Il 04/09/2013 11:04, Andreas Färber ha scritto:
> static inline TranslationBlock *tb_find_fast(CPUArchState *env)
> {
> + CPUState *cpu = ENV_GET_CPU(env);
> + CPUClass *cc = CPU_GET_CLASS(cpu);
> TranslationBlock *tb;
> - target_ulong cs_base, pc;
> + vaddr cs_base, pc;
> int flags;
>
> /* we record a subset of the CPU state. It will
> always be the same before a given translated block
> is executed. */
> - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
> + cc->get_tb_cpu_state(cpu, &pc, &cs_base, &flags);
I'm afraid you cannot turn inline functions into indirect calls like
this in hot paths.
One alternative would be to hoist the function call to the beginning of
cpu_exec, and ensure that any place that modifies the result calls
cpu_exit. It may be a problem for SPARC's npc stuff, for which I have
no idea how it works.
Another is to change cpu-exec.c into a file that is #included by
target-*/helper.c or something like that. This way cpu-exec.c can still
use the inline functions.
Paolo
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 03/41] cpu: Turn cpu_get_tb_cpu_state() into a CPUClass hook
2013-09-04 10:26 ` Paolo Bonzini
@ 2013-09-04 11:02 ` Andreas Färber
2013-09-04 11:20 ` Paolo Bonzini
0 siblings, 1 reply; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 11:02 UTC (permalink / raw)
To: Paolo Bonzini
Cc: Peter Maydell, Peter Crosthwaite, Jia Liu, Anthony Green,
qemu-devel, Alexander Graf, Blue Swirl, Max Filippov,
Michael Walle, qemu-ppc, Edgar E. Iglesias, Guan Xuetao,
Aurelien Jarno, Richard Henderson
Am 04.09.2013 12:26, schrieb Paolo Bonzini:
> Il 04/09/2013 11:04, Andreas Färber ha scritto:
>> static inline TranslationBlock *tb_find_fast(CPUArchState *env)
>> {
>> + CPUState *cpu = ENV_GET_CPU(env);
>> + CPUClass *cc = CPU_GET_CLASS(cpu);
>> TranslationBlock *tb;
>> - target_ulong cs_base, pc;
>> + vaddr cs_base, pc;
>> int flags;
>>
>> /* we record a subset of the CPU state. It will
>> always be the same before a given translated block
>> is executed. */
>> - cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
>> + cc->get_tb_cpu_state(cpu, &pc, &cs_base, &flags);
>
> I'm afraid you cannot turn inline functions into indirect calls like
> this in hot paths.
>
> One alternative would be to hoist the function call to the beginning of
> cpu_exec, and ensure that any place that modifies the result calls
> cpu_exit. It may be a problem for SPARC's npc stuff, for which I have
> no idea how it works.
Sorry, you lost me here...
> Another is to change cpu-exec.c into a file that is #included by
> target-*/helper.c or something like that. This way cpu-exec.c can still
> use the inline functions.
I don't see how that would help with compiling multiple CPU types into
one executable. A common CPU struct type is needed to compile the core
CPU code once, which in turn requires dispatching for target-specific
bits, such as this one or previously gdbstub and TBD monitor.
Combining only targets with target_ulong of the same size and identical
endianness is a restriction we can accept, I think - examples include
32-bit ARM+SH4A, ARM+MicroBlaze, ARM+Hexagon, ARM+Epiphany.
For performance reasons I have been careful not to have an, e.g.,
cpu_get_tb_cpu_state() wrapper that calls CPU_GET_CLASS() each time.
Many of the "cpu" variables added are being cleaned up later in the
series by argument propagation. And in placement of variables requiring
CPU() cast I have been careful to place them depending on where they
are/will be actually used rather than always placing them at the top.
But if behavior depends on the CPU type, then it cannot be a global
function - cpu.h as-is is a problem and needs to be broken up.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 03/41] cpu: Turn cpu_get_tb_cpu_state() into a CPUClass hook
2013-09-04 11:02 ` Andreas Färber
@ 2013-09-04 11:20 ` Paolo Bonzini
0 siblings, 0 replies; 68+ messages in thread
From: Paolo Bonzini @ 2013-09-04 11:20 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Peter Crosthwaite, Jia Liu, Anthony Green,
Alexander Graf, qemu-devel, Blue Swirl, Max Filippov,
Michael Walle, qemu-ppc, Edgar E. Iglesias, Guan Xuetao,
Aurelien Jarno, Richard Henderson
Il 04/09/2013 13:02, Andreas Färber ha scritto:
> Am 04.09.2013 12:26, schrieb Paolo Bonzini:
>> Another is to change cpu-exec.c into a file that is #included by
>> target-*/helper.c or something like that. This way cpu-exec.c can still
>> use the inline functions.
>
> I don't see how that would help with compiling multiple CPU types into
> one executable.
>
> A common CPU struct type is needed to compile the core
> CPU code once, which in turn requires dispatching for target-specific
> bits, such as this one or previously gdbstub and TBD monitor.
cpu-exec.c is all but common to the various targets. You could make
cpu_exec() itself a CPU method. Then calls to cpu_get_tb_cpu_state()
from cpu_exec() can remain inlined instead of being virtual calls.
Not all files have to be compiled "per target", probably only cputlb.c
and cpu-exec.c.
Paolo
> Combining only targets with target_ulong of the same size and identical
> endianness is a restriction we can accept, I think - examples include
> 32-bit ARM+SH4A, ARM+MicroBlaze, ARM+Hexagon, ARM+Epiphany.
>
> For performance reasons I have been careful not to have an, e.g.,
> cpu_get_tb_cpu_state() wrapper that calls CPU_GET_CLASS() each time.
> Many of the "cpu" variables added are being cleaned up later in the
> series by argument propagation. And in placement of variables requiring
> CPU() cast I have been careful to place them depending on where they
> are/will be actually used rather than always placing them at the top.
> But if behavior depends on the CPU type, then it cannot be a global
> function - cpu.h as-is is a problem and needs to be broken up.
>
> Andreas
>
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [RFC qom-cpu 04/41] cpu: Turn cpu_handle_mmu_fault() into a CPUClass hook
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (2 preceding siblings ...)
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 03/41] cpu: Turn cpu_get_tb_cpu_state() " Andreas Färber
@ 2013-09-04 9:04 ` Andreas Färber
2013-09-04 12:46 ` Jia Liu
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 05/41] cpu: Move mem_io_{pc, vaddr} fields from CPU_COMMON to CPUState Andreas Färber
` (39 subsequent siblings)
43 siblings, 1 reply; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:04 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Anthony Green, Alexander Graf, Blue Swirl,
Michael Walle, open list:PowerPC, Paul Brook, Edgar E. Iglesias,
Guan Xuetao, Andreas Färber, Aurelien Jarno,
Richard Henderson
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
include/qom/cpu.h | 3 +++
target-alpha/cpu.c | 4 +++-
target-alpha/cpu.h | 5 ++---
target-alpha/helper.c | 12 ++++++++----
target-alpha/mem_helper.c | 3 ++-
target-arm/cpu.c | 4 +++-
target-arm/cpu.h | 5 ++---
target-arm/helper.c | 13 +++++++++----
target-arm/op_helper.c | 3 ++-
target-cris/cpu.c | 4 +++-
target-cris/cpu.h | 3 +--
target-cris/helper.c | 24 +++++++++++++-----------
target-cris/op_helper.c | 3 ++-
target-i386/cpu.c | 4 +++-
target-i386/cpu.h | 3 +--
target-i386/helper.c | 19 ++++++++++++-------
target-i386/mem_helper.c | 3 ++-
target-lm32/cpu.c | 4 +++-
target-lm32/cpu.h | 3 +--
target-lm32/helper.c | 4 +++-
target-lm32/op_helper.c | 3 ++-
target-m68k/cpu.c | 4 +++-
target-m68k/cpu.h | 3 +--
target-m68k/helper.c | 17 ++++++++++-------
target-m68k/op_helper.c | 3 ++-
target-microblaze/cpu.c | 4 +++-
target-microblaze/cpu.h | 3 +--
target-microblaze/helper.c | 14 ++++++++------
target-microblaze/op_helper.c | 3 ++-
target-mips/cpu.c | 4 +++-
target-mips/cpu.h | 5 ++---
target-mips/helper.c | 15 +++++++++------
target-mips/op_helper.c | 3 ++-
target-moxie/cpu.c | 4 +++-
target-moxie/cpu.h | 2 +-
target-moxie/helper.c | 19 +++++++++++--------
target-openrisc/cpu.c | 4 +++-
target-openrisc/cpu.h | 4 +---
target-openrisc/mmu.c | 14 +++++++-------
target-openrisc/mmu_helper.c | 3 ++-
target-ppc/cpu.h | 4 ++--
target-ppc/translate_init.c | 4 +++-
target-ppc/user_only_helper.c | 6 ++++--
target-s390x/cpu.c | 4 +++-
target-s390x/cpu.h | 5 ++---
target-s390x/helper.c | 20 ++++++++++++--------
target-s390x/mem_helper.c | 3 ++-
target-sh4/cpu.c | 4 +++-
target-sh4/cpu.h | 5 ++---
target-sh4/helper.c | 13 +++++++++----
target-sh4/op_helper.c | 3 ++-
target-sparc/cpu.c | 4 +++-
target-sparc/cpu.h | 3 +--
target-sparc/ldst_helper.c | 3 ++-
target-sparc/mmu_helper.c | 18 ++++++++++++------
target-unicore32/cpu.c | 4 +++-
target-unicore32/cpu.h | 5 ++---
target-unicore32/helper.c | 5 ++++-
target-unicore32/op_helper.c | 3 ++-
target-unicore32/softmmu.c | 6 ++++--
user-exec.c | 9 +++++++--
61 files changed, 238 insertions(+), 150 deletions(-)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 3d6b66e..4d974f3 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -84,6 +84,7 @@ struct TranslationBlock;
* #TranslationBlock.
* @synchronize_from_tb: Callback for synchronizing state from a TCG
* #TranslationBlock.
+ * @handle_mmu_fault: Callback for handling an MMU fault.
* @get_phys_page_debug: Callback for obtaining a physical address.
* @gdb_read_register: Callback for letting GDB read a register.
* @gdb_write_register: Callback for letting GDB write a register.
@@ -120,6 +121,8 @@ typedef struct CPUClass {
void (*get_tb_cpu_state)(const CPUState *cpu, vaddr *pc, vaddr *cs_base,
int *flags);
void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
+ int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw,
+ int mmu_index);
hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index bb1eddc..e880983 100644
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -330,7 +330,9 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
cc->get_tb_cpu_state = alpha_cpu_get_tb_cpu_state;
cc->gdb_read_register = alpha_cpu_gdb_read_register;
cc->gdb_write_register = alpha_cpu_gdb_write_register;
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ cc->handle_mmu_fault = alpha_cpu_handle_mmu_fault;
+#else
cc->do_unassigned_access = alpha_cpu_unassigned_access;
cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_alpha_cpu;
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index a4abce8..dd117d9 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -435,9 +435,8 @@ int cpu_alpha_exec(CPUAlphaState *s);
is returned if the signal was handled by the virtual CPU. */
int cpu_alpha_signal_handler(int host_signum, void *pinfo,
void *puc);
-int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, uint64_t address, int rw,
- int mmu_idx);
-#define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
+int alpha_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
+ int mmu_idx);
void do_restore_state(CPUAlphaState *, uintptr_t retaddr);
void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);
diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index fc61bb0..ef2dc25 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -168,11 +168,13 @@ void helper_store_fpcr(CPUAlphaState *env, uint64_t val)
}
#if defined(CONFIG_USER_ONLY)
-int cpu_alpha_handle_mmu_fault(CPUAlphaState *env, target_ulong address,
+int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
int rw, int mmu_idx)
{
- env->exception_index = EXCP_MMFAULT;
- env->trap_arg0 = address;
+ AlphaCPU *cpu = ALPHA_CPU(cs);
+
+ cpu->env.exception_index = EXCP_MMFAULT;
+ cpu->env.trap_arg0 = address;
return 1;
}
#else
@@ -325,9 +327,11 @@ hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
return (fail >= 0 ? -1 : phys);
}
-int cpu_alpha_handle_mmu_fault(CPUAlphaState *env, target_ulong addr, int rw,
+int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int rw,
int mmu_idx)
{
+ AlphaCPU *cpu = ALPHA_CPU(cs);
+ CPUAlphaState *env = &cpu->env;
target_ulong phys;
int prot, fail;
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index 7160a1c..d140688 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -145,9 +145,10 @@ void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr,
void tlb_fill(CPUAlphaState *env, target_ulong addr, int is_write,
int mmu_idx, uintptr_t retaddr)
{
+ AlphaCPU *cpu = alpha_env_get_cpu(env);
int ret;
- ret = cpu_alpha_handle_mmu_fault(env, addr, is_write, mmu_idx);
+ ret = alpha_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
if (unlikely(ret != 0)) {
if (retaddr) {
cpu_restore_state(env, retaddr);
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 53bf337..4c6fe17 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -938,7 +938,9 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
cc->get_tb_cpu_state = arm_cpu_get_tb_cpu_state;
cc->gdb_read_register = arm_cpu_gdb_read_register;
cc->gdb_write_register = arm_cpu_gdb_write_register;
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
+#else
cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_arm_cpu;
#endif
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 161b9fd..ce98dda 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -266,9 +266,8 @@ uint32_t do_arm_semihosting(CPUARMState *env);
is returned if the signal was handled by the virtual CPU. */
int cpu_arm_signal_handler(int host_signum, void *pinfo,
void *puc);
-int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
- int mmu_idx);
-#define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
+int arm_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
+ int mmu_idx);
#define CPSR_M (0x1f)
#define CPSR_T (1 << 5)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e51ef20..9d0d8b4 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2078,9 +2078,12 @@ void arm_cpu_do_interrupt(CPUState *cs)
env->exception_index = -1;
}
-int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
- int mmu_idx)
+int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
+ int mmu_idx)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
if (rw == 2) {
env->exception_index = EXCP_PREFETCH_ABORT;
env->cp15.c6_insn = address;
@@ -3026,9 +3029,11 @@ static inline int get_phys_addr(CPUARMState *env, uint32_t address,
}
}
-int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
- int access_type, int mmu_idx)
+int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
+ int access_type, int mmu_idx)
{
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
hwaddr phys_addr;
target_ulong page_size;
int prot;
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index a918e5b..13d34fb 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -74,9 +74,10 @@ uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
+ ARMCPU *cpu = arm_env_get_cpu(env);
int ret;
- ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx);
+ ret = arm_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index 39a25ed..504d6a4 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -290,7 +290,9 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
cc->get_tb_cpu_state = cris_cpu_get_tb_cpu_state;
cc->gdb_read_register = cris_cpu_gdb_read_register;
cc->gdb_write_register = cris_cpu_gdb_write_register;
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ cc->handle_mmu_fault = cris_cpu_handle_mmu_fault;
+#else
cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
#endif
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 9f1fa38..9e9cb8c 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -239,9 +239,8 @@ static inline CPUCRISState *cpu_init(const char *cpu_model)
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
-int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
+int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
int mmu_idx);
-#define cpu_handle_mmu_fault cpu_cris_handle_mmu_fault
/* Support function regs. */
#define SFR_RW_GC_CFG 0][0
diff --git a/target-cris/helper.c b/target-cris/helper.c
index d274b38..72dc839 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -50,14 +50,14 @@ void crisv10_cpu_do_interrupt(CPUState *cs)
cris_cpu_do_interrupt(cs);
}
-int cpu_cris_handle_mmu_fault(CPUCRISState * env, target_ulong address, int rw,
+int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int mmu_idx)
{
- CRISCPU *cpu = cris_env_get_cpu(env);
+ CRISCPU *cpu = CRIS_CPU(cs);
- env->exception_index = 0xaa;
- env->pregs[PR_EDA] = address;
- cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
+ cpu->env.exception_index = 0xaa;
+ cpu->env.pregs[PR_EDA] = address;
+ cpu_dump_state(cs, stderr, fprintf, 0);
return 1;
}
@@ -73,23 +73,25 @@ static void cris_shift_ccs(CPUCRISState *env)
env->pregs[PR_CCS] = ccs;
}
-int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
+int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int mmu_idx)
{
- D(CPUState *cpu = CPU(cris_env_get_cpu(env)));
+ CRISCPU *cpu = CRIS_CPU(cs);
+ CPUCRISState *env = &cpu->env;
struct cris_mmu_result res;
int prot, miss;
int r = -1;
target_ulong phy;
- D(printf("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
+ D(printf("%s addr=%" VADDR_PRIx " pc=%x rw=%x\n",
+ __func__, address, env->pc, rw));
miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
rw, mmu_idx, 0);
if (miss) {
if (env->exception_index == EXCP_BUSFAULT) {
cpu_abort(env,
"CRIS: Illegal recursive bus fault."
- "addr=%x rw=%d\n",
+ "addr=%" VADDR_PRIx " rw=%d\n",
address, rw);
}
@@ -109,8 +111,8 @@ int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
r = 0;
}
if (r > 0) {
- D_LOG("%s returns %d irqreq=%x addr=%x phy=%x vec=%x pc=%x\n",
- __func__, r, cpu->interrupt_request, address, res.phy,
+ D_LOG("%s returns %d irqreq=%x addr=%" VADDR_PRIx " phy=%x vec=%x"
+ " pc=%x\n", __func__, r, cs->interrupt_request, address, res.phy,
res.bf_vec, env->pc);
}
return r;
diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
index b580513..4a6215d 100644
--- a/target-cris/op_helper.c
+++ b/target-cris/op_helper.c
@@ -57,11 +57,12 @@
void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
+ CRISCPU *cpu = cris_env_get_cpu(env);
int ret;
D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__,
env->pc, env->pregs[PR_EDA], (void *)retaddr);
- ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx);
+ ret = cris_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 995d5ff..3ed5a11 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2743,7 +2743,9 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
cc->gdb_write_register = x86_cpu_gdb_write_register;
cc->get_arch_id = x86_cpu_get_arch_id;
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
+#else
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
cc->write_elf64_note = x86_cpu_write_elf64_note;
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 999a46c..3620699 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1042,9 +1042,8 @@ void host_cpuid(uint32_t function, uint32_t count,
uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
/* helper.c */
-int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
+int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr,
int is_write, int mmu_idx);
-#define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index)
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 7c58e27..b25dafc 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -485,9 +485,12 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
#if defined(CONFIG_USER_ONLY)
-int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
+int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
int is_write, int mmu_idx)
{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
/* user mode only emulation */
is_write &= 1;
env->cr[2] = addr;
@@ -508,13 +511,15 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
# endif
/* return value:
- -1 = cannot handle fault
- 0 = nothing more to do
- 1 = generate PF fault
-*/
-int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
+ * -1 = cannot handle fault
+ * 0 = nothing more to do
+ * 1 = generate PF fault
+ */
+int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
int is_write1, int mmu_idx)
{
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
uint64_t ptep, pte;
target_ulong pde_addr, pte_addr;
int error_code, is_dirty, prot, page_size, is_write, is_user;
@@ -524,7 +529,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
is_user = mmu_idx == MMU_USER_IDX;
#if defined(DEBUG_MMU)
- printf("MMU fault: addr=" TARGET_FMT_lx " w=%d u=%d eip=" TARGET_FMT_lx "\n",
+ printf("MMU fault: addr=%" VADDR_PRIx " w=%d u=%d eip=" TARGET_FMT_lx "\n",
addr, is_write1, is_user, env->eip);
#endif
is_write = is_write1 & 1;
diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c
index 319a219..5b25ccd 100644
--- a/target-i386/mem_helper.c
+++ b/target-i386/mem_helper.c
@@ -135,9 +135,10 @@ void helper_boundl(CPUX86State *env, target_ulong a0, int v)
void tlb_fill(CPUX86State *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
+ X86CPU *cpu = x86_env_get_cpu(env);
int ret;
- ret = cpu_x86_handle_mmu_fault(env, addr, is_write, mmu_idx);
+ ret = x86_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
if (ret) {
if (retaddr) {
/* now we have a real cpu fault */
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
index 7976d39..607e332 100644
--- a/target-lm32/cpu.c
+++ b/target-lm32/cpu.c
@@ -108,7 +108,9 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
cc->get_tb_cpu_state = lm32_cpu_get_tb_cpu_state;
cc->gdb_read_register = lm32_cpu_gdb_read_register;
cc->gdb_write_register = lm32_cpu_gdb_write_register;
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ cc->handle_mmu_fault = lm32_cpu_handle_mmu_fault;
+#else
cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_lm32_cpu;
#endif
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index a34f047..a94fd79 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -207,9 +207,8 @@ static inline CPULM32State *cpu_init(const char *cpu_model)
#define cpu_gen_code cpu_lm32_gen_code
#define cpu_signal_handler cpu_lm32_signal_handler
-int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
+int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
int mmu_idx);
-#define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault
#include "exec/cpu-all.h"
#include "exec/exec-all.h"
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index 15bc615..55a3de6 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -20,9 +20,11 @@
#include "cpu.h"
#include "qemu/host-utils.h"
-int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
+int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int mmu_idx)
{
+ LM32CPU *cpu = LM32_CPU(cs);
+ CPULM32State *env = &cpu->env;
int prot;
address &= TARGET_PAGE_MASK;
diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
index 8f5ef55..215215e 100644
--- a/target-lm32/op_helper.c
+++ b/target-lm32/op_helper.c
@@ -80,9 +80,10 @@ uint32_t HELPER(rcsr_jrx)(CPULM32State *env)
void tlb_fill(CPULM32State *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
+ LM32CPU *cpu = lm32_env_get_cpu(env);
int ret;
- ret = cpu_lm32_handle_mmu_fault(env, addr, is_write, mmu_idx);
+ ret = lm32_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index 6dbfe89..e46b647 100644
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -222,7 +222,9 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
cc->get_tb_cpu_state = m68k_cpu_get_tb_cpu_state;
cc->gdb_read_register = m68k_cpu_gdb_read_register;
cc->gdb_write_register = m68k_cpu_gdb_write_register;
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ cc->handle_mmu_fault = m68k_cpu_handle_mmu_fault;
+#else
cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
#endif
dc->vmsd = &vmstate_m68k_cpu;
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 5c7992e..b8ad269 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -233,9 +233,8 @@ static inline CPUM68KState *cpu_init(const char *cpu_model)
#define MMU_MODE1_SUFFIX _user
#define MMU_USER_IDX 1
-int cpu_m68k_handle_mmu_fault(CPUM68KState *env, target_ulong address, int rw,
+int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
int mmu_idx);
-#define cpu_handle_mmu_fault cpu_m68k_handle_mmu_fault
#include "exec/cpu-all.h"
#include "exec/exec-all.h"
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 00a7a08..25a0570 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -278,11 +278,13 @@ void m68k_switch_sp(CPUM68KState *env)
#if defined(CONFIG_USER_ONLY)
-int cpu_m68k_handle_mmu_fault (CPUM68KState *env, target_ulong address, int rw,
- int mmu_idx)
+int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
+ int mmu_idx)
{
- env->exception_index = EXCP_ACCESS;
- env->mmu.ar = address;
+ M68kCPU *cpu = M68K_CPU(cs);
+
+ cpu->env.exception_index = EXCP_ACCESS;
+ cpu->env.mmu.ar = address;
return 1;
}
@@ -296,14 +298,15 @@ hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
return addr;
}
-int cpu_m68k_handle_mmu_fault (CPUM68KState *env, target_ulong address, int rw,
- int mmu_idx)
+int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
+ int mmu_idx)
{
+ M68kCPU *cpu = M68K_CPU(cs);
int prot;
address &= TARGET_PAGE_MASK;
prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
- tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(&cpu->env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
}
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
index 30f7d8b..bc10f38 100644
--- a/target-m68k/op_helper.c
+++ b/target-m68k/op_helper.c
@@ -59,9 +59,10 @@ extern int semihosting_enabled;
void tlb_fill(CPUM68KState *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
+ M68kCPU *cpu = m68k_env_get_cpu(env);
int ret;
- ret = cpu_m68k_handle_mmu_fault(env, addr, is_write, mmu_idx);
+ ret = m68k_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index fbcdcc4..8b248f4 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -178,7 +178,9 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
cc->get_tb_cpu_state = mb_cpu_get_tb_cpu_state;
cc->gdb_read_register = mb_cpu_gdb_read_register;
cc->gdb_write_register = mb_cpu_gdb_write_register;
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ cc->handle_mmu_fault = mb_cpu_handle_mmu_fault;
+#else
cc->do_unassigned_access = mb_cpu_unassigned_access;
cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
#endif
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index d80f812..1177e51 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -316,9 +316,8 @@ static inline CPUMBState *cpu_init(const char *cpu_model)
#define MMU_USER_IDX 2
/* See NB_MMU_MODES further up the file. */
-int cpu_mb_handle_mmu_fault(CPUMBState *env, target_ulong address, int rw,
+int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
int mmu_idx);
-#define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
static inline int cpu_interrupts_enabled(CPUMBState *env)
{
diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
index 4fa9ce9..d03f369 100644
--- a/target-microblaze/helper.c
+++ b/target-microblaze/helper.c
@@ -36,21 +36,23 @@ void mb_cpu_do_interrupt(CPUState *cs)
env->regs[14] = env->sregs[SR_PC];
}
-int cpu_mb_handle_mmu_fault(CPUMBState * env, target_ulong address, int rw,
+int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int mmu_idx)
{
- MicroBlazeCPU *cpu = mb_env_get_cpu(env);
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
- env->exception_index = 0xaa;
- cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
+ cpu->env.exception_index = 0xaa;
+ cpu_dump_state(cs, stderr, fprintf, 0);
return 1;
}
#else /* !CONFIG_USER_ONLY */
-int cpu_mb_handle_mmu_fault (CPUMBState *env, target_ulong address, int rw,
- int mmu_idx)
+int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
+ int mmu_idx)
{
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+ CPUMBState *env = &cpu->env;
unsigned int hit;
unsigned int mmu_available;
int r = 1;
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index 14baa84..b70b2ea 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -44,9 +44,10 @@
void tlb_fill(CPUMBState *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
+ MicroBlazeCPU *cpu = mb_env_get_cpu(env);
int ret;
- ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx);
+ ret = mb_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index 4aa06bb..2fd5591 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -153,7 +153,9 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
cc->gdb_read_register = mips_cpu_gdb_read_register;
cc->gdb_write_register = mips_cpu_gdb_write_register;
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ cc->handle_mmu_fault = mips_cpu_handle_mmu_fault;
+#else
cc->do_unassigned_access = mips_cpu_unassigned_access;
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
#endif
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 91217ed..b71a711 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -649,9 +649,8 @@ void cpu_mips_stop_count(CPUMIPSState *env);
void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
/* helper.c */
-int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw,
- int mmu_idx);
-#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
+int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
+ int mmu_idx);
#if !defined(CONFIG_USER_ONLY)
void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 33e0e88..d8e9166 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -268,9 +268,11 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
}
#endif
-int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw,
- int mmu_idx)
+int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
+ int mmu_idx)
{
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
#if !defined(CONFIG_USER_ONLY)
hwaddr physical;
int prot;
@@ -279,9 +281,9 @@ int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw,
int ret = 0;
#if 0
- log_cpu_state(CPU(mips_env_get_cpu(env)), 0);
+ log_cpu_state(cs, 0);
#endif
- qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d\n",
+ qemu_log("%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, env->active_tc.PC, address, rw, mmu_idx);
rw &= 1;
@@ -293,8 +295,9 @@ int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw,
access_type = ACCESS_INT;
ret = get_physical_address(env, &physical, &prot,
address, rw, access_type);
- qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx " prot %d\n",
- __func__, address, ret, physical, prot);
+ qemu_log("%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
+ " prot %d\n",
+ __func__, address, ret, physical, prot);
if (ret == TLBRET_MATCH) {
tlb_set_page(env, address & TARGET_PAGE_MASK,
physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 8e3a6d7..34ac4c6 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2134,9 +2134,10 @@ static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
+ MIPSCPU *cpu = mips_env_get_cpu(env);
int ret;
- ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx);
+ ret = mips_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
if (ret) {
do_raise_exception_err(env, env->exception_index,
env->error_code, retaddr);
diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
index 9983c99..e07a4df 100644
--- a/target-moxie/cpu.c
+++ b/target-moxie/cpu.c
@@ -119,7 +119,9 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
cc->dump_state = moxie_cpu_dump_state;
cc->set_pc = moxie_cpu_set_pc;
cc->get_tb_cpu_state = moxie_cpu_get_tb_cpu_state;
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ cc->handle_mmu_fault = moxie_cpu_handle_mmu_fault;
+#else
cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_moxie_cpu;
#endif
diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h
index 7e33efe..fb2a97e 100644
--- a/target-moxie/cpu.h
+++ b/target-moxie/cpu.h
@@ -139,7 +139,7 @@ static inline CPUMoxieState *cpu_init(const char *cpu_model)
#include "exec/cpu-all.h"
#include "exec/exec-all.h"
-int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address,
+int moxie_cpu_handle_mmu_fault(CPUState *cpu, vaddr address,
int rw, int mmu_idx);
#endif /* _CPU_MOXIE_H */
diff --git a/target-moxie/helper.c b/target-moxie/helper.c
index 7859102..8160475 100644
--- a/target-moxie/helper.c
+++ b/target-moxie/helper.c
@@ -49,9 +49,10 @@
void tlb_fill(CPUMoxieState *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
+ MoxieCPU *cpu = moxie_env_get_cpu(env);
int ret;
- ret = cpu_moxie_handle_mmu_fault(env, addr, is_write, mmu_idx);
+ ret = moxie_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
cpu_restore_state(env, retaddr);
@@ -103,27 +104,29 @@ void helper_debug(CPUMoxieState *env)
#if defined(CONFIG_USER_ONLY)
-void moxie_cpu_do_interrupt(CPUState *env)
+void moxie_cpu_do_interrupt(CPUState *cs)
{
env->exception_index = -1;
}
-int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address,
+int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
int rw, int mmu_idx)
{
- MoxieCPU *cpu = moxie_env_get_cpu(env);
+ MoxieCPU *cpu = MOXIE_CPU(cs);
- env->exception_index = 0xaa;
- env->debug1 = address;
- cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
+ cpu->env.exception_index = 0xaa;
+ cpu->env.debug1 = address;
+ cpu_dump_state(cs, stderr, fprintf, 0);
return 1;
}
#else /* !CONFIG_USER_ONLY */
-int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address,
+int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
int rw, int mmu_idx)
{
+ MoxieCPU *cpu = MOXIE_CPU(cs);
+ CPUMoxieState *env = &cpu->env;
MoxieMMUResult res;
int prot, miss;
target_ulong phy;
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 107e5f9..ee1591d 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -188,7 +188,9 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
cc->get_tb_cpu_state = openrisc_cpu_get_tb_cpu_state;
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ cc->handle_mmu_fault = openrisc_cpu_handle_mmu_fault;
+#else
cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
dc->vmsd = &vmstate_openrisc_cpu;
#endif
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index a41c271..8745072 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -353,15 +353,13 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
void openrisc_translate_init(void);
-int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
- target_ulong address,
+int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address,
int rw, int mmu_idx);
int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc);
#define cpu_list cpu_openrisc_list
#define cpu_exec cpu_openrisc_exec
#define cpu_gen_code cpu_openrisc_gen_code
-#define cpu_handle_mmu_fault cpu_openrisc_handle_mmu_fault
#define cpu_signal_handler cpu_openrisc_signal_handler
#ifndef CONFIG_USER_ONLY
diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c
index 57f5616..0f13c5d 100644
--- a/target-openrisc/mmu.c
+++ b/target-openrisc/mmu.c
@@ -181,19 +181,19 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu,
}
#ifndef CONFIG_USER_ONLY
-int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
- target_ulong address, int rw, int mmu_idx)
+int openrisc_cpu_handle_mmu_fault(CPUState *cs,
+ vaddr address, int rw, int mmu_idx)
{
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
int ret = 0;
hwaddr physical = 0;
int prot = 0;
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
ret = cpu_openrisc_get_phys_addr(cpu, &physical, &prot,
address, rw);
if (ret == TLBRET_MATCH) {
- tlb_set_page(env, address & TARGET_PAGE_MASK,
+ tlb_set_page(&cpu->env, address & TARGET_PAGE_MASK,
physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
mmu_idx, TARGET_PAGE_SIZE);
ret = 0;
@@ -205,11 +205,11 @@ int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
return ret;
}
#else
-int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
- target_ulong address, int rw, int mmu_idx)
+int openrisc_cpu_handle_mmu_fault(CPUState *cs,
+ vaddr address, int rw, int mmu_idx)
{
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
int ret = 0;
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret);
ret = 1;
diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c
index e46b092..b023a5f 100644
--- a/target-openrisc/mmu_helper.c
+++ b/target-openrisc/mmu_helper.c
@@ -39,9 +39,10 @@
void tlb_fill(CPUOpenRISCState *env, target_ulong addr, int is_write,
int mmu_idx, uintptr_t retaddr)
{
+ OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
int ret;
- ret = cpu_openrisc_handle_mmu_fault(env, addr, is_write, mmu_idx);
+ ret = openrisc_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
if (ret) {
if (retaddr) {
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 2ebf0a1..3b03ae6 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1098,8 +1098,8 @@ int cpu_ppc_signal_handler (int host_signum, void *pinfo,
void *puc);
void ppc_hw_interrupt (CPUPPCState *env);
#if defined(CONFIG_USER_ONLY)
-int cpu_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
- int mmu_idx);
+int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
+ int mmu_idx);
#endif
#if !defined(CONFIG_USER_ONLY)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 338d8fe..8b6fbb5 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8595,7 +8595,9 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
cc->get_tb_cpu_state = ppc_cpu_get_tb_cpu_state;
cc->gdb_read_register = ppc_cpu_gdb_read_register;
cc->gdb_write_register = ppc_cpu_gdb_write_register;
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault;
+#else
cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
cc->vmsd = &vmstate_ppc_cpu;
#endif
diff --git a/target-ppc/user_only_helper.c b/target-ppc/user_only_helper.c
index 56e686e..a7c99e0 100644
--- a/target-ppc/user_only_helper.c
+++ b/target-ppc/user_only_helper.c
@@ -20,9 +20,11 @@
#include "cpu.h"
-int cpu_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
- int mmu_idx)
+int ppc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
+ int mmu_idx)
{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ CPUPPCState *env = &cpu->env;
int exception, error_code;
if (rw == 2) {
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index a4a5370..ad0d5bc 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -257,7 +257,9 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
cc->get_tb_cpu_state = s390_cpu_get_tb_cpu_state;
cc->gdb_read_register = s390_cpu_gdb_read_register;
cc->gdb_write_register = s390_cpu_gdb_write_register;
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ cc->handle_mmu_fault = s390_cpu_handle_mmu_fault;
+#else
cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
cc->write_elf64_note = s390_cpu_write_elf64_note;
cc->write_elf64_qemunote = s390_cpu_write_elf64_qemunote;
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index cad092b..a09e4f9 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -308,9 +308,8 @@ int cpu_s390x_exec(CPUS390XState *s);
is returned if the signal was handled by the virtual CPU. */
int cpu_s390x_signal_handler(int host_signum, void *pinfo,
void *puc);
-int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
- int mmu_idx);
-#define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault
+int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
+ int mmu_idx);
#include "ioinst.h"
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index 61abfd7..361d713 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -94,14 +94,16 @@ void s390_cpu_do_interrupt(CPUState *cs)
env->exception_index = -1;
}
-int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong address,
- int rw, int mmu_idx)
+int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
+ int rw, int mmu_idx)
{
- env->exception_index = EXCP_PGM;
- env->int_pgm_code = PGM_ADDRESSING;
+ S390CPU *cpu = S390_CPU(cs);
+
+ cpu->env.exception_index = EXCP_PGM;
+ cpu->env.int_pgm_code = PGM_ADDRESSING;
/* On real machines this value is dropped into LowMem. Since this
is userland, simply put this someplace that cpu_loop can find it. */
- env->__excp_addr = address;
+ cpu->env.__excp_addr = address;
return 1;
}
@@ -377,14 +379,16 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
return r;
}
-int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong orig_vaddr,
- int rw, int mmu_idx)
+int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr,
+ int rw, int mmu_idx)
{
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
uint64_t asc = env->psw.mask & PSW_MASK_ASC;
target_ulong vaddr, raddr;
int prot;
- DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d\n",
+ DPRINTF("%s: address 0x%" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, orig_vaddr, rw, mmu_idx);
orig_vaddr &= TARGET_PAGE_MASK;
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index 1422ae9..747ba46 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -47,9 +47,10 @@
void tlb_fill(CPUS390XState *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
+ S390CPU *cpu = s390_env_get_cpu(env);
int ret;
- ret = cpu_s390x_handle_mmu_fault(env, addr, is_write, mmu_idx);
+ ret = s390_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
if (unlikely(ret != 0)) {
if (likely(retaddr)) {
/* now we have a real cpu fault */
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index 647a527..7f98f80 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -320,7 +320,9 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
cc->gdb_read_register = superh_cpu_gdb_read_register;
cc->gdb_write_register = superh_cpu_gdb_write_register;
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ cc->handle_mmu_fault = superh_cpu_handle_mmu_fault;
+#else
cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
#endif
dc->vmsd = &vmstate_sh_cpu;
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 42ecdd7..8abd0cc 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -193,9 +193,8 @@ SuperHCPU *cpu_sh4_init(const char *cpu_model);
int cpu_sh4_exec(CPUSH4State * s);
int cpu_sh4_signal_handler(int host_signum, void *pinfo,
void *puc);
-int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
- int mmu_idx);
-#define cpu_handle_mmu_fault cpu_sh4_handle_mmu_fault
+int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
+ int mmu_idx);
void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf);
#if !defined(CONFIG_USER_ONLY)
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 9ac2825..3f8f1fa 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -39,9 +39,12 @@ void superh_cpu_do_interrupt(CPUState *cs)
env->exception_index = -1;
}
-int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
- int mmu_idx)
+int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
+ int mmu_idx)
{
+ SuperHCPU *cpu = SUPERH_CPU(cs);
+ CPUSH4State *env = &cpu->env;
+
env->tea = address;
env->exception_index = -1;
switch (rw) {
@@ -447,9 +450,11 @@ static int get_physical_address(CPUSH4State * env, target_ulong * physical,
return get_mmu_address(env, physical, prot, address, rw, access_type);
}
-int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
- int mmu_idx)
+int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
+ int mmu_idx)
{
+ SuperHCPU *cpu = SUPERH_CPU(cs);
+ CPUSH4State *env = &cpu->env;
target_ulong physical;
int prot, ret, access_type;
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index e955e81..35f9067 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -41,9 +41,10 @@
void tlb_fill(CPUSH4State *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
+ SuperHCPU *cpu = sh_env_get_cpu(env);
int ret;
- ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx);
+ ret = superh_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
if (ret) {
/* now we have a real cpu fault */
if (retaddr) {
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index 49a4469..c8d8c55 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -857,7 +857,9 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb;
cc->gdb_read_register = sparc_cpu_gdb_read_register;
cc->gdb_write_register = sparc_cpu_gdb_write_register;
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ cc->handle_mmu_fault = sparc_cpu_handle_mmu_fault;
+#else
cc->do_unassigned_access = sparc_cpu_unassigned_access;
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
#endif
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index f078851..cfa1e0d 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -519,9 +519,8 @@ SPARCCPU *cpu_sparc_init(const char *cpu_model);
void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf);
/* mmu_helper.c */
-int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
+int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
int mmu_idx);
-#define cpu_handle_mmu_fault cpu_sparc_handle_mmu_fault
target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env);
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 2936b58..2f55af9 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -2432,9 +2432,10 @@ static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env,
void tlb_fill(CPUSPARCState *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
+ SPARCCPU *cpu = sparc_env_get_cpu(env);
int ret;
- ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx);
+ ret = sparc_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
if (ret) {
if (retaddr) {
cpu_restore_state(env, retaddr);
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index 9eb096e..0d88326 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -25,13 +25,15 @@
#if defined(CONFIG_USER_ONLY)
-int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
+int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int mmu_idx)
{
+ SPARCCPU *cpu = SPARC_CPU(cs);
+
if (rw & 2) {
- env1->exception_index = TT_TFAULT;
+ cpu->env.exception_index = TT_TFAULT;
} else {
- env1->exception_index = TT_DFAULT;
+ cpu->env.exception_index = TT_DFAULT;
}
return 1;
}
@@ -197,9 +199,11 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
}
/* Perform address translation */
-int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw,
+int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int mmu_idx)
{
+ SPARCCPU *cpu = SPARC_CPU(cs);
+ CPUSPARCState *env = &cpu->env;
hwaddr paddr;
target_ulong vaddr;
target_ulong page_size;
@@ -211,7 +215,7 @@ int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw,
vaddr = address;
if (error_code == 0) {
#ifdef DEBUG_MMU
- printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
+ printf("Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr "
TARGET_FMT_lx "\n", address, paddr, vaddr);
#endif
tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
@@ -703,9 +707,11 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
}
/* Perform address translation */
-int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw,
+int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int mmu_idx)
{
+ SPARCCPU *cpu = SPARC_CPU(cs);
+ CPUSPARCState *env = &cpu->env;
target_ulong vaddr;
hwaddr paddr;
target_ulong page_size;
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index e5fddcf..dcf3b16 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -170,7 +170,9 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
cc->mmu_index = uc32_cpu_mmu_index;
cc->set_pc = uc32_cpu_set_pc;
cc->get_tb_cpu_state = uc32_cpu_get_tb_cpu_state;
-#ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_USER_ONLY
+ cc->handle_mmu_fault = uc32_cpu_handle_mmu_fault;
+#else
cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
#endif
dc->vmsd = &vmstate_uc32_cpu;
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index 75f5fa9..25b119f 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -125,13 +125,10 @@ void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask)
#define cpu_init uc32_cpu_init
#define cpu_exec uc32_cpu_exec
#define cpu_signal_handler uc32_cpu_signal_handler
-#define cpu_handle_mmu_fault uc32_cpu_handle_mmu_fault
CPUUniCore32State *uc32_cpu_init(const char *cpu_model);
int uc32_cpu_exec(CPUUniCore32State *s);
int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
-int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw,
- int mmu_idx);
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
@@ -142,6 +139,8 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int
#include "cpu-qom.h"
#include "exec/exec-all.h"
+int uc32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
+ int mmu_idx);
void uc32_translate_init(void);
void switch_mode(CPUUniCore32State *, int);
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index 61eb2c3..4e90cf3 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -250,9 +250,12 @@ void uc32_cpu_do_interrupt(CPUState *cs)
cpu_abort(env, "NO interrupt in user mode\n");
}
-int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
+int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
int access_type, int mmu_idx)
{
+ UniCore32CPU *cpu = UNICORE32_CPU(cs);
+ CPUUniCore32State *env = &cpu->env;
+
cpu_abort(env, "NO mmu fault in user mode\n");
return 1;
}
diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
index 4f9f41e..5cd2378 100644
--- a/target-unicore32/op_helper.c
+++ b/target-unicore32/op_helper.c
@@ -258,9 +258,10 @@ uint32_t HELPER(ror_cc)(CPUUniCore32State *env, uint32_t x, uint32_t i)
void tlb_fill(CPUUniCore32State *env, target_ulong addr, int is_write,
int mmu_idx, uintptr_t retaddr)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
int ret;
- ret = uc32_cpu_handle_mmu_fault(env, addr, is_write, mmu_idx);
+ ret = uc32_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */
diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
index 1e13a85..408f1b0 100644
--- a/target-unicore32/softmmu.c
+++ b/target-unicore32/softmmu.c
@@ -208,9 +208,11 @@ do_fault:
return code;
}
-int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
+int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
int access_type, int mmu_idx)
{
+ UniCore32CPU *cpu = UNICORE32_CPU(cs);
+ CPUUniCore32State *env = &cpu->env;
uint32_t phys_addr;
target_ulong page_size;
int prot;
@@ -230,7 +232,7 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
ret = get_phys_addr_ucv2(env, address, access_type, is_user,
&phys_addr, &prot, &page_size);
if (is_user) {
- DPRINTF("user space access: ret %x, address %x, "
+ DPRINTF("user space access: ret %x, address %" VADDR_PRIx ", "
"access_type %x, phys_addr %x, prot %x\n",
ret, address, access_type, phys_addr, prot);
}
diff --git a/user-exec.c b/user-exec.c
index 82bfa66..d850d41 100644
--- a/user-exec.c
+++ b/user-exec.c
@@ -82,6 +82,8 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
int is_write, sigset_t *old_set,
void *puc)
{
+ CPUState *cpu;
+ CPUClass *cc;
CPUArchState *env;
int ret;
@@ -99,9 +101,12 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
are still valid segv ones */
address = h2g_nocheck(address);
- env = current_cpu->env_ptr;
+ cpu = current_cpu;
+ cc = CPU_GET_CLASS(cpu);
+ env = cpu->env_ptr;
/* see if it is an MMU fault */
- ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX);
+ g_assert(cc->handle_mmu_fault);
+ ret = cc->handle_mmu_fault(cpu, address, is_write, MMU_USER_IDX);
if (ret < 0) {
return 0; /* not an MMU fault */
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 04/41] cpu: Turn cpu_handle_mmu_fault() into a CPUClass hook
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 04/41] cpu: Turn cpu_handle_mmu_fault() " Andreas Färber
@ 2013-09-04 12:46 ` Jia Liu
0 siblings, 0 replies; 68+ messages in thread
From: Jia Liu @ 2013-09-04 12:46 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Anthony Green, qemu-devel@nongnu.org,
Alexander Graf, Blue Swirl, Michael Walle, open list:PowerPC,
Paul Brook, Edgar E. Iglesias, Guan Xuetao, Aurelien Jarno,
Richard Henderson
On Wed, Sep 4, 2013 at 5:04 PM, Andreas Färber <afaerber@suse.de> wrote:
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
> include/qom/cpu.h | 3 +++
> target-alpha/cpu.c | 4 +++-
> target-alpha/cpu.h | 5 ++---
> target-alpha/helper.c | 12 ++++++++----
> target-alpha/mem_helper.c | 3 ++-
> target-arm/cpu.c | 4 +++-
> target-arm/cpu.h | 5 ++---
> target-arm/helper.c | 13 +++++++++----
> target-arm/op_helper.c | 3 ++-
> target-cris/cpu.c | 4 +++-
> target-cris/cpu.h | 3 +--
> target-cris/helper.c | 24 +++++++++++++-----------
> target-cris/op_helper.c | 3 ++-
> target-i386/cpu.c | 4 +++-
> target-i386/cpu.h | 3 +--
> target-i386/helper.c | 19 ++++++++++++-------
> target-i386/mem_helper.c | 3 ++-
> target-lm32/cpu.c | 4 +++-
> target-lm32/cpu.h | 3 +--
> target-lm32/helper.c | 4 +++-
> target-lm32/op_helper.c | 3 ++-
> target-m68k/cpu.c | 4 +++-
> target-m68k/cpu.h | 3 +--
> target-m68k/helper.c | 17 ++++++++++-------
> target-m68k/op_helper.c | 3 ++-
> target-microblaze/cpu.c | 4 +++-
> target-microblaze/cpu.h | 3 +--
> target-microblaze/helper.c | 14 ++++++++------
> target-microblaze/op_helper.c | 3 ++-
> target-mips/cpu.c | 4 +++-
> target-mips/cpu.h | 5 ++---
> target-mips/helper.c | 15 +++++++++------
> target-mips/op_helper.c | 3 ++-
> target-moxie/cpu.c | 4 +++-
> target-moxie/cpu.h | 2 +-
> target-moxie/helper.c | 19 +++++++++++--------
> target-openrisc/cpu.c | 4 +++-
> target-openrisc/cpu.h | 4 +---
> target-openrisc/mmu.c | 14 +++++++-------
> target-openrisc/mmu_helper.c | 3 ++-
> target-ppc/cpu.h | 4 ++--
> target-ppc/translate_init.c | 4 +++-
> target-ppc/user_only_helper.c | 6 ++++--
> target-s390x/cpu.c | 4 +++-
> target-s390x/cpu.h | 5 ++---
> target-s390x/helper.c | 20 ++++++++++++--------
> target-s390x/mem_helper.c | 3 ++-
> target-sh4/cpu.c | 4 +++-
> target-sh4/cpu.h | 5 ++---
> target-sh4/helper.c | 13 +++++++++----
> target-sh4/op_helper.c | 3 ++-
> target-sparc/cpu.c | 4 +++-
> target-sparc/cpu.h | 3 +--
> target-sparc/ldst_helper.c | 3 ++-
> target-sparc/mmu_helper.c | 18 ++++++++++++------
> target-unicore32/cpu.c | 4 +++-
> target-unicore32/cpu.h | 5 ++---
> target-unicore32/helper.c | 5 ++++-
> target-unicore32/op_helper.c | 3 ++-
> target-unicore32/softmmu.c | 6 ++++--
> user-exec.c | 9 +++++++--
> 61 files changed, 238 insertions(+), 150 deletions(-)
>
> diff --git a/include/qom/cpu.h b/include/qom/cpu.h
> index 3d6b66e..4d974f3 100644
> --- a/include/qom/cpu.h
> +++ b/include/qom/cpu.h
> @@ -84,6 +84,7 @@ struct TranslationBlock;
> * #TranslationBlock.
> * @synchronize_from_tb: Callback for synchronizing state from a TCG
> * #TranslationBlock.
> + * @handle_mmu_fault: Callback for handling an MMU fault.
> * @get_phys_page_debug: Callback for obtaining a physical address.
> * @gdb_read_register: Callback for letting GDB read a register.
> * @gdb_write_register: Callback for letting GDB write a register.
> @@ -120,6 +121,8 @@ typedef struct CPUClass {
> void (*get_tb_cpu_state)(const CPUState *cpu, vaddr *pc, vaddr *cs_base,
> int *flags);
> void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
> + int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw,
> + int mmu_index);
> hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
> int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
> int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
> diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
> index bb1eddc..e880983 100644
> --- a/target-alpha/cpu.c
> +++ b/target-alpha/cpu.c
> @@ -330,7 +330,9 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
> cc->get_tb_cpu_state = alpha_cpu_get_tb_cpu_state;
> cc->gdb_read_register = alpha_cpu_gdb_read_register;
> cc->gdb_write_register = alpha_cpu_gdb_write_register;
> -#ifndef CONFIG_USER_ONLY
> +#ifdef CONFIG_USER_ONLY
> + cc->handle_mmu_fault = alpha_cpu_handle_mmu_fault;
> +#else
> cc->do_unassigned_access = alpha_cpu_unassigned_access;
> cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug;
> dc->vmsd = &vmstate_alpha_cpu;
> diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
> index a4abce8..dd117d9 100644
> --- a/target-alpha/cpu.h
> +++ b/target-alpha/cpu.h
> @@ -435,9 +435,8 @@ int cpu_alpha_exec(CPUAlphaState *s);
> is returned if the signal was handled by the virtual CPU. */
> int cpu_alpha_signal_handler(int host_signum, void *pinfo,
> void *puc);
> -int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, uint64_t address, int rw,
> - int mmu_idx);
> -#define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
> +int alpha_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
> + int mmu_idx);
> void do_restore_state(CPUAlphaState *, uintptr_t retaddr);
> void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
> void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);
> diff --git a/target-alpha/helper.c b/target-alpha/helper.c
> index fc61bb0..ef2dc25 100644
> --- a/target-alpha/helper.c
> +++ b/target-alpha/helper.c
> @@ -168,11 +168,13 @@ void helper_store_fpcr(CPUAlphaState *env, uint64_t val)
> }
>
> #if defined(CONFIG_USER_ONLY)
> -int cpu_alpha_handle_mmu_fault(CPUAlphaState *env, target_ulong address,
> +int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> int rw, int mmu_idx)
> {
> - env->exception_index = EXCP_MMFAULT;
> - env->trap_arg0 = address;
> + AlphaCPU *cpu = ALPHA_CPU(cs);
> +
> + cpu->env.exception_index = EXCP_MMFAULT;
> + cpu->env.trap_arg0 = address;
> return 1;
> }
> #else
> @@ -325,9 +327,11 @@ hwaddr alpha_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
> return (fail >= 0 ? -1 : phys);
> }
>
> -int cpu_alpha_handle_mmu_fault(CPUAlphaState *env, target_ulong addr, int rw,
> +int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int rw,
> int mmu_idx)
> {
> + AlphaCPU *cpu = ALPHA_CPU(cs);
> + CPUAlphaState *env = &cpu->env;
> target_ulong phys;
> int prot, fail;
>
> diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
> index 7160a1c..d140688 100644
> --- a/target-alpha/mem_helper.c
> +++ b/target-alpha/mem_helper.c
> @@ -145,9 +145,10 @@ void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr,
> void tlb_fill(CPUAlphaState *env, target_ulong addr, int is_write,
> int mmu_idx, uintptr_t retaddr)
> {
> + AlphaCPU *cpu = alpha_env_get_cpu(env);
> int ret;
>
> - ret = cpu_alpha_handle_mmu_fault(env, addr, is_write, mmu_idx);
> + ret = alpha_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> if (unlikely(ret != 0)) {
> if (retaddr) {
> cpu_restore_state(env, retaddr);
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 53bf337..4c6fe17 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -938,7 +938,9 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
> cc->get_tb_cpu_state = arm_cpu_get_tb_cpu_state;
> cc->gdb_read_register = arm_cpu_gdb_read_register;
> cc->gdb_write_register = arm_cpu_gdb_write_register;
> -#ifndef CONFIG_USER_ONLY
> +#ifdef CONFIG_USER_ONLY
> + cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
> +#else
> cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
> cc->vmsd = &vmstate_arm_cpu;
> #endif
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 161b9fd..ce98dda 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -266,9 +266,8 @@ uint32_t do_arm_semihosting(CPUARMState *env);
> is returned if the signal was handled by the virtual CPU. */
> int cpu_arm_signal_handler(int host_signum, void *pinfo,
> void *puc);
> -int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
> - int mmu_idx);
> -#define cpu_handle_mmu_fault cpu_arm_handle_mmu_fault
> +int arm_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
> + int mmu_idx);
>
> #define CPSR_M (0x1f)
> #define CPSR_T (1 << 5)
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index e51ef20..9d0d8b4 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2078,9 +2078,12 @@ void arm_cpu_do_interrupt(CPUState *cs)
> env->exception_index = -1;
> }
>
> -int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
> - int mmu_idx)
> +int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> + int mmu_idx)
> {
> + ARMCPU *cpu = ARM_CPU(cs);
> + CPUARMState *env = &cpu->env;
> +
> if (rw == 2) {
> env->exception_index = EXCP_PREFETCH_ABORT;
> env->cp15.c6_insn = address;
> @@ -3026,9 +3029,11 @@ static inline int get_phys_addr(CPUARMState *env, uint32_t address,
> }
> }
>
> -int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
> - int access_type, int mmu_idx)
> +int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> + int access_type, int mmu_idx)
> {
> + ARMCPU *cpu = ARM_CPU(cs);
> + CPUARMState *env = &cpu->env;
> hwaddr phys_addr;
> target_ulong page_size;
> int prot;
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index a918e5b..13d34fb 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -74,9 +74,10 @@ uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
> void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> + ARMCPU *cpu = arm_env_get_cpu(env);
> int ret;
>
> - ret = cpu_arm_handle_mmu_fault(env, addr, is_write, mmu_idx);
> + ret = arm_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> if (retaddr) {
> /* now we have a real cpu fault */
> diff --git a/target-cris/cpu.c b/target-cris/cpu.c
> index 39a25ed..504d6a4 100644
> --- a/target-cris/cpu.c
> +++ b/target-cris/cpu.c
> @@ -290,7 +290,9 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
> cc->get_tb_cpu_state = cris_cpu_get_tb_cpu_state;
> cc->gdb_read_register = cris_cpu_gdb_read_register;
> cc->gdb_write_register = cris_cpu_gdb_write_register;
> -#ifndef CONFIG_USER_ONLY
> +#ifdef CONFIG_USER_ONLY
> + cc->handle_mmu_fault = cris_cpu_handle_mmu_fault;
> +#else
> cc->get_phys_page_debug = cris_cpu_get_phys_page_debug;
> #endif
>
> diff --git a/target-cris/cpu.h b/target-cris/cpu.h
> index 9f1fa38..9e9cb8c 100644
> --- a/target-cris/cpu.h
> +++ b/target-cris/cpu.h
> @@ -239,9 +239,8 @@ static inline CPUCRISState *cpu_init(const char *cpu_model)
> #define MMU_MODE1_SUFFIX _user
> #define MMU_USER_IDX 1
>
> -int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
> +int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
> int mmu_idx);
> -#define cpu_handle_mmu_fault cpu_cris_handle_mmu_fault
>
> /* Support function regs. */
> #define SFR_RW_GC_CFG 0][0
> diff --git a/target-cris/helper.c b/target-cris/helper.c
> index d274b38..72dc839 100644
> --- a/target-cris/helper.c
> +++ b/target-cris/helper.c
> @@ -50,14 +50,14 @@ void crisv10_cpu_do_interrupt(CPUState *cs)
> cris_cpu_do_interrupt(cs);
> }
>
> -int cpu_cris_handle_mmu_fault(CPUCRISState * env, target_ulong address, int rw,
> +int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> int mmu_idx)
> {
> - CRISCPU *cpu = cris_env_get_cpu(env);
> + CRISCPU *cpu = CRIS_CPU(cs);
>
> - env->exception_index = 0xaa;
> - env->pregs[PR_EDA] = address;
> - cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
> + cpu->env.exception_index = 0xaa;
> + cpu->env.pregs[PR_EDA] = address;
> + cpu_dump_state(cs, stderr, fprintf, 0);
> return 1;
> }
>
> @@ -73,23 +73,25 @@ static void cris_shift_ccs(CPUCRISState *env)
> env->pregs[PR_CCS] = ccs;
> }
>
> -int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
> +int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> int mmu_idx)
> {
> - D(CPUState *cpu = CPU(cris_env_get_cpu(env)));
> + CRISCPU *cpu = CRIS_CPU(cs);
> + CPUCRISState *env = &cpu->env;
> struct cris_mmu_result res;
> int prot, miss;
> int r = -1;
> target_ulong phy;
>
> - D(printf("%s addr=%x pc=%x rw=%x\n", __func__, address, env->pc, rw));
> + D(printf("%s addr=%" VADDR_PRIx " pc=%x rw=%x\n",
> + __func__, address, env->pc, rw));
> miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
> rw, mmu_idx, 0);
> if (miss) {
> if (env->exception_index == EXCP_BUSFAULT) {
> cpu_abort(env,
> "CRIS: Illegal recursive bus fault."
> - "addr=%x rw=%d\n",
> + "addr=%" VADDR_PRIx " rw=%d\n",
> address, rw);
> }
>
> @@ -109,8 +111,8 @@ int cpu_cris_handle_mmu_fault(CPUCRISState *env, target_ulong address, int rw,
> r = 0;
> }
> if (r > 0) {
> - D_LOG("%s returns %d irqreq=%x addr=%x phy=%x vec=%x pc=%x\n",
> - __func__, r, cpu->interrupt_request, address, res.phy,
> + D_LOG("%s returns %d irqreq=%x addr=%" VADDR_PRIx " phy=%x vec=%x"
> + " pc=%x\n", __func__, r, cs->interrupt_request, address, res.phy,
> res.bf_vec, env->pc);
> }
> return r;
> diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
> index b580513..4a6215d 100644
> --- a/target-cris/op_helper.c
> +++ b/target-cris/op_helper.c
> @@ -57,11 +57,12 @@
> void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> + CRISCPU *cpu = cris_env_get_cpu(env);
> int ret;
>
> D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__,
> env->pc, env->pregs[PR_EDA], (void *)retaddr);
> - ret = cpu_cris_handle_mmu_fault(env, addr, is_write, mmu_idx);
> + ret = cris_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> if (retaddr) {
> /* now we have a real cpu fault */
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 995d5ff..3ed5a11 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -2743,7 +2743,9 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
> cc->gdb_write_register = x86_cpu_gdb_write_register;
> cc->get_arch_id = x86_cpu_get_arch_id;
> cc->get_paging_enabled = x86_cpu_get_paging_enabled;
> -#ifndef CONFIG_USER_ONLY
> +#ifdef CONFIG_USER_ONLY
> + cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
> +#else
> cc->get_memory_mapping = x86_cpu_get_memory_mapping;
> cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
> cc->write_elf64_note = x86_cpu_write_elf64_note;
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index 999a46c..3620699 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -1042,9 +1042,8 @@ void host_cpuid(uint32_t function, uint32_t count,
> uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
>
> /* helper.c */
> -int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
> +int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr,
> int is_write, int mmu_idx);
> -#define cpu_handle_mmu_fault cpu_x86_handle_mmu_fault
> void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
>
> static inline bool hw_local_breakpoint_enabled(unsigned long dr7, int index)
> diff --git a/target-i386/helper.c b/target-i386/helper.c
> index 7c58e27..b25dafc 100644
> --- a/target-i386/helper.c
> +++ b/target-i386/helper.c
> @@ -485,9 +485,12 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
>
> #if defined(CONFIG_USER_ONLY)
>
> -int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
> +int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
> int is_write, int mmu_idx)
> {
> + X86CPU *cpu = X86_CPU(cs);
> + CPUX86State *env = &cpu->env;
> +
> /* user mode only emulation */
> is_write &= 1;
> env->cr[2] = addr;
> @@ -508,13 +511,15 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
> # endif
>
> /* return value:
> - -1 = cannot handle fault
> - 0 = nothing more to do
> - 1 = generate PF fault
> -*/
> -int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
> + * -1 = cannot handle fault
> + * 0 = nothing more to do
> + * 1 = generate PF fault
> + */
> +int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
> int is_write1, int mmu_idx)
> {
> + X86CPU *cpu = X86_CPU(cs);
> + CPUX86State *env = &cpu->env;
> uint64_t ptep, pte;
> target_ulong pde_addr, pte_addr;
> int error_code, is_dirty, prot, page_size, is_write, is_user;
> @@ -524,7 +529,7 @@ int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr,
>
> is_user = mmu_idx == MMU_USER_IDX;
> #if defined(DEBUG_MMU)
> - printf("MMU fault: addr=" TARGET_FMT_lx " w=%d u=%d eip=" TARGET_FMT_lx "\n",
> + printf("MMU fault: addr=%" VADDR_PRIx " w=%d u=%d eip=" TARGET_FMT_lx "\n",
> addr, is_write1, is_user, env->eip);
> #endif
> is_write = is_write1 & 1;
> diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c
> index 319a219..5b25ccd 100644
> --- a/target-i386/mem_helper.c
> +++ b/target-i386/mem_helper.c
> @@ -135,9 +135,10 @@ void helper_boundl(CPUX86State *env, target_ulong a0, int v)
> void tlb_fill(CPUX86State *env, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> + X86CPU *cpu = x86_env_get_cpu(env);
> int ret;
>
> - ret = cpu_x86_handle_mmu_fault(env, addr, is_write, mmu_idx);
> + ret = x86_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> if (ret) {
> if (retaddr) {
> /* now we have a real cpu fault */
> diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
> index 7976d39..607e332 100644
> --- a/target-lm32/cpu.c
> +++ b/target-lm32/cpu.c
> @@ -108,7 +108,9 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
> cc->get_tb_cpu_state = lm32_cpu_get_tb_cpu_state;
> cc->gdb_read_register = lm32_cpu_gdb_read_register;
> cc->gdb_write_register = lm32_cpu_gdb_write_register;
> -#ifndef CONFIG_USER_ONLY
> +#ifdef CONFIG_USER_ONLY
> + cc->handle_mmu_fault = lm32_cpu_handle_mmu_fault;
> +#else
> cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
> cc->vmsd = &vmstate_lm32_cpu;
> #endif
> diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
> index a34f047..a94fd79 100644
> --- a/target-lm32/cpu.h
> +++ b/target-lm32/cpu.h
> @@ -207,9 +207,8 @@ static inline CPULM32State *cpu_init(const char *cpu_model)
> #define cpu_gen_code cpu_lm32_gen_code
> #define cpu_signal_handler cpu_lm32_signal_handler
>
> -int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
> +int lm32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
> int mmu_idx);
> -#define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault
>
> #include "exec/cpu-all.h"
> #include "exec/exec-all.h"
> diff --git a/target-lm32/helper.c b/target-lm32/helper.c
> index 15bc615..55a3de6 100644
> --- a/target-lm32/helper.c
> +++ b/target-lm32/helper.c
> @@ -20,9 +20,11 @@
> #include "cpu.h"
> #include "qemu/host-utils.h"
>
> -int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
> +int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> int mmu_idx)
> {
> + LM32CPU *cpu = LM32_CPU(cs);
> + CPULM32State *env = &cpu->env;
> int prot;
>
> address &= TARGET_PAGE_MASK;
> diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
> index 8f5ef55..215215e 100644
> --- a/target-lm32/op_helper.c
> +++ b/target-lm32/op_helper.c
> @@ -80,9 +80,10 @@ uint32_t HELPER(rcsr_jrx)(CPULM32State *env)
> void tlb_fill(CPULM32State *env, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> + LM32CPU *cpu = lm32_env_get_cpu(env);
> int ret;
>
> - ret = cpu_lm32_handle_mmu_fault(env, addr, is_write, mmu_idx);
> + ret = lm32_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> if (retaddr) {
> /* now we have a real cpu fault */
> diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
> index 6dbfe89..e46b647 100644
> --- a/target-m68k/cpu.c
> +++ b/target-m68k/cpu.c
> @@ -222,7 +222,9 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
> cc->get_tb_cpu_state = m68k_cpu_get_tb_cpu_state;
> cc->gdb_read_register = m68k_cpu_gdb_read_register;
> cc->gdb_write_register = m68k_cpu_gdb_write_register;
> -#ifndef CONFIG_USER_ONLY
> +#ifdef CONFIG_USER_ONLY
> + cc->handle_mmu_fault = m68k_cpu_handle_mmu_fault;
> +#else
> cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
> #endif
> dc->vmsd = &vmstate_m68k_cpu;
> diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
> index 5c7992e..b8ad269 100644
> --- a/target-m68k/cpu.h
> +++ b/target-m68k/cpu.h
> @@ -233,9 +233,8 @@ static inline CPUM68KState *cpu_init(const char *cpu_model)
> #define MMU_MODE1_SUFFIX _user
> #define MMU_USER_IDX 1
>
> -int cpu_m68k_handle_mmu_fault(CPUM68KState *env, target_ulong address, int rw,
> +int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
> int mmu_idx);
> -#define cpu_handle_mmu_fault cpu_m68k_handle_mmu_fault
>
> #include "exec/cpu-all.h"
> #include "exec/exec-all.h"
> diff --git a/target-m68k/helper.c b/target-m68k/helper.c
> index 00a7a08..25a0570 100644
> --- a/target-m68k/helper.c
> +++ b/target-m68k/helper.c
> @@ -278,11 +278,13 @@ void m68k_switch_sp(CPUM68KState *env)
>
> #if defined(CONFIG_USER_ONLY)
>
> -int cpu_m68k_handle_mmu_fault (CPUM68KState *env, target_ulong address, int rw,
> - int mmu_idx)
> +int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> + int mmu_idx)
> {
> - env->exception_index = EXCP_ACCESS;
> - env->mmu.ar = address;
> + M68kCPU *cpu = M68K_CPU(cs);
> +
> + cpu->env.exception_index = EXCP_ACCESS;
> + cpu->env.mmu.ar = address;
> return 1;
> }
>
> @@ -296,14 +298,15 @@ hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
> return addr;
> }
>
> -int cpu_m68k_handle_mmu_fault (CPUM68KState *env, target_ulong address, int rw,
> - int mmu_idx)
> +int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> + int mmu_idx)
> {
> + M68kCPU *cpu = M68K_CPU(cs);
> int prot;
>
> address &= TARGET_PAGE_MASK;
> prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
> - tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
> + tlb_set_page(&cpu->env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
> return 0;
> }
>
> diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
> index 30f7d8b..bc10f38 100644
> --- a/target-m68k/op_helper.c
> +++ b/target-m68k/op_helper.c
> @@ -59,9 +59,10 @@ extern int semihosting_enabled;
> void tlb_fill(CPUM68KState *env, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> + M68kCPU *cpu = m68k_env_get_cpu(env);
> int ret;
>
> - ret = cpu_m68k_handle_mmu_fault(env, addr, is_write, mmu_idx);
> + ret = m68k_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> if (retaddr) {
> /* now we have a real cpu fault */
> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
> index fbcdcc4..8b248f4 100644
> --- a/target-microblaze/cpu.c
> +++ b/target-microblaze/cpu.c
> @@ -178,7 +178,9 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
> cc->get_tb_cpu_state = mb_cpu_get_tb_cpu_state;
> cc->gdb_read_register = mb_cpu_gdb_read_register;
> cc->gdb_write_register = mb_cpu_gdb_write_register;
> -#ifndef CONFIG_USER_ONLY
> +#ifdef CONFIG_USER_ONLY
> + cc->handle_mmu_fault = mb_cpu_handle_mmu_fault;
> +#else
> cc->do_unassigned_access = mb_cpu_unassigned_access;
> cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
> #endif
> diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
> index d80f812..1177e51 100644
> --- a/target-microblaze/cpu.h
> +++ b/target-microblaze/cpu.h
> @@ -316,9 +316,8 @@ static inline CPUMBState *cpu_init(const char *cpu_model)
> #define MMU_USER_IDX 2
> /* See NB_MMU_MODES further up the file. */
>
> -int cpu_mb_handle_mmu_fault(CPUMBState *env, target_ulong address, int rw,
> +int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
> int mmu_idx);
> -#define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
>
> static inline int cpu_interrupts_enabled(CPUMBState *env)
> {
> diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
> index 4fa9ce9..d03f369 100644
> --- a/target-microblaze/helper.c
> +++ b/target-microblaze/helper.c
> @@ -36,21 +36,23 @@ void mb_cpu_do_interrupt(CPUState *cs)
> env->regs[14] = env->sregs[SR_PC];
> }
>
> -int cpu_mb_handle_mmu_fault(CPUMBState * env, target_ulong address, int rw,
> +int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> int mmu_idx)
> {
> - MicroBlazeCPU *cpu = mb_env_get_cpu(env);
> + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
>
> - env->exception_index = 0xaa;
> - cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
> + cpu->env.exception_index = 0xaa;
> + cpu_dump_state(cs, stderr, fprintf, 0);
> return 1;
> }
>
> #else /* !CONFIG_USER_ONLY */
>
> -int cpu_mb_handle_mmu_fault (CPUMBState *env, target_ulong address, int rw,
> - int mmu_idx)
> +int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> + int mmu_idx)
> {
> + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
> + CPUMBState *env = &cpu->env;
> unsigned int hit;
> unsigned int mmu_available;
> int r = 1;
> diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
> index 14baa84..b70b2ea 100644
> --- a/target-microblaze/op_helper.c
> +++ b/target-microblaze/op_helper.c
> @@ -44,9 +44,10 @@
> void tlb_fill(CPUMBState *env, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> + MicroBlazeCPU *cpu = mb_env_get_cpu(env);
> int ret;
>
> - ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx);
> + ret = mb_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> if (retaddr) {
> /* now we have a real cpu fault */
> diff --git a/target-mips/cpu.c b/target-mips/cpu.c
> index 4aa06bb..2fd5591 100644
> --- a/target-mips/cpu.c
> +++ b/target-mips/cpu.c
> @@ -153,7 +153,9 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
> cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
> cc->gdb_read_register = mips_cpu_gdb_read_register;
> cc->gdb_write_register = mips_cpu_gdb_write_register;
> -#ifndef CONFIG_USER_ONLY
> +#ifdef CONFIG_USER_ONLY
> + cc->handle_mmu_fault = mips_cpu_handle_mmu_fault;
> +#else
> cc->do_unassigned_access = mips_cpu_unassigned_access;
> cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
> #endif
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index 91217ed..b71a711 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -649,9 +649,8 @@ void cpu_mips_stop_count(CPUMIPSState *env);
> void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
>
> /* helper.c */
> -int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw,
> - int mmu_idx);
> -#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
> +int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
> + int mmu_idx);
> #if !defined(CONFIG_USER_ONLY)
> void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
> hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
> diff --git a/target-mips/helper.c b/target-mips/helper.c
> index 33e0e88..d8e9166 100644
> --- a/target-mips/helper.c
> +++ b/target-mips/helper.c
> @@ -268,9 +268,11 @@ hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
> }
> #endif
>
> -int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw,
> - int mmu_idx)
> +int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> + int mmu_idx)
> {
> + MIPSCPU *cpu = MIPS_CPU(cs);
> + CPUMIPSState *env = &cpu->env;
> #if !defined(CONFIG_USER_ONLY)
> hwaddr physical;
> int prot;
> @@ -279,9 +281,9 @@ int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw,
> int ret = 0;
>
> #if 0
> - log_cpu_state(CPU(mips_env_get_cpu(env)), 0);
> + log_cpu_state(cs, 0);
> #endif
> - qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d\n",
> + qemu_log("%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
> __func__, env->active_tc.PC, address, rw, mmu_idx);
>
> rw &= 1;
> @@ -293,8 +295,9 @@ int cpu_mips_handle_mmu_fault (CPUMIPSState *env, target_ulong address, int rw,
> access_type = ACCESS_INT;
> ret = get_physical_address(env, &physical, &prot,
> address, rw, access_type);
> - qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx " prot %d\n",
> - __func__, address, ret, physical, prot);
> + qemu_log("%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
> + " prot %d\n",
> + __func__, address, ret, physical, prot);
> if (ret == TLBRET_MATCH) {
> tlb_set_page(env, address & TARGET_PAGE_MASK,
> physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
> index 8e3a6d7..34ac4c6 100644
> --- a/target-mips/op_helper.c
> +++ b/target-mips/op_helper.c
> @@ -2134,9 +2134,10 @@ static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
> void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> + MIPSCPU *cpu = mips_env_get_cpu(env);
> int ret;
>
> - ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx);
> + ret = mips_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> if (ret) {
> do_raise_exception_err(env, env->exception_index,
> env->error_code, retaddr);
> diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
> index 9983c99..e07a4df 100644
> --- a/target-moxie/cpu.c
> +++ b/target-moxie/cpu.c
> @@ -119,7 +119,9 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data)
> cc->dump_state = moxie_cpu_dump_state;
> cc->set_pc = moxie_cpu_set_pc;
> cc->get_tb_cpu_state = moxie_cpu_get_tb_cpu_state;
> -#ifndef CONFIG_USER_ONLY
> +#ifdef CONFIG_USER_ONLY
> + cc->handle_mmu_fault = moxie_cpu_handle_mmu_fault;
> +#else
> cc->get_phys_page_debug = moxie_cpu_get_phys_page_debug;
> cc->vmsd = &vmstate_moxie_cpu;
> #endif
> diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h
> index 7e33efe..fb2a97e 100644
> --- a/target-moxie/cpu.h
> +++ b/target-moxie/cpu.h
> @@ -139,7 +139,7 @@ static inline CPUMoxieState *cpu_init(const char *cpu_model)
> #include "exec/cpu-all.h"
> #include "exec/exec-all.h"
>
> -int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address,
> +int moxie_cpu_handle_mmu_fault(CPUState *cpu, vaddr address,
> int rw, int mmu_idx);
>
> #endif /* _CPU_MOXIE_H */
> diff --git a/target-moxie/helper.c b/target-moxie/helper.c
> index 7859102..8160475 100644
> --- a/target-moxie/helper.c
> +++ b/target-moxie/helper.c
> @@ -49,9 +49,10 @@
> void tlb_fill(CPUMoxieState *env, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> + MoxieCPU *cpu = moxie_env_get_cpu(env);
> int ret;
>
> - ret = cpu_moxie_handle_mmu_fault(env, addr, is_write, mmu_idx);
> + ret = moxie_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> if (retaddr) {
> cpu_restore_state(env, retaddr);
> @@ -103,27 +104,29 @@ void helper_debug(CPUMoxieState *env)
>
> #if defined(CONFIG_USER_ONLY)
>
> -void moxie_cpu_do_interrupt(CPUState *env)
> +void moxie_cpu_do_interrupt(CPUState *cs)
> {
> env->exception_index = -1;
> }
>
> -int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address,
> +int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> int rw, int mmu_idx)
> {
> - MoxieCPU *cpu = moxie_env_get_cpu(env);
> + MoxieCPU *cpu = MOXIE_CPU(cs);
>
> - env->exception_index = 0xaa;
> - env->debug1 = address;
> - cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
> + cpu->env.exception_index = 0xaa;
> + cpu->env.debug1 = address;
> + cpu_dump_state(cs, stderr, fprintf, 0);
> return 1;
> }
>
> #else /* !CONFIG_USER_ONLY */
>
> -int cpu_moxie_handle_mmu_fault(CPUMoxieState *env, target_ulong address,
> +int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> int rw, int mmu_idx)
> {
> + MoxieCPU *cpu = MOXIE_CPU(cs);
> + CPUMoxieState *env = &cpu->env;
> MoxieMMUResult res;
> int prot, miss;
> target_ulong phy;
> diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
> index 107e5f9..ee1591d 100644
> --- a/target-openrisc/cpu.c
> +++ b/target-openrisc/cpu.c
> @@ -188,7 +188,9 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
> cc->get_tb_cpu_state = openrisc_cpu_get_tb_cpu_state;
> cc->gdb_read_register = openrisc_cpu_gdb_read_register;
> cc->gdb_write_register = openrisc_cpu_gdb_write_register;
> -#ifndef CONFIG_USER_ONLY
> +#ifdef CONFIG_USER_ONLY
> + cc->handle_mmu_fault = openrisc_cpu_handle_mmu_fault;
> +#else
> cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug;
> dc->vmsd = &vmstate_openrisc_cpu;
> #endif
> diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
> index a41c271..8745072 100644
> --- a/target-openrisc/cpu.h
> +++ b/target-openrisc/cpu.h
> @@ -353,15 +353,13 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
> int openrisc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
> int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
> void openrisc_translate_init(void);
> -int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
> - target_ulong address,
> +int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address,
> int rw, int mmu_idx);
> int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc);
>
> #define cpu_list cpu_openrisc_list
> #define cpu_exec cpu_openrisc_exec
> #define cpu_gen_code cpu_openrisc_gen_code
> -#define cpu_handle_mmu_fault cpu_openrisc_handle_mmu_fault
> #define cpu_signal_handler cpu_openrisc_signal_handler
>
> #ifndef CONFIG_USER_ONLY
> diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c
> index 57f5616..0f13c5d 100644
> --- a/target-openrisc/mmu.c
> +++ b/target-openrisc/mmu.c
> @@ -181,19 +181,19 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu,
> }
>
> #ifndef CONFIG_USER_ONLY
> -int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
> - target_ulong address, int rw, int mmu_idx)
> +int openrisc_cpu_handle_mmu_fault(CPUState *cs,
> + vaddr address, int rw, int mmu_idx)
> {
> + OpenRISCCPU *cpu = OPENRISC_CPU(cs);
> int ret = 0;
> hwaddr physical = 0;
> int prot = 0;
> - OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
>
> ret = cpu_openrisc_get_phys_addr(cpu, &physical, &prot,
> address, rw);
>
> if (ret == TLBRET_MATCH) {
> - tlb_set_page(env, address & TARGET_PAGE_MASK,
> + tlb_set_page(&cpu->env, address & TARGET_PAGE_MASK,
> physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
> mmu_idx, TARGET_PAGE_SIZE);
> ret = 0;
> @@ -205,11 +205,11 @@ int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
> return ret;
> }
> #else
> -int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
> - target_ulong address, int rw, int mmu_idx)
> +int openrisc_cpu_handle_mmu_fault(CPUState *cs,
> + vaddr address, int rw, int mmu_idx)
> {
> + OpenRISCCPU *cpu = OPENRISC_CPU(cs);
> int ret = 0;
> - OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
>
> cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret);
> ret = 1;
> diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c
> index e46b092..b023a5f 100644
> --- a/target-openrisc/mmu_helper.c
> +++ b/target-openrisc/mmu_helper.c
> @@ -39,9 +39,10 @@
> void tlb_fill(CPUOpenRISCState *env, target_ulong addr, int is_write,
> int mmu_idx, uintptr_t retaddr)
> {
> + OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
> int ret;
>
> - ret = cpu_openrisc_handle_mmu_fault(env, addr, is_write, mmu_idx);
> + ret = openrisc_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
>
> if (ret) {
> if (retaddr) {
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 2ebf0a1..3b03ae6 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1098,8 +1098,8 @@ int cpu_ppc_signal_handler (int host_signum, void *pinfo,
> void *puc);
> void ppc_hw_interrupt (CPUPPCState *env);
> #if defined(CONFIG_USER_ONLY)
> -int cpu_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
> - int mmu_idx);
> +int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
> + int mmu_idx);
> #endif
>
> #if !defined(CONFIG_USER_ONLY)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 338d8fe..8b6fbb5 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8595,7 +8595,9 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
> cc->get_tb_cpu_state = ppc_cpu_get_tb_cpu_state;
> cc->gdb_read_register = ppc_cpu_gdb_read_register;
> cc->gdb_write_register = ppc_cpu_gdb_write_register;
> -#ifndef CONFIG_USER_ONLY
> +#ifdef CONFIG_USER_ONLY
> + cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault;
> +#else
> cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
> cc->vmsd = &vmstate_ppc_cpu;
> #endif
> diff --git a/target-ppc/user_only_helper.c b/target-ppc/user_only_helper.c
> index 56e686e..a7c99e0 100644
> --- a/target-ppc/user_only_helper.c
> +++ b/target-ppc/user_only_helper.c
> @@ -20,9 +20,11 @@
>
> #include "cpu.h"
>
> -int cpu_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
> - int mmu_idx)
> +int ppc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> + int mmu_idx)
> {
> + PowerPCCPU *cpu = POWERPC_CPU(cs);
> + CPUPPCState *env = &cpu->env;
> int exception, error_code;
>
> if (rw == 2) {
> diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
> index a4a5370..ad0d5bc 100644
> --- a/target-s390x/cpu.c
> +++ b/target-s390x/cpu.c
> @@ -257,7 +257,9 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
> cc->get_tb_cpu_state = s390_cpu_get_tb_cpu_state;
> cc->gdb_read_register = s390_cpu_gdb_read_register;
> cc->gdb_write_register = s390_cpu_gdb_write_register;
> -#ifndef CONFIG_USER_ONLY
> +#ifdef CONFIG_USER_ONLY
> + cc->handle_mmu_fault = s390_cpu_handle_mmu_fault;
> +#else
> cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
> cc->write_elf64_note = s390_cpu_write_elf64_note;
> cc->write_elf64_qemunote = s390_cpu_write_elf64_qemunote;
> diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
> index cad092b..a09e4f9 100644
> --- a/target-s390x/cpu.h
> +++ b/target-s390x/cpu.h
> @@ -308,9 +308,8 @@ int cpu_s390x_exec(CPUS390XState *s);
> is returned if the signal was handled by the virtual CPU. */
> int cpu_s390x_signal_handler(int host_signum, void *pinfo,
> void *puc);
> -int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw,
> - int mmu_idx);
> -#define cpu_handle_mmu_fault cpu_s390x_handle_mmu_fault
> +int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
> + int mmu_idx);
>
> #include "ioinst.h"
>
> diff --git a/target-s390x/helper.c b/target-s390x/helper.c
> index 61abfd7..361d713 100644
> --- a/target-s390x/helper.c
> +++ b/target-s390x/helper.c
> @@ -94,14 +94,16 @@ void s390_cpu_do_interrupt(CPUState *cs)
> env->exception_index = -1;
> }
>
> -int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong address,
> - int rw, int mmu_idx)
> +int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> + int rw, int mmu_idx)
> {
> - env->exception_index = EXCP_PGM;
> - env->int_pgm_code = PGM_ADDRESSING;
> + S390CPU *cpu = S390_CPU(cs);
> +
> + cpu->env.exception_index = EXCP_PGM;
> + cpu->env.int_pgm_code = PGM_ADDRESSING;
> /* On real machines this value is dropped into LowMem. Since this
> is userland, simply put this someplace that cpu_loop can find it. */
> - env->__excp_addr = address;
> + cpu->env.__excp_addr = address;
> return 1;
> }
>
> @@ -377,14 +379,16 @@ int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
> return r;
> }
>
> -int cpu_s390x_handle_mmu_fault(CPUS390XState *env, target_ulong orig_vaddr,
> - int rw, int mmu_idx)
> +int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr,
> + int rw, int mmu_idx)
> {
> + S390CPU *cpu = S390_CPU(cs);
> + CPUS390XState *env = &cpu->env;
> uint64_t asc = env->psw.mask & PSW_MASK_ASC;
> target_ulong vaddr, raddr;
> int prot;
>
> - DPRINTF("%s: address 0x%" PRIx64 " rw %d mmu_idx %d\n",
> + DPRINTF("%s: address 0x%" VADDR_PRIx " rw %d mmu_idx %d\n",
> __func__, orig_vaddr, rw, mmu_idx);
>
> orig_vaddr &= TARGET_PAGE_MASK;
> diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
> index 1422ae9..747ba46 100644
> --- a/target-s390x/mem_helper.c
> +++ b/target-s390x/mem_helper.c
> @@ -47,9 +47,10 @@
> void tlb_fill(CPUS390XState *env, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> int ret;
>
> - ret = cpu_s390x_handle_mmu_fault(env, addr, is_write, mmu_idx);
> + ret = s390_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> if (unlikely(ret != 0)) {
> if (likely(retaddr)) {
> /* now we have a real cpu fault */
> diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
> index 647a527..7f98f80 100644
> --- a/target-sh4/cpu.c
> +++ b/target-sh4/cpu.c
> @@ -320,7 +320,9 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
> cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
> cc->gdb_read_register = superh_cpu_gdb_read_register;
> cc->gdb_write_register = superh_cpu_gdb_write_register;
> -#ifndef CONFIG_USER_ONLY
> +#ifdef CONFIG_USER_ONLY
> + cc->handle_mmu_fault = superh_cpu_handle_mmu_fault;
> +#else
> cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
> #endif
> dc->vmsd = &vmstate_sh_cpu;
> diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
> index 42ecdd7..8abd0cc 100644
> --- a/target-sh4/cpu.h
> +++ b/target-sh4/cpu.h
> @@ -193,9 +193,8 @@ SuperHCPU *cpu_sh4_init(const char *cpu_model);
> int cpu_sh4_exec(CPUSH4State * s);
> int cpu_sh4_signal_handler(int host_signum, void *pinfo,
> void *puc);
> -int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
> - int mmu_idx);
> -#define cpu_handle_mmu_fault cpu_sh4_handle_mmu_fault
> +int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
> + int mmu_idx);
>
> void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf);
> #if !defined(CONFIG_USER_ONLY)
> diff --git a/target-sh4/helper.c b/target-sh4/helper.c
> index 9ac2825..3f8f1fa 100644
> --- a/target-sh4/helper.c
> +++ b/target-sh4/helper.c
> @@ -39,9 +39,12 @@ void superh_cpu_do_interrupt(CPUState *cs)
> env->exception_index = -1;
> }
>
> -int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
> - int mmu_idx)
> +int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> + int mmu_idx)
> {
> + SuperHCPU *cpu = SUPERH_CPU(cs);
> + CPUSH4State *env = &cpu->env;
> +
> env->tea = address;
> env->exception_index = -1;
> switch (rw) {
> @@ -447,9 +450,11 @@ static int get_physical_address(CPUSH4State * env, target_ulong * physical,
> return get_mmu_address(env, physical, prot, address, rw, access_type);
> }
>
> -int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
> - int mmu_idx)
> +int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> + int mmu_idx)
> {
> + SuperHCPU *cpu = SUPERH_CPU(cs);
> + CPUSH4State *env = &cpu->env;
> target_ulong physical;
> int prot, ret, access_type;
>
> diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
> index e955e81..35f9067 100644
> --- a/target-sh4/op_helper.c
> +++ b/target-sh4/op_helper.c
> @@ -41,9 +41,10 @@
> void tlb_fill(CPUSH4State *env, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> + SuperHCPU *cpu = sh_env_get_cpu(env);
> int ret;
>
> - ret = cpu_sh4_handle_mmu_fault(env, addr, is_write, mmu_idx);
> + ret = superh_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> if (ret) {
> /* now we have a real cpu fault */
> if (retaddr) {
> diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
> index 49a4469..c8d8c55 100644
> --- a/target-sparc/cpu.c
> +++ b/target-sparc/cpu.c
> @@ -857,7 +857,9 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
> cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb;
> cc->gdb_read_register = sparc_cpu_gdb_read_register;
> cc->gdb_write_register = sparc_cpu_gdb_write_register;
> -#ifndef CONFIG_USER_ONLY
> +#ifdef CONFIG_USER_ONLY
> + cc->handle_mmu_fault = sparc_cpu_handle_mmu_fault;
> +#else
> cc->do_unassigned_access = sparc_cpu_unassigned_access;
> cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
> #endif
> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
> index f078851..cfa1e0d 100644
> --- a/target-sparc/cpu.h
> +++ b/target-sparc/cpu.h
> @@ -519,9 +519,8 @@ SPARCCPU *cpu_sparc_init(const char *cpu_model);
> void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
> void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf);
> /* mmu_helper.c */
> -int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
> +int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
> int mmu_idx);
> -#define cpu_handle_mmu_fault cpu_sparc_handle_mmu_fault
> target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
> void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env);
>
> diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
> index 2936b58..2f55af9 100644
> --- a/target-sparc/ldst_helper.c
> +++ b/target-sparc/ldst_helper.c
> @@ -2432,9 +2432,10 @@ static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env,
> void tlb_fill(CPUSPARCState *env, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> + SPARCCPU *cpu = sparc_env_get_cpu(env);
> int ret;
>
> - ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, mmu_idx);
> + ret = sparc_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> if (ret) {
> if (retaddr) {
> cpu_restore_state(env, retaddr);
> diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
> index 9eb096e..0d88326 100644
> --- a/target-sparc/mmu_helper.c
> +++ b/target-sparc/mmu_helper.c
> @@ -25,13 +25,15 @@
>
> #if defined(CONFIG_USER_ONLY)
>
> -int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
> +int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> int mmu_idx)
> {
> + SPARCCPU *cpu = SPARC_CPU(cs);
> +
> if (rw & 2) {
> - env1->exception_index = TT_TFAULT;
> + cpu->env.exception_index = TT_TFAULT;
> } else {
> - env1->exception_index = TT_DFAULT;
> + cpu->env.exception_index = TT_DFAULT;
> }
> return 1;
> }
> @@ -197,9 +199,11 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
> }
>
> /* Perform address translation */
> -int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw,
> +int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> int mmu_idx)
> {
> + SPARCCPU *cpu = SPARC_CPU(cs);
> + CPUSPARCState *env = &cpu->env;
> hwaddr paddr;
> target_ulong vaddr;
> target_ulong page_size;
> @@ -211,7 +215,7 @@ int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw,
> vaddr = address;
> if (error_code == 0) {
> #ifdef DEBUG_MMU
> - printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr "
> + printf("Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr "
> TARGET_FMT_lx "\n", address, paddr, vaddr);
> #endif
> tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
> @@ -703,9 +707,11 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical,
> }
>
> /* Perform address translation */
> -int cpu_sparc_handle_mmu_fault(CPUSPARCState *env, target_ulong address, int rw,
> +int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> int mmu_idx)
> {
> + SPARCCPU *cpu = SPARC_CPU(cs);
> + CPUSPARCState *env = &cpu->env;
> target_ulong vaddr;
> hwaddr paddr;
> target_ulong page_size;
> diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
> index e5fddcf..dcf3b16 100644
> --- a/target-unicore32/cpu.c
> +++ b/target-unicore32/cpu.c
> @@ -170,7 +170,9 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data)
> cc->mmu_index = uc32_cpu_mmu_index;
> cc->set_pc = uc32_cpu_set_pc;
> cc->get_tb_cpu_state = uc32_cpu_get_tb_cpu_state;
> -#ifndef CONFIG_USER_ONLY
> +#ifdef CONFIG_USER_ONLY
> + cc->handle_mmu_fault = uc32_cpu_handle_mmu_fault;
> +#else
> cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug;
> #endif
> dc->vmsd = &vmstate_uc32_cpu;
> diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
> index 75f5fa9..25b119f 100644
> --- a/target-unicore32/cpu.h
> +++ b/target-unicore32/cpu.h
> @@ -125,13 +125,10 @@ void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask)
> #define cpu_init uc32_cpu_init
> #define cpu_exec uc32_cpu_exec
> #define cpu_signal_handler uc32_cpu_signal_handler
> -#define cpu_handle_mmu_fault uc32_cpu_handle_mmu_fault
>
> CPUUniCore32State *uc32_cpu_init(const char *cpu_model);
> int uc32_cpu_exec(CPUUniCore32State *s);
> int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
> -int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw,
> - int mmu_idx);
>
> /* MMU modes definitions */
> #define MMU_MODE0_SUFFIX _kernel
> @@ -142,6 +139,8 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int
> #include "cpu-qom.h"
> #include "exec/exec-all.h"
>
> +int uc32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
> + int mmu_idx);
> void uc32_translate_init(void);
> void switch_mode(CPUUniCore32State *, int);
>
> diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
> index 61eb2c3..4e90cf3 100644
> --- a/target-unicore32/helper.c
> +++ b/target-unicore32/helper.c
> @@ -250,9 +250,12 @@ void uc32_cpu_do_interrupt(CPUState *cs)
> cpu_abort(env, "NO interrupt in user mode\n");
> }
>
> -int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
> +int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> int access_type, int mmu_idx)
> {
> + UniCore32CPU *cpu = UNICORE32_CPU(cs);
> + CPUUniCore32State *env = &cpu->env;
> +
> cpu_abort(env, "NO mmu fault in user mode\n");
> return 1;
> }
> diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
> index 4f9f41e..5cd2378 100644
> --- a/target-unicore32/op_helper.c
> +++ b/target-unicore32/op_helper.c
> @@ -258,9 +258,10 @@ uint32_t HELPER(ror_cc)(CPUUniCore32State *env, uint32_t x, uint32_t i)
> void tlb_fill(CPUUniCore32State *env, target_ulong addr, int is_write,
> int mmu_idx, uintptr_t retaddr)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> int ret;
>
> - ret = uc32_cpu_handle_mmu_fault(env, addr, is_write, mmu_idx);
> + ret = uc32_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> if (retaddr) {
> /* now we have a real cpu fault */
> diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
> index 1e13a85..408f1b0 100644
> --- a/target-unicore32/softmmu.c
> +++ b/target-unicore32/softmmu.c
> @@ -208,9 +208,11 @@ do_fault:
> return code;
> }
>
> -int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
> +int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> int access_type, int mmu_idx)
> {
> + UniCore32CPU *cpu = UNICORE32_CPU(cs);
> + CPUUniCore32State *env = &cpu->env;
> uint32_t phys_addr;
> target_ulong page_size;
> int prot;
> @@ -230,7 +232,7 @@ int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address,
> ret = get_phys_addr_ucv2(env, address, access_type, is_user,
> &phys_addr, &prot, &page_size);
> if (is_user) {
> - DPRINTF("user space access: ret %x, address %x, "
> + DPRINTF("user space access: ret %x, address %" VADDR_PRIx ", "
> "access_type %x, phys_addr %x, prot %x\n",
> ret, address, access_type, phys_addr, prot);
> }
> diff --git a/user-exec.c b/user-exec.c
> index 82bfa66..d850d41 100644
> --- a/user-exec.c
> +++ b/user-exec.c
> @@ -82,6 +82,8 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
> int is_write, sigset_t *old_set,
> void *puc)
> {
> + CPUState *cpu;
> + CPUClass *cc;
> CPUArchState *env;
> int ret;
>
> @@ -99,9 +101,12 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
> are still valid segv ones */
> address = h2g_nocheck(address);
>
> - env = current_cpu->env_ptr;
> + cpu = current_cpu;
> + cc = CPU_GET_CLASS(cpu);
> + env = cpu->env_ptr;
> /* see if it is an MMU fault */
> - ret = cpu_handle_mmu_fault(env, address, is_write, MMU_USER_IDX);
> + g_assert(cc->handle_mmu_fault);
> + ret = cc->handle_mmu_fault(cpu, address, is_write, MMU_USER_IDX);
> if (ret < 0) {
> return 0; /* not an MMU fault */
> }
target-openrisc: Tested-by: Jia Liu <proljc@gmail.com>
> --
> 1.8.1.4
>
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [RFC qom-cpu 05/41] cpu: Move mem_io_{pc, vaddr} fields from CPU_COMMON to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (3 preceding siblings ...)
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 04/41] cpu: Turn cpu_handle_mmu_fault() " Andreas Färber
@ 2013-09-04 9:04 ` Andreas Färber
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 06/41] cpu: Move can_do_io field " Andreas Färber
` (38 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Reset them.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
exec.c | 4 ++--
hw/i386/kvmvapic.c | 2 +-
include/exec/cpu-defs.h | 7 -------
include/exec/softmmu_template.h | 10 ++++++----
include/qom/cpu.h | 8 ++++++++
qom/cpu.c | 2 ++
target-i386/helper.c | 7 +++++--
translate-all.c | 15 ++++++++-------
8 files changed, 32 insertions(+), 23 deletions(-)
diff --git a/exec.c b/exec.c
index 4354eac..00c44ea 100644
--- a/exec.c
+++ b/exec.c
@@ -1459,7 +1459,7 @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
flushed */
if (dirty_flags == 0xff) {
CPUArchState *env = current_cpu->env_ptr;
- tlb_set_dirty(env, env->mem_io_vaddr);
+ tlb_set_dirty(env, current_cpu->mem_io_vaddr);
}
}
@@ -1493,7 +1493,7 @@ static void check_watchpoint(int offset, int len_mask, int flags)
cpu_interrupt(cpu, CPU_INTERRUPT_DEBUG);
return;
}
- vaddr = (env->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
+ vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
if ((vaddr == (wp->vaddr & len_mask) ||
(vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) {
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index 7295e5b..01e1117 100644
--- a/hw/i386/kvmvapic.c
+++ b/hw/i386/kvmvapic.c
@@ -408,7 +408,7 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
if (!kvm_enabled()) {
CPUClass *cc = CPU_GET_CLASS(cs);
- cpu_restore_state(env, env->mem_io_pc);
+ cpu_restore_state(env, cs->mem_io_pc);
cc->get_tb_cpu_state(cs, ¤t_pc, ¤t_cs_base,
¤t_flags);
}
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index a5c028c..d8e1af8 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -145,13 +145,6 @@ typedef struct CPUWatchpoint {
#define CPU_TEMP_BUF_NLONGS 128
#define CPU_COMMON \
/* soft mmu support */ \
- /* in order to avoid passing too many arguments to the MMIO \
- helpers, we store some rarely used information in the CPU \
- context) */ \
- uintptr_t mem_io_pc; /* host pc at which the memory was \
- accessed */ \
- target_ulong mem_io_vaddr; /* target virtual addr at which the \
- memory was accessed */ \
CPU_COMMON_TLB \
struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
\
diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h
index 5bbc56a..8b74d4f 100644
--- a/include/exec/softmmu_template.h
+++ b/include/exec/softmmu_template.h
@@ -75,16 +75,17 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
target_ulong addr,
uintptr_t retaddr)
{
+ CPUState *cpu = ENV_GET_CPU(env);
uint64_t val;
MemoryRegion *mr = iotlb_to_region(physaddr);
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
- env->mem_io_pc = retaddr;
+ cpu->mem_io_pc = retaddr;
if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) {
cpu_io_recompile(env, retaddr);
}
- env->mem_io_vaddr = addr;
+ cpu->mem_io_vaddr = addr;
io_mem_read(mr, physaddr, &val, 1 << SHIFT);
return val;
}
@@ -196,6 +197,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env,
target_ulong addr,
uintptr_t retaddr)
{
+ CPUState *cpu = ENV_GET_CPU(env);
MemoryRegion *mr = iotlb_to_region(physaddr);
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
@@ -203,8 +205,8 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env,
cpu_io_recompile(env, retaddr);
}
- env->mem_io_vaddr = addr;
- env->mem_io_pc = retaddr;
+ cpu->mem_io_vaddr = addr;
+ cpu->mem_io_pc = retaddr;
io_mem_write(mr, physaddr, val, 1 << SHIFT);
}
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 4d974f3..d79466a 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -166,6 +166,8 @@ struct kvm_run;
* @gdb_num_regs: Number of total registers accessible to GDB.
* @gdb_num_g_regs: Number of registers in GDB 'g' packets.
* @next_cpu: Next CPU sharing TB cache.
+ * @mem_io_pc: Host Program Counter at which the memory was accessed.
+ * @mem_io_vaddr: Target virtual address at which the memory was accessed.
* @kvm_fd: vCPU file descriptor for KVM.
*
* State of one CPU core or thread.
@@ -204,6 +206,12 @@ struct CPUState {
int gdb_num_g_regs;
QTAILQ_ENTRY(CPUState) node;
+ /* In order to avoid passing too many arguments to the MMIO helpers,
+ * we store some rarely used information in the CPU context.
+ */
+ uintptr_t mem_io_pc;
+ vaddr mem_io_vaddr;
+
int kvm_fd;
bool kvm_vcpu_dirty;
struct KVMState *kvm_state;
diff --git a/qom/cpu.c b/qom/cpu.c
index 9b9c2c6..bf3c913 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -198,6 +198,8 @@ static void cpu_common_reset(CPUState *cpu)
cpu->interrupt_request = 0;
cpu->current_tb = NULL;
cpu->halted = 0;
+ cpu->mem_io_pc = 0;
+ cpu->mem_io_vaddr = 0;
}
static int cpu_common_mmu_index(const CPUState *cs)
diff --git a/target-i386/helper.c b/target-i386/helper.c
index b25dafc..8c2ad94 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -1248,12 +1248,15 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
void cpu_report_tpr_access(CPUX86State *env, TPRAccess access)
{
+ X86CPU *cpu = x86_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
+
if (kvm_enabled()) {
env->tpr_access_type = access;
- cpu_interrupt(CPU(x86_env_get_cpu(env)), CPU_INTERRUPT_TPR);
+ cpu_interrupt(cs, CPU_INTERRUPT_TPR);
} else {
- cpu_restore_state(env, env->mem_io_pc);
+ cpu_restore_state(env, cs->mem_io_pc);
apic_handle_tpr_access_report(env->apic_state, env->eip, access);
}
diff --git a/translate-all.c b/translate-all.c
index 6000d4a..73ff1cf 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1062,9 +1062,9 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
if (current_tb_not_found) {
current_tb_not_found = 0;
current_tb = NULL;
- if (env->mem_io_pc) {
+ if (cpu->mem_io_pc) {
/* now we have a real cpu fault */
- current_tb = tb_find_pc(env->mem_io_pc);
+ current_tb = tb_find_pc(cpu->mem_io_pc);
}
}
if (current_tb == tb &&
@@ -1076,7 +1076,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
restore the CPU state */
current_tb_modified = 1;
- cpu_restore_state_from_tb(current_tb, env, env->mem_io_pc);
+ cpu_restore_state_from_tb(current_tb, env, cpu->mem_io_pc);
cc->get_tb_cpu_state(cpu, ¤t_pc, ¤t_cs_base,
¤t_flags);
}
@@ -1103,7 +1103,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
if (!p->first_tb) {
invalidate_page_bitmap(p);
if (is_cpu_write_access) {
- tlb_unprotect_code_phys(env, start, env->mem_io_vaddr);
+ tlb_unprotect_code_phys(env, start, cpu->mem_io_vaddr);
}
}
#endif
@@ -1389,14 +1389,15 @@ void tb_invalidate_phys_addr(hwaddr addr)
void tb_check_watchpoint(CPUArchState *env)
{
+ CPUState *cpu = ENV_GET_CPU(env);
TranslationBlock *tb;
- tb = tb_find_pc(env->mem_io_pc);
+ tb = tb_find_pc(cpu->mem_io_pc);
if (!tb) {
cpu_abort(env, "check_watchpoint: could not find TB for pc=%p",
- (void *)env->mem_io_pc);
+ (void *)cpu->mem_io_pc);
}
- cpu_restore_state_from_tb(tb, env, env->mem_io_pc);
+ cpu_restore_state_from_tb(tb, env, cpu->mem_io_pc);
tb_phys_invalidate(tb, -1);
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 06/41] cpu: Move can_do_io field from CPU_COMMON to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (4 preceding siblings ...)
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 05/41] cpu: Move mem_io_{pc, vaddr} fields from CPU_COMMON to CPUState Andreas Färber
@ 2013-09-04 9:04 ` Andreas Färber
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 07/41] cpu: Move icount_extra " Andreas Färber
` (37 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Rename can_do_io() to cpu_can_do_io() and change argument to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cpus.c | 2 +-
include/exec/cpu-defs.h | 1 -
include/exec/exec-all.h | 21 +++++++++++++--------
include/exec/gen-icount.h | 4 ++--
include/exec/softmmu_template.h | 4 ++--
include/qom/cpu.h | 2 ++
qom/cpu.c | 1 +
translate-all.c | 5 +++--
8 files changed, 24 insertions(+), 16 deletions(-)
diff --git a/cpus.c b/cpus.c
index 5acb98b..439a0d8 100644
--- a/cpus.c
+++ b/cpus.c
@@ -128,7 +128,7 @@ int64_t cpu_get_icount(void)
icount = qemu_icount;
if (cpu) {
CPUArchState *env = cpu->env_ptr;
- if (!can_do_io(env)) {
+ if (!cpu_can_do_io(cpu)) {
fprintf(stderr, "Bad clock read\n");
}
icount -= (env->icount_decr.u16.low + env->icount_extra);
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index d8e1af8..a2726c1 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -156,7 +156,6 @@ typedef struct CPUWatchpoint {
uint32_t u32; \
icount_decr_u16 u16; \
} icount_decr; \
- uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \
\
/* from this point: preserved by CPU reset */ \
/* ice debug support */ \
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index beb4149..e61b3f1 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -422,20 +422,25 @@ extern int singlestep;
/* cpu-exec.c */
extern volatile sig_atomic_t exit_request;
-/* Deterministic execution requires that IO only be performed on the last
- instruction of a TB so that interrupts take effect immediately. */
-static inline int can_do_io(CPUArchState *env)
+/**
+ * cpu_can_do_io:
+ * @cpu: The CPU for which to check IO.
+ *
+ * Deterministic execution requires that IO only be performed on the last
+ * instruction of a TB so that interrupts take effect immediately.
+ *
+ * Returns: %true if memory-mapped IO is safe, %false otherwise.
+ */
+static inline bool cpu_can_do_io(CPUState *cpu)
{
- CPUState *cpu = ENV_GET_CPU(env);
-
if (!use_icount) {
- return 1;
+ return true;
}
/* If not executing code then assume we are ok. */
if (cpu->current_tb == NULL) {
- return 1;
+ return true;
}
- return env->can_do_io != 0;
+ return cpu->can_do_io != 0;
}
#endif
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index 39a6b61..f0dace3 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec/gen-icount.h
@@ -51,14 +51,14 @@ static void gen_tb_end(TranslationBlock *tb, int num_insns)
static inline void gen_io_start(void)
{
TCGv_i32 tmp = tcg_const_i32(1);
- tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUArchState, can_do_io));
+ tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io));
tcg_temp_free_i32(tmp);
}
static inline void gen_io_end(void)
{
TCGv_i32 tmp = tcg_const_i32(0);
- tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUArchState, can_do_io));
+ tcg_gen_st_i32(tmp, cpu_env, -ENV_OFFSET + offsetof(CPUState, can_do_io));
tcg_temp_free_i32(tmp);
}
diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h
index 8b74d4f..bbfda31 100644
--- a/include/exec/softmmu_template.h
+++ b/include/exec/softmmu_template.h
@@ -81,7 +81,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
cpu->mem_io_pc = retaddr;
- if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) {
+ if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
cpu_io_recompile(env, retaddr);
}
@@ -201,7 +201,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env,
MemoryRegion *mr = iotlb_to_region(physaddr);
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
- if (mr != &io_mem_rom && mr != &io_mem_notdirty && !can_do_io(env)) {
+ if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
cpu_io_recompile(env, retaddr);
}
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index d79466a..88cbb9d 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -160,6 +160,7 @@ struct kvm_run;
* @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
* CPU and return to its top level loop.
* @singlestep_enabled: Flags for single-stepping.
+ * @can_do_io: Nonzero if memory-mapped IO is safe.
* @env_ptr: Pointer to subclass-specific CPUArchState field.
* @current_tb: Currently executing TB.
* @gdb_regs: Additional GDB registers.
@@ -220,6 +221,7 @@ struct CPUState {
/* TODO Move common fields from CPUArchState here. */
int cpu_index; /* used by alpha TCG */
uint32_t halted; /* used by alpha, cris, ppc TCG */
+ uint32_t can_do_io;
};
QTAILQ_HEAD(CPUTailQ, CPUState);
diff --git a/qom/cpu.c b/qom/cpu.c
index bf3c913..96b8771 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -200,6 +200,7 @@ static void cpu_common_reset(CPUState *cpu)
cpu->halted = 0;
cpu->mem_io_pc = 0;
cpu->mem_io_vaddr = 0;
+ cpu->can_do_io = 0;
}
static int cpu_common_mmu_index(const CPUState *cs)
diff --git a/translate-all.c b/translate-all.c
index 73ff1cf..69dea6e 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -196,6 +196,7 @@ int cpu_gen_code(CPUArchState *env, TranslationBlock *tb, int *gen_code_size_ptr
static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env,
uintptr_t searched_pc)
{
+ CPUState *cpu = ENV_GET_CPU(env);
TCGContext *s = &tcg_ctx;
int j;
uintptr_t tc_ptr;
@@ -214,7 +215,7 @@ static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env,
/* Reset the cycle counter to the start of the block. */
env->icount_decr.u16.low += tb->icount;
/* Clear the IO flag. */
- env->can_do_io = 0;
+ cpu->can_do_io = 0;
}
/* find opc index corresponding to search_pc */
@@ -1422,7 +1423,7 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask)
if (use_icount) {
env->icount_decr.u16.high = 0xffff;
- if (!can_do_io(env)
+ if (!cpu_can_do_io(cpu)
&& (mask & ~old_mask) != 0) {
cpu_abort(env, "Raised interrupt while not in I/O function");
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 07/41] cpu: Move icount_extra field from CPU_COMMON to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (5 preceding siblings ...)
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 06/41] cpu: Move can_do_io field " Andreas Färber
@ 2013-09-04 9:04 ` Andreas Färber
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 08/41] cpu: Move icount_decr " Andreas Färber
` (36 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Reset it.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cpu-exec.c | 10 +++++-----
cpus.c | 14 +++++++-------
include/exec/cpu-defs.h | 1 -
include/qom/cpu.h | 2 ++
qom/cpu.c | 1 +
5 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index c839f80..8a135ca 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -644,15 +644,15 @@ int cpu_exec(CPUArchState *env)
int insns_left;
tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
insns_left = env->icount_decr.u32;
- if (env->icount_extra && insns_left >= 0) {
+ if (cpu->icount_extra && insns_left >= 0) {
/* Refill decrementer and continue execution. */
- env->icount_extra += insns_left;
- if (env->icount_extra > 0xffff) {
+ cpu->icount_extra += insns_left;
+ if (cpu->icount_extra > 0xffff) {
insns_left = 0xffff;
} else {
- insns_left = env->icount_extra;
+ insns_left = cpu->icount_extra;
}
- env->icount_extra -= insns_left;
+ cpu->icount_extra -= insns_left;
env->icount_decr.u16.low = insns_left;
} else {
if (insns_left > 0) {
diff --git a/cpus.c b/cpus.c
index 439a0d8..318e13f 100644
--- a/cpus.c
+++ b/cpus.c
@@ -131,7 +131,7 @@ int64_t cpu_get_icount(void)
if (!cpu_can_do_io(cpu)) {
fprintf(stderr, "Bad clock read\n");
}
- icount -= (env->icount_decr.u16.low + env->icount_extra);
+ icount -= (env->icount_decr.u16.low + cpu->icount_extra);
}
return qemu_icount_bias + (icount << icount_time_shift);
}
@@ -1147,6 +1147,7 @@ int vm_stop_force_state(RunState state)
static int tcg_cpu_exec(CPUArchState *env)
{
+ CPUState *cpu = ENV_GET_CPU(env);
int ret;
#ifdef CONFIG_PROFILER
int64_t ti;
@@ -1159,9 +1160,9 @@ static int tcg_cpu_exec(CPUArchState *env)
int64_t count;
int64_t deadline;
int decr;
- qemu_icount -= (env->icount_decr.u16.low + env->icount_extra);
+ qemu_icount -= (env->icount_decr.u16.low + cpu->icount_extra);
env->icount_decr.u16.low = 0;
- env->icount_extra = 0;
+ cpu->icount_extra = 0;
deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL);
/* Maintain prior (possibly buggy) behaviour where if no deadline
@@ -1178,7 +1179,7 @@ static int tcg_cpu_exec(CPUArchState *env)
decr = (count > 0xffff) ? 0xffff : count;
count -= decr;
env->icount_decr.u16.low = decr;
- env->icount_extra = count;
+ cpu->icount_extra = count;
}
ret = cpu_exec(env);
#ifdef CONFIG_PROFILER
@@ -1187,10 +1188,9 @@ static int tcg_cpu_exec(CPUArchState *env)
if (use_icount) {
/* Fold pending instructions back into the
instruction counter, and clear the interrupt flag. */
- qemu_icount -= (env->icount_decr.u16.low
- + env->icount_extra);
+ qemu_icount -= (env->icount_decr.u16.low + cpu->icount_extra);
env->icount_decr.u32 = 0;
- env->icount_extra = 0;
+ cpu->icount_extra = 0;
}
return ret;
}
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index a2726c1..9f0c0f2 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -148,7 +148,6 @@ typedef struct CPUWatchpoint {
CPU_COMMON_TLB \
struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
\
- int64_t icount_extra; /* Instructions until next timer event. */ \
/* Number of cycles left, with interrupt flag in high bit. \
This allows a single read-compare-cbranch-write sequence to test \
for both decrementer underflow and exceptions. */ \
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 88cbb9d..fdf7ae5 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -160,6 +160,7 @@ struct kvm_run;
* @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
* CPU and return to its top level loop.
* @singlestep_enabled: Flags for single-stepping.
+ * @icount_extra: Instructions until next timer event.
* @can_do_io: Nonzero if memory-mapped IO is safe.
* @env_ptr: Pointer to subclass-specific CPUArchState field.
* @current_tb: Currently executing TB.
@@ -199,6 +200,7 @@ struct CPUState {
volatile sig_atomic_t tcg_exit_req;
uint32_t interrupt_request;
int singlestep_enabled;
+ int64_t icount_extra;
void *env_ptr; /* CPUArchState */
struct TranslationBlock *current_tb;
diff --git a/qom/cpu.c b/qom/cpu.c
index 96b8771..fe0d2e7 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -200,6 +200,7 @@ static void cpu_common_reset(CPUState *cpu)
cpu->halted = 0;
cpu->mem_io_pc = 0;
cpu->mem_io_vaddr = 0;
+ cpu->icount_extra = 0;
cpu->can_do_io = 0;
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 08/41] cpu: Move icount_decr field from CPU_COMMON to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (6 preceding siblings ...)
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 07/41] cpu: Move icount_extra " Andreas Färber
@ 2013-09-04 9:04 ` Andreas Färber
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 09/41] cpu: Move tb_jmp_cache " Andreas Färber
` (35 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cpu-exec.c | 4 ++--
cpus.c | 13 ++++++-------
include/exec/cpu-defs.h | 20 --------------------
include/exec/gen-icount.h | 6 ++++--
include/qom/cpu.h | 19 +++++++++++++++++++
qom/cpu.c | 1 +
translate-all.c | 15 ++++++++-------
7 files changed, 40 insertions(+), 38 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 8a135ca..b164662 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -643,7 +643,7 @@ int cpu_exec(CPUArchState *env)
/* Instruction counter expired. */
int insns_left;
tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
- insns_left = env->icount_decr.u32;
+ insns_left = cpu->icount_decr.u32;
if (cpu->icount_extra && insns_left >= 0) {
/* Refill decrementer and continue execution. */
cpu->icount_extra += insns_left;
@@ -653,7 +653,7 @@ int cpu_exec(CPUArchState *env)
insns_left = cpu->icount_extra;
}
cpu->icount_extra -= insns_left;
- env->icount_decr.u16.low = insns_left;
+ cpu->icount_decr.u16.low = insns_left;
} else {
if (insns_left > 0) {
/* Execute remaining instructions. */
diff --git a/cpus.c b/cpus.c
index 318e13f..fd1fe1c 100644
--- a/cpus.c
+++ b/cpus.c
@@ -127,11 +127,10 @@ int64_t cpu_get_icount(void)
icount = qemu_icount;
if (cpu) {
- CPUArchState *env = cpu->env_ptr;
if (!cpu_can_do_io(cpu)) {
fprintf(stderr, "Bad clock read\n");
}
- icount -= (env->icount_decr.u16.low + cpu->icount_extra);
+ icount -= (cpu->icount_decr.u16.low + cpu->icount_extra);
}
return qemu_icount_bias + (icount << icount_time_shift);
}
@@ -1160,8 +1159,8 @@ static int tcg_cpu_exec(CPUArchState *env)
int64_t count;
int64_t deadline;
int decr;
- qemu_icount -= (env->icount_decr.u16.low + cpu->icount_extra);
- env->icount_decr.u16.low = 0;
+ qemu_icount -= (cpu->icount_decr.u16.low + cpu->icount_extra);
+ cpu->icount_decr.u16.low = 0;
cpu->icount_extra = 0;
deadline = qemu_clock_deadline_ns_all(QEMU_CLOCK_VIRTUAL);
@@ -1178,7 +1177,7 @@ static int tcg_cpu_exec(CPUArchState *env)
qemu_icount += count;
decr = (count > 0xffff) ? 0xffff : count;
count -= decr;
- env->icount_decr.u16.low = decr;
+ cpu->icount_decr.u16.low = decr;
cpu->icount_extra = count;
}
ret = cpu_exec(env);
@@ -1188,8 +1187,8 @@ static int tcg_cpu_exec(CPUArchState *env)
if (use_icount) {
/* Fold pending instructions back into the
instruction counter, and clear the interrupt flag. */
- qemu_icount -= (env->icount_decr.u16.low + cpu->icount_extra);
- env->icount_decr.u32 = 0;
+ qemu_icount -= (cpu->icount_decr.u16.low + cpu->icount_extra);
+ cpu->icount_decr.u32 = 0;
cpu->icount_extra = 0;
}
return ret;
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 9f0c0f2..b301ac2 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -117,18 +117,6 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
#endif
-#ifdef HOST_WORDS_BIGENDIAN
-typedef struct icount_decr_u16 {
- uint16_t high;
- uint16_t low;
-} icount_decr_u16;
-#else
-typedef struct icount_decr_u16 {
- uint16_t low;
- uint16_t high;
-} icount_decr_u16;
-#endif
-
typedef struct CPUBreakpoint {
target_ulong pc;
int flags; /* BP_* */
@@ -148,14 +136,6 @@ typedef struct CPUWatchpoint {
CPU_COMMON_TLB \
struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
\
- /* Number of cycles left, with interrupt flag in high bit. \
- This allows a single read-compare-cbranch-write sequence to test \
- for both decrementer underflow and exceptions. */ \
- union { \
- uint32_t u32; \
- icount_decr_u16 u16; \
- } icount_decr; \
- \
/* from this point: preserved by CPU reset */ \
/* ice debug support */ \
QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index f0dace3..da53395 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec/gen-icount.h
@@ -26,13 +26,15 @@ static inline void gen_tb_start(void)
icount_label = gen_new_label();
count = tcg_temp_local_new_i32();
- tcg_gen_ld_i32(count, cpu_env, offsetof(CPUArchState, icount_decr.u32));
+ tcg_gen_ld_i32(count, cpu_env,
+ -ENV_OFFSET + offsetof(CPUState, icount_decr.u32));
/* This is a horrid hack to allow fixing up the value later. */
icount_arg = tcg_ctx.gen_opparam_ptr + 1;
tcg_gen_subi_i32(count, count, 0xdeadbeef);
tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, icount_label);
- tcg_gen_st16_i32(count, cpu_env, offsetof(CPUArchState, icount_decr.u16.low));
+ tcg_gen_st16_i32(count, cpu_env,
+ -ENV_OFFSET + offsetof(CPUState, icount_decr.u16.low));
tcg_temp_free_i32(count);
}
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index fdf7ae5..e2ab371 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -141,6 +141,18 @@ typedef struct CPUClass {
const char *gdb_core_xml_file;
} CPUClass;
+#ifdef HOST_WORDS_BIGENDIAN
+typedef struct icount_decr_u16 {
+ uint16_t high;
+ uint16_t low;
+} icount_decr_u16;
+#else
+typedef struct icount_decr_u16 {
+ uint16_t low;
+ uint16_t high;
+} icount_decr_u16;
+#endif
+
struct KVMState;
struct kvm_run;
@@ -161,6 +173,9 @@ struct kvm_run;
* CPU and return to its top level loop.
* @singlestep_enabled: Flags for single-stepping.
* @icount_extra: Instructions until next timer event.
+ * @icount_decr: Number of cycles left, with interrupt flag in high bit.
+ * This allows a single read-compare-cbranch-write sequence to test
+ * for both decrementer underflow and exceptions.
* @can_do_io: Nonzero if memory-mapped IO is safe.
* @env_ptr: Pointer to subclass-specific CPUArchState field.
* @current_tb: Currently executing TB.
@@ -223,6 +238,10 @@ struct CPUState {
/* TODO Move common fields from CPUArchState here. */
int cpu_index; /* used by alpha TCG */
uint32_t halted; /* used by alpha, cris, ppc TCG */
+ union {
+ uint32_t u32;
+ icount_decr_u16 u16;
+ } icount_decr;
uint32_t can_do_io;
};
diff --git a/qom/cpu.c b/qom/cpu.c
index fe0d2e7..192a9f1 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -201,6 +201,7 @@ static void cpu_common_reset(CPUState *cpu)
cpu->mem_io_pc = 0;
cpu->mem_io_vaddr = 0;
cpu->icount_extra = 0;
+ cpu->icount_decr.u32 = 0;
cpu->can_do_io = 0;
}
diff --git a/translate-all.c b/translate-all.c
index 69dea6e..bbf911e 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -213,7 +213,7 @@ static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env,
if (use_icount) {
/* Reset the cycle counter to the start of the block. */
- env->icount_decr.u16.low += tb->icount;
+ cpu->icount_decr.u16.low += tb->icount;
/* Clear the IO flag. */
cpu->can_do_io = 0;
}
@@ -238,7 +238,7 @@ static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env,
while (s->gen_opc_instr_start[j] == 0) {
j--;
}
- env->icount_decr.u16.low -= s->gen_opc_icount[j];
+ cpu->icount_decr.u16.low -= s->gen_opc_icount[j];
restore_state_to_opc(env, tb, j);
@@ -1422,7 +1422,7 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask)
}
if (use_icount) {
- env->icount_decr.u16.high = 0xffff;
+ cpu->icount_decr.u16.high = 0xffff;
if (!cpu_can_do_io(cpu)
&& (mask & ~old_mask) != 0) {
cpu_abort(env, "Raised interrupt while not in I/O function");
@@ -1438,6 +1438,7 @@ CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt;
must be at the end of the TB */
void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr)
{
+ CPUState *cpu = ENV_GET_CPU(env);
TranslationBlock *tb;
uint32_t n, cflags;
target_ulong pc, cs_base;
@@ -1448,11 +1449,11 @@ void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr)
cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p",
(void *)retaddr);
}
- n = env->icount_decr.u16.low + tb->icount;
+ n = cpu->icount_decr.u16.low + tb->icount;
cpu_restore_state_from_tb(tb, env, retaddr);
/* Calculate how many instructions had been executed before the fault
occurred. */
- n = n - env->icount_decr.u16.low;
+ n = n - cpu->icount_decr.u16.low;
/* Generate a new TB ending on the I/O insn. */
n++;
/* On MIPS and SH, delay slot instructions can only be restarted if
@@ -1462,14 +1463,14 @@ void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr)
#if defined(TARGET_MIPS)
if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) {
env->active_tc.PC -= 4;
- env->icount_decr.u16.low++;
+ cpu->icount_decr.u16.low++;
env->hflags &= ~MIPS_HFLAG_BMASK;
}
#elif defined(TARGET_SH4)
if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
&& n > 1) {
env->pc -= 2;
- env->icount_decr.u16.low++;
+ cpu->icount_decr.u16.low++;
env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
}
#endif
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 09/41] cpu: Move tb_jmp_cache field from CPU_COMMON to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (7 preceding siblings ...)
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 08/41] cpu: Move icount_decr " Andreas Färber
@ 2013-09-04 9:04 ` Andreas Färber
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 10/41] cpu: Move jmp_env " Andreas Färber
` (34 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Clear it on reset.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cpu-exec.c | 5 +++--
cputlb.c | 2 +-
include/exec/cpu-defs.h | 4 ----
include/qom/cpu.h | 4 ++++
qom/cpu.c | 1 +
translate-all.c | 15 ++++++---------
6 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index b164662..31331dc 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -100,6 +100,7 @@ static TranslationBlock *tb_find_slow(CPUArchState *env,
target_ulong cs_base,
uint64_t flags)
{
+ CPUState *cpu = ENV_GET_CPU(env);
TranslationBlock *tb, **ptb1;
unsigned int h;
tb_page_addr_t phys_pc, phys_page1;
@@ -147,7 +148,7 @@ static TranslationBlock *tb_find_slow(CPUArchState *env,
tcg_ctx.tb_ctx.tb_phys_hash[h] = tb;
}
/* we add the TB in the virtual pc hash table */
- env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
+ cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
return tb;
}
@@ -163,7 +164,7 @@ static inline TranslationBlock *tb_find_fast(CPUArchState *env)
always be the same before a given translated block
is executed. */
cc->get_tb_cpu_state(cpu, &pc, &cs_base, &flags);
- tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
+ tb = cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
tb->flags != flags)) {
tb = tb_find_slow(env, pc, cs_base, flags);
diff --git a/cputlb.c b/cputlb.c
index 85a028f..e8131d8 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -72,7 +72,7 @@ void tlb_flush(CPUArchState *env, int flush_global)
}
}
- memset(env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof (void *));
+ memset(cpu->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof(void *));
env->tlb_flush_addr = -1;
env->tlb_flush_mask = 0;
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index b301ac2..c67c98a 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -60,9 +60,6 @@ typedef uint64_t target_ulong;
#define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */
#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
-#define TB_JMP_CACHE_BITS 12
-#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
-
/* Only the bottom TB_JMP_PAGE_BITS of the jump cache hash bits vary for
addresses on the same page. The top bits are the same. This allows
TLB invalidation to quickly clear a subset of the hash table. */
@@ -134,7 +131,6 @@ typedef struct CPUWatchpoint {
#define CPU_COMMON \
/* soft mmu support */ \
CPU_COMMON_TLB \
- struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
\
/* from this point: preserved by CPU reset */ \
/* ice debug support */ \
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index e2ab371..568cc12 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -156,6 +156,9 @@ typedef struct icount_decr_u16 {
struct KVMState;
struct kvm_run;
+#define TB_JMP_CACHE_BITS 12
+#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
+
/**
* CPUState:
* @cpu_index: CPU index (informative).
@@ -219,6 +222,7 @@ struct CPUState {
void *env_ptr; /* CPUArchState */
struct TranslationBlock *current_tb;
+ struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
struct GDBRegisterState *gdb_regs;
int gdb_num_regs;
int gdb_num_g_regs;
diff --git a/qom/cpu.c b/qom/cpu.c
index 192a9f1..69f26b0 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -203,6 +203,7 @@ static void cpu_common_reset(CPUState *cpu)
cpu->icount_extra = 0;
cpu->icount_decr.u32 = 0;
cpu->can_do_io = 0;
+ memset(cpu->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof(void *));
}
static int cpu_common_mmu_index(const CPUState *cs)
diff --git a/translate-all.c b/translate-all.c
index bbf911e..ef34936 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -698,9 +698,7 @@ void tb_flush(CPUArchState *env1)
tcg_ctx.tb_ctx.nb_tbs = 0;
CPU_FOREACH(cpu) {
- CPUArchState *env = cpu->env_ptr;
-
- memset(env->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof(void *));
+ memset(cpu->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof(void *));
}
memset(tcg_ctx.tb_ctx.tb_phys_hash, 0,
@@ -852,10 +850,8 @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
/* remove the TB from the hash list */
h = tb_jmp_cache_hash_func(tb->pc);
CPU_FOREACH(cpu) {
- CPUArchState *env = cpu->env_ptr;
-
- if (env->tb_jmp_cache[h] == tb) {
- env->tb_jmp_cache[h] = NULL;
+ if (cpu->tb_jmp_cache[h] == tb) {
+ cpu->tb_jmp_cache[h] = NULL;
}
}
@@ -1497,16 +1493,17 @@ void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr)
void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr)
{
+ CPUState *cpu = ENV_GET_CPU(env);
unsigned int i;
/* Discard jump cache entries for any tb which might potentially
overlap the flushed page. */
i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE);
- memset(&env->tb_jmp_cache[i], 0,
+ memset(&cpu->tb_jmp_cache[i], 0,
TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
i = tb_jmp_cache_hash_page(addr);
- memset(&env->tb_jmp_cache[i], 0,
+ memset(&cpu->tb_jmp_cache[i], 0,
TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *));
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 10/41] cpu: Move jmp_env field from CPU_COMMON to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (8 preceding siblings ...)
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 09/41] cpu: Move tb_jmp_cache " Andreas Färber
@ 2013-09-04 9:04 ` Andreas Färber
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 11/41] cpu: Move exception_index " Andreas Färber
` (33 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cpu-exec.c | 8 +++++---
include/exec/cpu-defs.h | 2 --
include/qom/cpu.h | 2 ++
user-exec.c | 3 ++-
4 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 31331dc..39e4f8b 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -28,7 +28,7 @@ void cpu_loop_exit(CPUArchState *env)
CPUState *cpu = ENV_GET_CPU(env);
cpu->current_tb = NULL;
- siglongjmp(env->jmp_env, 1);
+ siglongjmp(cpu->jmp_env, 1);
}
/* exit the current TB from a signal handler. The host registers are
@@ -37,10 +37,12 @@ void cpu_loop_exit(CPUArchState *env)
#if defined(CONFIG_SOFTMMU)
void cpu_resume_from_signal(CPUArchState *env, void *puc)
{
+ CPUState *cpu = ENV_GET_CPU(env);
+
/* XXX: restore cpu registers saved in host registers */
env->exception_index = -1;
- siglongjmp(env->jmp_env, 1);
+ siglongjmp(cpu->jmp_env, 1);
}
#endif
@@ -264,7 +266,7 @@ int cpu_exec(CPUArchState *env)
/* prepare setjmp context for exception handling */
for(;;) {
- if (sigsetjmp(env->jmp_env, 0) == 0) {
+ if (sigsetjmp(cpu->jmp_env, 0) == 0) {
/* if an exception is pending, we execute it here */
if (env->exception_index >= 0) {
if (env->exception_index >= EXCP_INTERRUPT) {
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index c67c98a..d000a5e 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -24,7 +24,6 @@
#endif
#include "config.h"
-#include <setjmp.h>
#include <inttypes.h>
#include "qemu/osdep.h"
#include "qemu/queue.h"
@@ -140,7 +139,6 @@ typedef struct CPUWatchpoint {
CPUWatchpoint *watchpoint_hit; \
\
/* Core interrupt code */ \
- sigjmp_buf jmp_env; \
int exception_index; \
\
/* user data */ \
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 568cc12..288ffa9 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -21,6 +21,7 @@
#define QEMU_CPU_H
#include <signal.h>
+#include <setjmp.h>
#include "hw/qdev-core.h"
#include "exec/hwaddr.h"
#include "qemu/queue.h"
@@ -219,6 +220,7 @@ struct CPUState {
uint32_t interrupt_request;
int singlestep_enabled;
int64_t icount_extra;
+ sigjmp_buf jmp_env;
void *env_ptr; /* CPUArchState */
struct TranslationBlock *current_tb;
diff --git a/user-exec.c b/user-exec.c
index d850d41..dec636e 100644
--- a/user-exec.c
+++ b/user-exec.c
@@ -52,6 +52,7 @@ static void exception_action(CPUArchState *env1)
*/
void cpu_resume_from_signal(CPUArchState *env1, void *puc)
{
+ CPUState *cpu = ENV_GET_CPU(env1);
#ifdef __linux__
struct ucontext *uc = puc;
#elif defined(__OpenBSD__)
@@ -71,7 +72,7 @@ void cpu_resume_from_signal(CPUArchState *env1, void *puc)
#endif
}
env1->exception_index = -1;
- siglongjmp(env1->jmp_env, 1);
+ siglongjmp(cpu->jmp_env, 1);
}
/* 'pc' is the host PC at which the exception was raised. 'address' is
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 11/41] cpu: Move exception_index field from CPU_COMMON to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (9 preceding siblings ...)
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 10/41] cpu: Move jmp_env " Andreas Färber
@ 2013-09-04 9:04 ` Andreas Färber
2013-09-04 12:47 ` Jia Liu
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 12/41] cpu: Move cpu_copy() into linux-user Andreas Färber
` (32 subsequent siblings)
43 siblings, 1 reply; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:04 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Anthony Green, Riku Voipio,
Alexander Graf, Blue Swirl, Max Filippov, Michael Walle,
open list:e500, Paul Brook, Scott Wood, Edgar E. Iglesias,
Guan Xuetao, Andreas Färber, Aurelien Jarno,
Richard Henderson
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cpu-exec.c | 50 +++++++++++++++++++++---------------------
exec.c | 2 +-
hw/ppc/e500.c | 3 +--
hw/ppc/ppce500_spin.c | 2 +-
hw/ppc/spapr_hcall.c | 2 +-
hw/s390x/s390-virtio.c | 8 +++----
include/exec/cpu-defs.h | 3 ---
include/qom/cpu.h | 1 +
linux-user/signal.c | 7 +++---
target-alpha/helper.c | 18 ++++++++++-----
target-alpha/mem_helper.c | 4 +++-
target-arm/helper.c | 25 ++++++++++-----------
target-arm/op_helper.c | 16 +++++++++-----
target-cris/helper.c | 18 +++++++--------
target-cris/op_helper.c | 6 +++--
target-i386/excp_helper.c | 4 +++-
target-i386/helper.c | 6 ++---
target-i386/mem_helper.c | 5 +++--
target-i386/misc_helper.c | 6 +++--
target-i386/seg_helper.c | 8 ++++---
target-i386/svm_helper.c | 13 ++++++-----
target-lm32/helper.c | 12 +++++-----
target-lm32/op_helper.c | 6 +++--
target-m68k/helper.c | 2 +-
target-m68k/op_helper.c | 22 +++++++++----------
target-m68k/qregs.def | 1 -
target-m68k/translate.c | 5 +++++
target-microblaze/helper.c | 16 ++++++--------
target-microblaze/op_helper.c | 4 +++-
target-mips/helper.c | 31 ++++++++++++++------------
target-mips/op_helper.c | 9 +++++---
target-mips/translate.c | 4 +---
target-moxie/helper.c | 21 ++++++++++--------
target-openrisc/cpu.c | 2 +-
target-openrisc/exception.c | 4 +++-
target-openrisc/interrupt.c | 27 ++++++++++++-----------
target-openrisc/mmu.c | 3 ++-
target-ppc/excp_helper.c | 19 +++++++++-------
target-ppc/fpu_helper.c | 26 +++++++++++++++-------
target-ppc/mmu-hash32.c | 24 ++++++++++----------
target-ppc/mmu-hash64.c | 15 +++++++------
target-ppc/mmu_helper.c | 43 ++++++++++++++++++------------------
target-ppc/translate_init.c | 2 +-
target-ppc/user_only_helper.c | 2 +-
target-s390x/helper.c | 39 ++++++++++++++++-----------------
target-s390x/mem_helper.c | 9 ++++----
target-s390x/misc_helper.c | 15 +++++++++----
target-sh4/helper.c | 51 +++++++++++++++++++++----------------------
target-sh4/op_helper.c | 4 +++-
target-sparc/helper.c | 10 ++++++---
target-sparc/int32_helper.c | 8 +++----
target-sparc/int64_helper.c | 6 ++---
target-sparc/ldst_helper.c | 3 ++-
target-sparc/mmu_helper.c | 22 +++++++++----------
target-unicore32/op_helper.c | 4 +++-
target-unicore32/softmmu.c | 8 +++----
target-xtensa/helper.c | 20 +++++++++--------
target-xtensa/op_helper.c | 4 +++-
user-exec.c | 6 +++--
59 files changed, 393 insertions(+), 323 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 39e4f8b..0081eaf 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -41,7 +41,7 @@ void cpu_resume_from_signal(CPUArchState *env, void *puc)
/* XXX: restore cpu registers saved in host registers */
- env->exception_index = -1;
+ cpu->exception_index = -1;
siglongjmp(cpu->jmp_env, 1);
}
#endif
@@ -262,16 +262,16 @@ int cpu_exec(CPUArchState *env)
#else
#error unsupported target CPU
#endif
- env->exception_index = -1;
+ cpu->exception_index = -1;
/* prepare setjmp context for exception handling */
for(;;) {
if (sigsetjmp(cpu->jmp_env, 0) == 0) {
/* if an exception is pending, we execute it here */
- if (env->exception_index >= 0) {
- if (env->exception_index >= EXCP_INTERRUPT) {
+ if (cpu->exception_index >= 0) {
+ if (cpu->exception_index >= EXCP_INTERRUPT) {
/* exit request from the cpu execution loop */
- ret = env->exception_index;
+ ret = cpu->exception_index;
if (ret == EXCP_DEBUG) {
cpu_handle_debug_exception(env);
}
@@ -284,11 +284,11 @@ int cpu_exec(CPUArchState *env)
#if defined(TARGET_I386)
cc->do_interrupt(cpu);
#endif
- ret = env->exception_index;
+ ret = cpu->exception_index;
break;
#else
cc->do_interrupt(cpu);
- env->exception_index = -1;
+ cpu->exception_index = -1;
#endif
}
}
@@ -303,7 +303,7 @@ int cpu_exec(CPUArchState *env)
}
if (interrupt_request & CPU_INTERRUPT_DEBUG) {
cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
- env->exception_index = EXCP_DEBUG;
+ cpu->exception_index = EXCP_DEBUG;
cpu_loop_exit(env);
}
#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
@@ -312,7 +312,7 @@ int cpu_exec(CPUArchState *env)
if (interrupt_request & CPU_INTERRUPT_HALT) {
cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
cpu->halted = 1;
- env->exception_index = EXCP_HLT;
+ cpu->exception_index = EXCP_HLT;
cpu_loop_exit(env);
}
#endif
@@ -327,7 +327,7 @@ int cpu_exec(CPUArchState *env)
cpu_svm_check_intercept_param(env, SVM_EXIT_INIT,
0);
do_cpu_init(x86_env_get_cpu(env));
- env->exception_index = EXCP_HALTED;
+ cpu->exception_index = EXCP_HALTED;
cpu_loop_exit(env);
} else if (interrupt_request & CPU_INTERRUPT_SIPI) {
do_cpu_sipi(x86_env_get_cpu(env));
@@ -396,7 +396,7 @@ int cpu_exec(CPUArchState *env)
#elif defined(TARGET_LM32)
if ((interrupt_request & CPU_INTERRUPT_HARD)
&& (env->ie & IE_IE)) {
- env->exception_index = EXCP_IRQ;
+ cpu->exception_index = EXCP_IRQ;
cc->do_interrupt(cpu);
next_tb = 0;
}
@@ -405,7 +405,7 @@ int cpu_exec(CPUArchState *env)
&& (env->sregs[SR_MSR] & MSR_IE)
&& !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
&& !(env->iflags & (D_FLAG | IMM_FLAG))) {
- env->exception_index = EXCP_IRQ;
+ cpu->exception_index = EXCP_IRQ;
cc->do_interrupt(cpu);
next_tb = 0;
}
@@ -413,7 +413,7 @@ int cpu_exec(CPUArchState *env)
if ((interrupt_request & CPU_INTERRUPT_HARD) &&
cpu_mips_hw_interrupts_pending(env)) {
/* Raise it */
- env->exception_index = EXCP_EXT_INTERRUPT;
+ cpu->exception_index = EXCP_EXT_INTERRUPT;
env->error_code = 0;
cc->do_interrupt(cpu);
next_tb = 0;
@@ -430,7 +430,7 @@ int cpu_exec(CPUArchState *env)
idx = EXCP_TICK;
}
if (idx >= 0) {
- env->exception_index = idx;
+ cpu->exception_index = idx;
cc->do_interrupt(cpu);
next_tb = 0;
}
@@ -445,7 +445,7 @@ int cpu_exec(CPUArchState *env)
if (((type == TT_EXTINT) &&
cpu_pil_allowed(env, pil)) ||
type != TT_EXTINT) {
- env->exception_index = env->interrupt_index;
+ cpu->exception_index = env->interrupt_index;
cc->do_interrupt(cpu);
next_tb = 0;
}
@@ -454,7 +454,7 @@ int cpu_exec(CPUArchState *env)
#elif defined(TARGET_ARM)
if (interrupt_request & CPU_INTERRUPT_FIQ
&& !(env->uncached_cpsr & CPSR_F)) {
- env->exception_index = EXCP_FIQ;
+ cpu->exception_index = EXCP_FIQ;
cc->do_interrupt(cpu);
next_tb = 0;
}
@@ -470,14 +470,14 @@ int cpu_exec(CPUArchState *env)
if (interrupt_request & CPU_INTERRUPT_HARD
&& ((IS_M(env) && env->regs[15] < 0xfffffff0)
|| !(env->uncached_cpsr & CPSR_I))) {
- env->exception_index = EXCP_IRQ;
+ cpu->exception_index = EXCP_IRQ;
cc->do_interrupt(cpu);
next_tb = 0;
}
#elif defined(TARGET_UNICORE32)
if (interrupt_request & CPU_INTERRUPT_HARD
&& !(env->uncached_asr & ASR_I)) {
- env->exception_index = UC32_EXCP_INTR;
+ cpu->exception_index = UC32_EXCP_INTR;
cc->do_interrupt(cpu);
next_tb = 0;
}
@@ -512,7 +512,7 @@ int cpu_exec(CPUArchState *env)
}
}
if (idx >= 0) {
- env->exception_index = idx;
+ cpu->exception_index = idx;
env->error_code = 0;
cc->do_interrupt(cpu);
next_tb = 0;
@@ -522,7 +522,7 @@ int cpu_exec(CPUArchState *env)
if (interrupt_request & CPU_INTERRUPT_HARD
&& (env->pregs[PR_CCS] & I_FLAG)
&& !env->locked_irq) {
- env->exception_index = EXCP_IRQ;
+ cpu->exception_index = EXCP_IRQ;
cc->do_interrupt(cpu);
next_tb = 0;
}
@@ -534,7 +534,7 @@ int cpu_exec(CPUArchState *env)
m_flag_archval = M_FLAG_V32;
}
if ((env->pregs[PR_CCS] & m_flag_archval)) {
- env->exception_index = EXCP_NMI;
+ cpu->exception_index = EXCP_NMI;
cc->do_interrupt(cpu);
next_tb = 0;
}
@@ -548,7 +548,7 @@ int cpu_exec(CPUArchState *env)
hardware doesn't rely on this, so we
provide/save the vector when the interrupt is
first signalled. */
- env->exception_index = env->pending_vector;
+ cpu->exception_index = env->pending_vector;
do_interrupt_m68k_hardirq(env);
next_tb = 0;
}
@@ -560,7 +560,7 @@ int cpu_exec(CPUArchState *env)
}
#elif defined(TARGET_XTENSA)
if (interrupt_request & CPU_INTERRUPT_HARD) {
- env->exception_index = EXC_IRQ;
+ cpu->exception_index = EXC_IRQ;
cc->do_interrupt(cpu);
next_tb = 0;
}
@@ -576,7 +576,7 @@ int cpu_exec(CPUArchState *env)
}
if (unlikely(cpu->exit_request)) {
cpu->exit_request = 0;
- env->exception_index = EXCP_INTERRUPT;
+ cpu->exception_index = EXCP_INTERRUPT;
cpu_loop_exit(env);
}
#if defined(DEBUG_DISAS)
@@ -662,7 +662,7 @@ int cpu_exec(CPUArchState *env)
/* Execute remaining instructions. */
cpu_exec_nocache(env, insns_left, tb);
}
- env->exception_index = EXCP_INTERRUPT;
+ cpu->exception_index = EXCP_INTERRUPT;
next_tb = 0;
cpu_loop_exit(env);
}
diff --git a/exec.c b/exec.c
index 00c44ea..508f1e2 100644
--- a/exec.c
+++ b/exec.c
@@ -1502,7 +1502,7 @@ static void check_watchpoint(int offset, int len_mask, int flags)
env->watchpoint_hit = wp;
tb_check_watchpoint(env);
if (wp->flags & BP_STOP_BEFORE_ACCESS) {
- env->exception_index = EXCP_DEBUG;
+ cpu->exception_index = EXCP_DEBUG;
cpu_loop_exit(env);
} else {
cc->get_tb_cpu_state(cpu, &pc, &cs_base, &cpu_flags);
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index cfdd84b..2d1d478 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -468,14 +468,13 @@ static void ppce500_cpu_reset_sec(void *opaque)
{
PowerPCCPU *cpu = opaque;
CPUState *cs = CPU(cpu);
- CPUPPCState *env = &cpu->env;
cpu_reset(cs);
/* Secondary CPU starts in halted state for now. Needs to change when
implementing non-kernel boot. */
cs->halted = 1;
- env->exception_index = EXCP_HLT;
+ cs->exception_index = EXCP_HLT;
}
static void ppce500_cpu_reset(void *opaque)
diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c
index 78b23fa..f9fdc8c 100644
--- a/hw/ppc/ppce500_spin.c
+++ b/hw/ppc/ppce500_spin.c
@@ -117,7 +117,7 @@ static void spin_kick(void *data)
mmubooke_create_initial_mapping(env, 0, map_start, map_size);
cpu->halted = 0;
- env->exception_index = -1;
+ cpu->exception_index = -1;
cpu->stopped = false;
qemu_cpu_kick(cpu);
}
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index f10ba8a..d4aa4ea 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -511,7 +511,7 @@ static target_ulong h_cede(PowerPCCPU *cpu, sPAPREnvironment *spapr,
hreg_compute_hflags(env);
if (!cpu_has_work(cs)) {
cs->halted = 1;
- env->exception_index = EXCP_HLT;
+ cs->exception_index = EXCP_HLT;
cs->exit_request = 1;
}
return H_SUCCESS;
diff --git a/hw/s390x/s390-virtio.c b/hw/s390x/s390-virtio.c
index 7adf92a..393f3c8 100644
--- a/hw/s390x/s390-virtio.c
+++ b/hw/s390x/s390-virtio.c
@@ -134,25 +134,23 @@ static unsigned s390_running_cpus;
void s390_add_running_cpu(S390CPU *cpu)
{
CPUState *cs = CPU(cpu);
- CPUS390XState *env = &cpu->env;
if (cs->halted) {
s390_running_cpus++;
cs->halted = 0;
- env->exception_index = -1;
+ cs->exception_index = -1;
}
}
unsigned s390_del_running_cpu(S390CPU *cpu)
{
CPUState *cs = CPU(cpu);
- CPUS390XState *env = &cpu->env;
if (cs->halted == 0) {
assert(s390_running_cpus >= 1);
s390_running_cpus--;
cs->halted = 1;
- env->exception_index = EXCP_HLT;
+ cs->exception_index = EXCP_HLT;
}
return s390_running_cpus;
}
@@ -195,7 +193,7 @@ void s390_init_cpus(const char *cpu_model, uint8_t *storage_keys)
ipi_states[i] = cpu;
cs->halted = 1;
- cpu->env.exception_index = EXCP_HLT;
+ cs->exception_index = EXCP_HLT;
cpu->env.storage_keys = storage_keys;
}
}
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index d000a5e..6801968 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -138,9 +138,6 @@ typedef struct CPUWatchpoint {
QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
CPUWatchpoint *watchpoint_hit; \
\
- /* Core interrupt code */ \
- int exception_index; \
- \
/* user data */ \
void *opaque; \
\
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 288ffa9..8191a80 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -249,6 +249,7 @@ struct CPUState {
icount_decr_u16 u16;
} icount_decr;
uint32_t can_do_io;
+ int32_t exception_index; /* used by m68k TCG */
};
QTAILQ_HEAD(CPUTailQ, CPUState);
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 23d65da..6e51519 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -773,8 +773,9 @@ static int
setup_sigcontext(struct target_sigcontext *sc, struct target_fpstate *fpstate,
CPUX86State *env, abi_ulong mask, abi_ulong fpstate_addr)
{
- int err = 0;
- uint16_t magic;
+ CPUState *cs = CPU(x86_env_get_cpu(env));
+ int err = 0;
+ uint16_t magic;
/* already locked in setup_frame() */
err |= __put_user(env->segs[R_GS].selector, (unsigned int *)&sc->gs);
@@ -789,7 +790,7 @@ setup_sigcontext(struct target_sigcontext *sc, struct target_fpstate *fpstate,
err |= __put_user(env->regs[R_EDX], &sc->edx);
err |= __put_user(env->regs[R_ECX], &sc->ecx);
err |= __put_user(env->regs[R_EAX], &sc->eax);
- err |= __put_user(env->exception_index, &sc->trapno);
+ err |= __put_user(cs->exception_index, &sc->trapno);
err |= __put_user(env->error_code, &sc->err);
err |= __put_user(env->eip, &sc->eip);
err |= __put_user(env->segs[R_CS].selector, (unsigned int *)&sc->cs);
diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index ef2dc25..6f103ec 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -173,7 +173,7 @@ int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
{
AlphaCPU *cpu = ALPHA_CPU(cs);
- cpu->env.exception_index = EXCP_MMFAULT;
+ cs->exception_index = EXCP_MMFAULT;
cpu->env.trap_arg0 = address;
return 1;
}
@@ -337,7 +337,7 @@ int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int rw,
fail = get_physical_address(env, addr, 1 << rw, mmu_idx, &phys, &prot);
if (unlikely(fail >= 0)) {
- env->exception_index = EXCP_MMFAULT;
+ cs->exception_index = EXCP_MMFAULT;
env->trap_arg0 = addr;
env->trap_arg1 = fail;
env->trap_arg2 = (rw == 2 ? -1 : rw);
@@ -354,7 +354,7 @@ void alpha_cpu_do_interrupt(CPUState *cs)
{
AlphaCPU *cpu = ALPHA_CPU(cs);
CPUAlphaState *env = &cpu->env;
- int i = env->exception_index;
+ int i = cs->exception_index;
if (qemu_loglevel_mask(CPU_LOG_INT)) {
static int count;
@@ -405,7 +405,7 @@ void alpha_cpu_do_interrupt(CPUState *cs)
++count, name, env->error_code, env->pc, env->ir[IR_SP]);
}
- env->exception_index = -1;
+ cs->exception_index = -1;
#if !defined(CONFIG_USER_ONLY)
switch (i) {
@@ -507,7 +507,10 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
We expect that ENV->PC has already been updated. */
void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error)
{
- env->exception_index = excp;
+ AlphaCPU *cpu = alpha_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
+
+ cs->exception_index = excp;
env->error_code = error;
cpu_loop_exit(env);
}
@@ -516,7 +519,10 @@ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error)
void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr,
int excp, int error)
{
- env->exception_index = excp;
+ AlphaCPU *cpu = alpha_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
+
+ cs->exception_index = excp;
env->error_code = error;
if (retaddr) {
cpu_restore_state(env, retaddr);
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index d140688..22fcbe1 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -91,6 +91,8 @@ uint64_t helper_stq_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
static void do_unaligned_access(CPUAlphaState *env, target_ulong addr,
int is_write, int is_user, uintptr_t retaddr)
{
+ AlphaCPU *cpu = alpha_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
uint64_t pc;
uint32_t insn;
@@ -104,7 +106,7 @@ static void do_unaligned_access(CPUAlphaState *env, target_ulong addr,
env->trap_arg0 = addr;
env->trap_arg1 = insn >> 26; /* opcode */
env->trap_arg2 = (insn >> 21) & 31; /* dest regno */
- env->exception_index = EXCP_UNALIGN;
+ cs->exception_index = EXCP_UNALIGN;
env->error_code = 0;
cpu_loop_exit(env);
}
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 9d0d8b4..508a7fc 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2072,10 +2072,7 @@ uint32_t HELPER(rbit)(uint32_t x)
void arm_cpu_do_interrupt(CPUState *cs)
{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
-
- env->exception_index = -1;
+ cs->exception_index = -1;
}
int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
@@ -2085,10 +2082,10 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
CPUARMState *env = &cpu->env;
if (rw == 2) {
- env->exception_index = EXCP_PREFETCH_ABORT;
+ cs->exception_index = EXCP_PREFETCH_ABORT;
env->cp15.c6_insn = address;
} else {
- env->exception_index = EXCP_DATA_ABORT;
+ cs->exception_index = EXCP_DATA_ABORT;
env->cp15.c6_data = address;
}
return 1;
@@ -2270,7 +2267,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
uint32_t lr;
uint32_t addr;
- arm_log_exception(env->exception_index);
+ arm_log_exception(cs->exception_index);
lr = 0xfffffff1;
if (env->v7m.current_sp)
@@ -2282,7 +2279,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
handle it. */
/* TODO: Need to escalate if the current priority is higher than the
one we're raising. */
- switch (env->exception_index) {
+ switch (cs->exception_index) {
case EXCP_UDEF:
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
return;
@@ -2314,7 +2311,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
do_v7m_exception_exit(env);
return;
default:
- cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
+ cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
return; /* Never happens. Keep compiler happy. */
}
@@ -2355,10 +2352,10 @@ void arm_cpu_do_interrupt(CPUState *cs)
assert(!IS_M(env));
- arm_log_exception(env->exception_index);
+ arm_log_exception(cs->exception_index);
/* TODO: Vectored interrupt controller. */
- switch (env->exception_index) {
+ switch (cs->exception_index) {
case EXCP_UDEF:
new_mode = ARM_CPU_MODE_UND;
addr = 0x04;
@@ -2439,7 +2436,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
offset = 4;
break;
default:
- cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
+ cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
return; /* Never happens. Keep compiler happy. */
}
/* High vectors. */
@@ -3053,13 +3050,13 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
if (access_type == 2) {
env->cp15.c5_insn = ret;
env->cp15.c6_insn = address;
- env->exception_index = EXCP_PREFETCH_ABORT;
+ cs->exception_index = EXCP_PREFETCH_ABORT;
} else {
env->cp15.c5_data = ret;
if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
env->cp15.c5_data |= (1 << 11);
env->cp15.c6_data = address;
- env->exception_index = EXCP_DATA_ABORT;
+ cs->exception_index = EXCP_DATA_ABORT;
}
return 1;
}
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 13d34fb..2c2b3b7 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -24,7 +24,10 @@
static void raise_exception(CPUARMState *env, int tt)
{
- env->exception_index = tt;
+ ARMCPU *cpu = arm_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
+
+ cs->exception_index = tt;
cpu_loop_exit(env);
}
@@ -75,15 +78,16 @@ void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
ARMCPU *cpu = arm_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
int ret;
- ret = arm_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
+ ret = arm_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
}
- raise_exception(env, env->exception_index);
+ raise_exception(env, cs->exception_index);
}
}
#endif
@@ -221,14 +225,16 @@ void HELPER(wfi)(CPUARMState *env)
{
CPUState *cs = CPU(arm_env_get_cpu(env));
- env->exception_index = EXCP_HLT;
+ cs->exception_index = EXCP_HLT;
cs->halted = 1;
cpu_loop_exit(env);
}
void HELPER(exception)(CPUARMState *env, uint32_t excp)
{
- env->exception_index = excp;
+ CPUState *cs = CPU(arm_env_get_cpu(env));
+
+ cs->exception_index = excp;
cpu_loop_exit(env);
}
diff --git a/target-cris/helper.c b/target-cris/helper.c
index 72dc839..3c4501c 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -41,7 +41,7 @@ void cris_cpu_do_interrupt(CPUState *cs)
CRISCPU *cpu = CRIS_CPU(cs);
CPUCRISState *env = &cpu->env;
- env->exception_index = -1;
+ cs->exception_index = -1;
env->pregs[PR_ERP] = env->pc;
}
@@ -55,7 +55,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
{
CRISCPU *cpu = CRIS_CPU(cs);
- cpu->env.exception_index = 0xaa;
+ cs->exception_index = 0xaa;
cpu->env.pregs[PR_EDA] = address;
cpu_dump_state(cs, stderr, fprintf, 0);
return 1;
@@ -88,7 +88,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
rw, mmu_idx, 0);
if (miss) {
- if (env->exception_index == EXCP_BUSFAULT) {
+ if (cs->exception_index == EXCP_BUSFAULT) {
cpu_abort(env,
"CRIS: Illegal recursive bus fault."
"addr=%" VADDR_PRIx " rw=%d\n",
@@ -96,7 +96,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
}
env->pregs[PR_EDA] = address;
- env->exception_index = EXCP_BUSFAULT;
+ cs->exception_index = EXCP_BUSFAULT;
env->fault_vector = res.bf_vec;
r = 1;
} else {
@@ -125,11 +125,11 @@ void crisv10_cpu_do_interrupt(CPUState *cs)
int ex_vec = -1;
D_LOG("exception index=%d interrupt_req=%d\n",
- env->exception_index,
+ cs->exception_index,
cs->interrupt_request);
assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
- switch (env->exception_index) {
+ switch (cs->exception_index) {
case EXCP_BREAK:
/* These exceptions are genereated by the core itself.
ERP should point to the insn following the brk. */
@@ -182,10 +182,10 @@ void cris_cpu_do_interrupt(CPUState *cs)
int ex_vec = -1;
D_LOG("exception index=%d interrupt_req=%d\n",
- env->exception_index,
+ cs->exception_index,
cs->interrupt_request);
- switch (env->exception_index) {
+ switch (cs->exception_index) {
case EXCP_BREAK:
/* These exceptions are genereated by the core itself.
ERP should point to the insn following the brk. */
@@ -248,7 +248,7 @@ void cris_cpu_do_interrupt(CPUState *cs)
/* Clear the excption_index to avoid spurios hw_aborts for recursive
bus faults. */
- env->exception_index = -1;
+ cs->exception_index = -1;
D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
__func__, env->pc, ex_vec,
diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
index 4a6215d..9b20b94 100644
--- a/target-cris/op_helper.c
+++ b/target-cris/op_helper.c
@@ -79,8 +79,10 @@ void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx,
void helper_raise_exception(CPUCRISState *env, uint32_t index)
{
- env->exception_index = index;
- cpu_loop_exit(env);
+ CPUState *cs = CPU(cris_env_get_cpu(env));
+
+ cs->exception_index = index;
+ cpu_loop_exit(env);
}
void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
diff --git a/target-i386/excp_helper.c b/target-i386/excp_helper.c
index 5319aef..ec76eba 100644
--- a/target-i386/excp_helper.c
+++ b/target-i386/excp_helper.c
@@ -94,6 +94,8 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno,
int is_int, int error_code,
int next_eip_addend)
{
+ CPUState *cs = CPU(x86_env_get_cpu(env));
+
if (!is_int) {
cpu_svm_check_intercept_param(env, SVM_EXIT_EXCP_BASE + intno,
error_code);
@@ -102,7 +104,7 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno,
cpu_svm_check_intercept_param(env, SVM_EXIT_SWINT, 0);
}
- env->exception_index = intno;
+ cs->exception_index = intno;
env->error_code = error_code;
env->exception_is_int = is_int;
env->exception_next_eip = env->eip + next_eip_addend;
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 8c2ad94..864d9f8 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -496,7 +496,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
env->cr[2] = addr;
env->error_code = (is_write << PG_ERROR_W_BIT);
env->error_code |= PG_ERROR_U_MASK;
- env->exception_index = EXCP0E_PAGE;
+ cs->exception_index = EXCP0E_PAGE;
return 1;
}
@@ -555,7 +555,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
sext = (int64_t)addr >> 47;
if (sext != 0 && sext != -1) {
env->error_code = 0;
- env->exception_index = EXCP0D_GPF;
+ cs->exception_index = EXCP0D_GPF;
return 1;
}
@@ -885,7 +885,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
env->cr[2] = addr;
}
env->error_code = error_code;
- env->exception_index = EXCP0E_PAGE;
+ cs->exception_index = EXCP0E_PAGE;
return 1;
}
diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c
index 5b25ccd..c0d3b45 100644
--- a/target-i386/mem_helper.c
+++ b/target-i386/mem_helper.c
@@ -136,15 +136,16 @@ void tlb_fill(CPUX86State *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
X86CPU *cpu = x86_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
int ret;
- ret = x86_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
+ ret = x86_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (ret) {
if (retaddr) {
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
}
- raise_exception_err(env, env->exception_index, env->error_code);
+ raise_exception_err(env, cs->exception_index, env->error_code);
}
}
#endif
diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c
index 93933fd..a058c43 100644
--- a/target-i386/misc_helper.c
+++ b/target-i386/misc_helper.c
@@ -573,7 +573,7 @@ static void do_hlt(X86CPU *cpu)
env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
cs->halted = 1;
- env->exception_index = EXCP_HLT;
+ cs->exception_index = EXCP_HLT;
cpu_loop_exit(env);
}
@@ -620,6 +620,8 @@ void helper_mwait(CPUX86State *env, int next_eip_addend)
void helper_debug(CPUX86State *env)
{
- env->exception_index = EXCP_DEBUG;
+ CPUState *cs = CPU(x86_env_get_cpu(env));
+
+ cs->exception_index = EXCP_DEBUG;
cpu_loop_exit(env);
}
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index e789102..b689e94 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -935,7 +935,9 @@ static void do_interrupt64(CPUX86State *env, int intno, int is_int,
#if defined(CONFIG_USER_ONLY)
void helper_syscall(CPUX86State *env, int next_eip_addend)
{
- env->exception_index = EXCP_SYSCALL;
+ CPUState *cs = CPU(x86_env_get_cpu(env));
+
+ cs->exception_index = EXCP_SYSCALL;
env->exception_next_eip = env->eip + next_eip_addend;
cpu_loop_exit(env);
}
@@ -1244,7 +1246,7 @@ void x86_cpu_do_interrupt(CPUState *cs)
/* if user mode only, we simulate a fake exception
which will be handled outside the cpu execution
loop */
- do_interrupt_user(env, env->exception_index,
+ do_interrupt_user(env, cs->exception_index,
env->exception_is_int,
env->error_code,
env->exception_next_eip);
@@ -1254,7 +1256,7 @@ void x86_cpu_do_interrupt(CPUState *cs)
/* simulate a real cpu exception. On i386, it can
trigger new exceptions, but we do not handle
double or triple faults yet. */
- do_interrupt_all(cpu, env->exception_index,
+ do_interrupt_all(cpu, cs->exception_index,
env->exception_is_int,
env->error_code,
env->exception_next_eip, 0);
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index 4a7de42..3c12cb8 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -122,6 +122,7 @@ static inline void svm_load_seg_cache(CPUX86State *env, hwaddr addr,
void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
{
+ CPUState *cs = CPU(x86_env_get_cpu(env));
target_ulong addr;
uint32_t event_inj;
uint32_t int_ctl;
@@ -290,7 +291,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
/* FIXME: need to implement valid_err */
switch (event_inj & SVM_EVTINJ_TYPE_MASK) {
case SVM_EVTINJ_TYPE_INTR:
- env->exception_index = vector;
+ cs->exception_index = vector;
env->error_code = event_inj_err;
env->exception_is_int = 0;
env->exception_next_eip = -1;
@@ -299,7 +300,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
do_interrupt_x86_hardirq(env, vector, 1);
break;
case SVM_EVTINJ_TYPE_NMI:
- env->exception_index = EXCP02_NMI;
+ cs->exception_index = EXCP02_NMI;
env->error_code = event_inj_err;
env->exception_is_int = 0;
env->exception_next_eip = env->eip;
@@ -307,7 +308,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
cpu_loop_exit(env);
break;
case SVM_EVTINJ_TYPE_EXEPT:
- env->exception_index = vector;
+ cs->exception_index = vector;
env->error_code = event_inj_err;
env->exception_is_int = 0;
env->exception_next_eip = -1;
@@ -315,7 +316,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
cpu_loop_exit(env);
break;
case SVM_EVTINJ_TYPE_SOFT:
- env->exception_index = vector;
+ cs->exception_index = vector;
env->error_code = event_inj_err;
env->exception_is_int = 1;
env->exception_next_eip = env->eip;
@@ -323,7 +324,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
cpu_loop_exit(env);
break;
}
- qemu_log_mask(CPU_LOG_TB_IN_ASM, " %#x %#x\n", env->exception_index,
+ qemu_log_mask(CPU_LOG_TB_IN_ASM, " %#x %#x\n", cs->exception_index,
env->error_code);
}
}
@@ -705,7 +706,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
#GP fault is delivered inside the host. */
/* remove any pending exception */
- env->exception_index = -1;
+ cs->exception_index = -1;
env->error_code = 0;
env->old_exception = -1;
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index 55a3de6..b2093a8 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -57,9 +57,9 @@ void lm32_cpu_do_interrupt(CPUState *cs)
CPULM32State *env = &cpu->env;
qemu_log_mask(CPU_LOG_INT,
- "exception at pc=%x type=%x\n", env->pc, env->exception_index);
+ "exception at pc=%x type=%x\n", env->pc, cs->exception_index);
- switch (env->exception_index) {
+ switch (cs->exception_index) {
case EXCP_INSN_BUS_ERROR:
case EXCP_DATA_BUS_ERROR:
case EXCP_DIVIDE_BY_ZERO:
@@ -70,9 +70,9 @@ void lm32_cpu_do_interrupt(CPUState *cs)
env->ie |= (env->ie & IE_IE) ? IE_EIE : 0;
env->ie &= ~IE_IE;
if (env->dc & DC_RE) {
- env->pc = env->deba + (env->exception_index * 32);
+ env->pc = env->deba + (cs->exception_index * 32);
} else {
- env->pc = env->eba + (env->exception_index * 32);
+ env->pc = env->eba + (cs->exception_index * 32);
}
log_cpu_state_mask(CPU_LOG_INT, cs, 0);
break;
@@ -82,12 +82,12 @@ void lm32_cpu_do_interrupt(CPUState *cs)
env->regs[R_BA] = env->pc;
env->ie |= (env->ie & IE_IE) ? IE_BIE : 0;
env->ie &= ~IE_IE;
- env->pc = env->deba + (env->exception_index * 32);
+ env->pc = env->deba + (cs->exception_index * 32);
log_cpu_state_mask(CPU_LOG_INT, cs, 0);
break;
default:
cpu_abort(env, "unhandled exception type=%d\n",
- env->exception_index);
+ cs->exception_index);
break;
}
}
diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
index 215215e..c7ad910 100644
--- a/target-lm32/op_helper.c
+++ b/target-lm32/op_helper.c
@@ -21,7 +21,9 @@
void HELPER(raise_exception)(CPULM32State *env, uint32_t index)
{
- env->exception_index = index;
+ CPUState *cs = CPU(lm32_env_get_cpu(env));
+
+ cs->exception_index = index;
cpu_loop_exit(env);
}
@@ -30,7 +32,7 @@ void HELPER(hlt)(CPULM32State *env)
CPUState *cs = CPU(lm32_env_get_cpu(env));
cs->halted = 1;
- env->exception_index = EXCP_HLT;
+ cs->exception_index = EXCP_HLT;
cpu_loop_exit(env);
}
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 25a0570..003a298 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -283,7 +283,7 @@ int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
{
M68kCPU *cpu = M68K_CPU(cs);
- cpu->env.exception_index = EXCP_ACCESS;
+ cs->exception_index = EXCP_ACCESS;
cpu->env.mmu.ar = address;
return 1;
}
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
index bc10f38..466ad0c 100644
--- a/target-m68k/op_helper.c
+++ b/target-m68k/op_helper.c
@@ -23,10 +23,7 @@
void m68k_cpu_do_interrupt(CPUState *cs)
{
- M68kCPU *cpu = M68K_CPU(cs);
- CPUM68KState *env = &cpu->env;
-
- env->exception_index = -1;
+ cs->exception_index = -1;
}
void do_interrupt_m68k_hardirq(CPUM68KState *env)
@@ -88,7 +85,7 @@ static void do_rte(CPUM68KState *env)
static void do_interrupt_all(CPUM68KState *env, int is_hw)
{
- CPUState *cs;
+ CPUState *cs = CPU(m68k_env_get_cpu(env));
uint32_t sp;
uint32_t fmt;
uint32_t retaddr;
@@ -98,7 +95,7 @@ static void do_interrupt_all(CPUM68KState *env, int is_hw)
retaddr = env->pc;
if (!is_hw) {
- switch (env->exception_index) {
+ switch (cs->exception_index) {
case EXCP_RTE:
/* Return from an exception. */
do_rte(env);
@@ -113,20 +110,19 @@ static void do_interrupt_all(CPUM68KState *env, int is_hw)
do_m68k_semihosting(env, env->dregs[0]);
return;
}
- cs = CPU(m68k_env_get_cpu(env));
cs->halted = 1;
- env->exception_index = EXCP_HLT;
+ cs->exception_index = EXCP_HLT;
cpu_loop_exit(env);
return;
}
- if (env->exception_index >= EXCP_TRAP0
- && env->exception_index <= EXCP_TRAP15) {
+ if (cs->exception_index >= EXCP_TRAP0
+ && cs->exception_index <= EXCP_TRAP15) {
/* Move the PC after the trap instruction. */
retaddr += 2;
}
}
- vector = env->exception_index << 2;
+ vector = cs->exception_index << 2;
sp = env->aregs[7];
@@ -169,7 +165,9 @@ void do_interrupt_m68k_hardirq(CPUM68KState *env)
static void raise_exception(CPUM68KState *env, int tt)
{
- env->exception_index = tt;
+ CPUState *cs = CPU(m68k_env_get_cpu(env));
+
+ cs->exception_index = tt;
cpu_loop_exit(env);
}
diff --git a/target-m68k/qregs.def b/target-m68k/qregs.def
index 4235b02..204663e 100644
--- a/target-m68k/qregs.def
+++ b/target-m68k/qregs.def
@@ -7,6 +7,5 @@ DEFO32(CC_SRC, cc_src)
DEFO32(CC_X, cc_x)
DEFO32(DIV1, div1)
DEFO32(DIV2, div2)
-DEFO32(EXCEPTION, exception_index)
DEFO32(MACSR, macsr)
DEFO32(MAC_MASK, mac_mask)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 0be0a96..f3cdee0 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -43,6 +43,7 @@
#undef DEFF64
static TCGv_i32 cpu_halted;
+static TCGv_i32 cpu_exception_index;
static TCGv_ptr cpu_env;
@@ -81,6 +82,10 @@ void m68k_tcg_init(void)
cpu_halted = tcg_global_mem_new_i32(TCG_AREG0,
-offsetof(M68kCPU, env) +
offsetof(CPUState, halted), "HALTED");
+ cpu_exception_index = tcg_global_mem_new_i32(TCG_AREG0,
+ -offsetof(M68kCPU, env) +
+ offsetof(CPUState, exception_index),
+ "EXCEPTION");
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
index d03f369..4825415 100644
--- a/target-microblaze/helper.c
+++ b/target-microblaze/helper.c
@@ -31,7 +31,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
CPUMBState *env = &cpu->env;
- env->exception_index = -1;
+ cs->exception_index = -1;
env->res_addr = RES_ADDR_NONE;
env->regs[14] = env->sregs[SR_PC];
}
@@ -39,9 +39,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int mmu_idx)
{
- MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
-
- cpu->env.exception_index = 0xaa;
+ cs->exception_index = 0xaa;
cpu_dump_state(cs, stderr, fprintf, 0);
return 1;
}
@@ -99,12 +97,12 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
break;
}
- if (env->exception_index == EXCP_MMU) {
+ if (cs->exception_index == EXCP_MMU) {
cpu_abort(env, "recursive faults\n");
}
/* TLB miss. */
- env->exception_index = EXCP_MMU;
+ cs->exception_index = EXCP_MMU;
}
} else {
/* MMU disabled or not available. */
@@ -127,7 +125,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
/* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */
env->res_addr = RES_ADDR_NONE;
- switch (env->exception_index) {
+ switch (cs->exception_index) {
case EXCP_HW_EXCP:
if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
qemu_log("Exception raised on system without exceptions!\n");
@@ -253,7 +251,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
env->sregs[SR_MSR] |= t;
env->sregs[SR_MSR] |= MSR_BIP;
- if (env->exception_index == EXCP_HW_BREAK) {
+ if (cs->exception_index == EXCP_HW_BREAK) {
env->regs[16] = env->sregs[SR_PC];
env->sregs[SR_MSR] |= MSR_BIP;
env->sregs[SR_PC] = cpu->base_vectors + 0x18;
@@ -262,7 +260,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
break;
default:
cpu_abort(env, "unhandled exception type=%d\n",
- env->exception_index);
+ cs->exception_index);
break;
}
}
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index b70b2ea..318185a 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -95,7 +95,9 @@ uint32_t helper_get(uint32_t id, uint32_t ctrl)
void helper_raise_exception(CPUMBState *env, uint32_t index)
{
- env->exception_index = index;
+ CPUState *cs = CPU(mb_env_get_cpu(env));
+
+ cs->exception_index = index;
cpu_loop_exit(env);
}
diff --git a/target-mips/helper.c b/target-mips/helper.c
index d8e9166..698c3d1 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -204,6 +204,7 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
int rw, int tlb_error)
{
+ CPUState *cs = CPU(mips_env_get_cpu(env));
int exception = 0, error_code = 0;
switch (tlb_error) {
@@ -249,7 +250,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
#endif
- env->exception_index = exception;
+ cs->exception_index = exception;
env->error_code = error_code;
}
@@ -404,27 +405,29 @@ static void set_hflags_for_handler (CPUMIPSState *env)
void mips_cpu_do_interrupt(CPUState *cs)
{
+#if !defined(CONFIG_USER_ONLY)
MIPSCPU *cpu = MIPS_CPU(cs);
CPUMIPSState *env = &cpu->env;
-#if !defined(CONFIG_USER_ONLY)
target_ulong offset;
int cause = -1;
const char *name;
- if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
- if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
+ if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
+ if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
name = "unknown";
- else
- name = excp_names[env->exception_index];
+ } else {
+ name = excp_names[cs->exception_index];
+ }
qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
__func__, env->active_tc.PC, env->CP0_EPC, name);
}
- if (env->exception_index == EXCP_EXT_INTERRUPT &&
- (env->hflags & MIPS_HFLAG_DM))
- env->exception_index = EXCP_DINT;
+ if (cs->exception_index == EXCP_EXT_INTERRUPT &&
+ (env->hflags & MIPS_HFLAG_DM)) {
+ cs->exception_index = EXCP_DINT;
+ }
offset = 0x180;
- switch (env->exception_index) {
+ switch (cs->exception_index) {
case EXCP_DSS:
env->CP0_Debug |= 1 << CP0DB_DSS;
/* Debug single step cannot be raised inside a delay slot and
@@ -632,11 +635,11 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
break;
default:
- qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index);
- printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
+ qemu_log("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
+ printf("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
exit(1);
}
- if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
+ if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
__func__, env->active_tc.PC, env->CP0_EPC, cause,
@@ -644,7 +647,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->CP0_DEPC);
}
#endif
- env->exception_index = EXCP_NONE;
+ cs->exception_index = EXCP_NONE;
}
#if !defined(CONFIG_USER_ONLY)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 34ac4c6..eeb98a6 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -38,10 +38,12 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
int error_code,
uintptr_t pc)
{
+ CPUState *cs = CPU(mips_env_get_cpu(env));
+
if (exception < EXCP_SC) {
qemu_log("%s: %d %d\n", __func__, exception, error_code);
}
- env->exception_index = exception;
+ cs->exception_index = exception;
env->error_code = error_code;
if (pc) {
@@ -2135,11 +2137,12 @@ void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
MIPSCPU *cpu = mips_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
int ret;
- ret = mips_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
+ ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (ret) {
- do_raise_exception_err(env, env->exception_index,
+ do_raise_exception_err(env, cs->exception_index,
env->error_code, retaddr);
}
}
diff --git a/target-mips/translate.c b/target-mips/translate.c
index ad43d59..716d50c 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -15922,10 +15922,8 @@ MIPSCPU *cpu_mips_init(const char *cpu_model)
void cpu_state_reset(CPUMIPSState *env)
{
-#ifndef CONFIG_USER_ONLY
MIPSCPU *cpu = mips_env_get_cpu(env);
CPUState *cs = CPU(cpu);
-#endif
/* Reset registers to their default values */
env->CP0_PRid = env->cpu_model->CP0_PRid;
@@ -16049,7 +16047,7 @@ void cpu_state_reset(CPUMIPSState *env)
}
#endif
compute_hflags(env);
- env->exception_index = EXCP_NONE;
+ cs->exception_index = EXCP_NONE;
}
void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, int pc_pos)
diff --git a/target-moxie/helper.c b/target-moxie/helper.c
index 8160475..3b14f37 100644
--- a/target-moxie/helper.c
+++ b/target-moxie/helper.c
@@ -63,7 +63,9 @@ void tlb_fill(CPUMoxieState *env, target_ulong addr, int is_write, int mmu_idx,
void helper_raise_exception(CPUMoxieState *env, int ex)
{
- env->exception_index = ex;
+ CPUState *cs = CPU(moxie_env_get_cpu(env));
+
+ cs->exception_index = ex;
/* Stash the exception type. */
env->sregs[2] = ex;
/* Stash the address where the exception occurred. */
@@ -98,7 +100,9 @@ uint32_t helper_udiv(CPUMoxieState *env, uint32_t a, uint32_t b)
void helper_debug(CPUMoxieState *env)
{
- env->exception_index = EXCP_DEBUG;
+ CPUState *cs = CPU(moxie_env_get_cpu(env));
+
+ cs->exception_index = EXCP_DEBUG;
cpu_loop_exit(env);
}
@@ -106,7 +110,9 @@ void helper_debug(CPUMoxieState *env)
void moxie_cpu_do_interrupt(CPUState *cs)
{
- env->exception_index = -1;
+ CPUState *cs = CPU(moxie_env_get_cpu(env));
+
+ cs->exception_index = -1;
}
int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
@@ -114,7 +120,7 @@ int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
{
MoxieCPU *cpu = MOXIE_CPU(cs);
- cpu->env.exception_index = 0xaa;
+ cs->exception_index = 0xaa;
cpu->env.debug1 = address;
cpu_dump_state(cs, stderr, fprintf, 0);
return 1;
@@ -138,7 +144,7 @@ int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
if (miss) {
/* handle the miss. */
phy = 0;
- env->exception_index = MOXIE_EX_MMU_MISS;
+ cs->exception_index = MOXIE_EX_MMU_MISS;
} else {
phy = res.phy;
r = 0;
@@ -150,10 +156,7 @@ int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
void moxie_cpu_do_interrupt(CPUState *cs)
{
- MoxieCPU *cpu = MOXIE_CPU(cs);
- CPUMoxieState *env = &cpu->env;
-
- switch (env->exception_index) {
+ switch (cs->exception_index) {
case MOXIE_EX_BREAK:
break;
default:
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index ee1591d..b233969 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -69,7 +69,7 @@ static void openrisc_cpu_reset(CPUState *s)
cpu->env.pc = 0x100;
cpu->env.sr = SR_FO | SR_SM;
- cpu->env.exception_index = -1;
+ s->exception_index = -1;
cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S;
diff --git a/target-openrisc/exception.c b/target-openrisc/exception.c
index 58e53c6..b96f3f8 100644
--- a/target-openrisc/exception.c
+++ b/target-openrisc/exception.c
@@ -22,6 +22,8 @@
void QEMU_NORETURN raise_exception(OpenRISCCPU *cpu, uint32_t excp)
{
- cpu->env.exception_index = excp;
+ CPUState *cs = CPU(cpu);
+
+ cs->exception_index = excp;
cpu_loop_exit(&cpu->env);
}
diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
index 16ef4b3..64f2ca6 100644
--- a/target-openrisc/interrupt.c
+++ b/target-openrisc/interrupt.c
@@ -27,25 +27,26 @@
void openrisc_cpu_do_interrupt(CPUState *cs)
{
+#ifndef CONFIG_USER_ONLY
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
CPUOpenRISCState *env = &cpu->env;
-#ifndef CONFIG_USER_ONLY
+
if (env->flags & D_FLAG) { /* Delay Slot insn */
env->flags &= ~D_FLAG;
env->sr |= SR_DSX;
- if (env->exception_index == EXCP_TICK ||
- env->exception_index == EXCP_INT ||
- env->exception_index == EXCP_SYSCALL ||
- env->exception_index == EXCP_FPE) {
+ if (cs->exception_index == EXCP_TICK ||
+ cs->exception_index == EXCP_INT ||
+ cs->exception_index == EXCP_SYSCALL ||
+ cs->exception_index == EXCP_FPE) {
env->epcr = env->jmp_pc;
} else {
env->epcr = env->pc - 4;
}
} else {
- if (env->exception_index == EXCP_TICK ||
- env->exception_index == EXCP_INT ||
- env->exception_index == EXCP_SYSCALL ||
- env->exception_index == EXCP_FPE) {
+ if (cs->exception_index == EXCP_TICK ||
+ cs->exception_index == EXCP_INT ||
+ cs->exception_index == EXCP_SYSCALL ||
+ cs->exception_index == EXCP_FPE) {
env->epcr = env->npc;
} else {
env->epcr = env->pc;
@@ -65,12 +66,12 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
- if (env->exception_index > 0 && env->exception_index < EXCP_NR) {
- env->pc = (env->exception_index << 8);
+ if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) {
+ env->pc = (cs->exception_index << 8);
} else {
- cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
+ cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
}
#endif
- env->exception_index = -1;
+ cs->exception_index = -1;
}
diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c
index 0f13c5d..b1830da 100644
--- a/target-openrisc/mmu.c
+++ b/target-openrisc/mmu.c
@@ -146,6 +146,7 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu,
target_ulong address,
int rw, int tlb_error)
{
+ CPUState *cs = CPU(cpu);
int exception = 0;
switch (tlb_error) {
@@ -176,7 +177,7 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu,
#endif
}
- cpu->env.exception_index = exception;
+ cs->exception_index = exception;
cpu->env.eear = address;
}
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index c959460..0ec2615 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -43,13 +43,15 @@ void ppc_cpu_do_interrupt(CPUState *cs)
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
- env->exception_index = POWERPC_EXCP_NONE;
+ cs->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
}
void ppc_hw_interrupt(CPUPPCState *env)
{
- env->exception_index = POWERPC_EXCP_NONE;
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
+
+ cs->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
}
#else /* defined(CONFIG_USER_ONLY) */
@@ -68,8 +70,8 @@ static inline void dump_syscall(CPUPPCState *env)
*/
static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
{
+ CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- CPUState *cs;
target_ulong msr, new_msr, vector;
int srr0, srr1, asrr0, asrr1;
int lpes0, lpes1, lev;
@@ -135,7 +137,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
fprintf(stderr, "Machine check while not allowed. "
"Entering checkstop state\n");
}
- cs = CPU(cpu);
cs->halted = 1;
cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
}
@@ -202,7 +203,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
case POWERPC_EXCP_FP:
if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
LOG_EXCP("Ignore floating point exception\n");
- env->exception_index = POWERPC_EXCP_NONE;
+ cs->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
return;
}
@@ -655,7 +656,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
hreg_compute_hflags(env);
env->nip = vector;
/* Reset exception state */
- env->exception_index = POWERPC_EXCP_NONE;
+ cs->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
@@ -672,7 +673,7 @@ void ppc_cpu_do_interrupt(CPUState *cs)
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
- powerpc_excp(cpu, env->excp_model, env->exception_index);
+ powerpc_excp(cpu, env->excp_model, cs->exception_index);
}
void ppc_hw_interrupt(CPUPPCState *env)
@@ -808,10 +809,12 @@ static void cpu_dump_rfi(target_ulong RA, target_ulong msr)
void helper_raise_exception_err(CPUPPCState *env, uint32_t exception,
uint32_t error_code)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
+
#if 0
printf("Raise exception %3x code : %d\n", exception, error_code);
#endif
- env->exception_index = exception;
+ cs->exception_index = exception;
env->error_code = error_code;
cpu_loop_exit(env);
}
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 4f60218..314e66f 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -108,6 +108,7 @@ uint32_t helper_compute_fprf(CPUPPCState *env, uint64_t arg, uint32_t set_fprf)
/* Floating-point invalid operations exception */
static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
uint64_t ret = 0;
int ve;
@@ -142,7 +143,7 @@ static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op)
env->fpscr |= 0x11 << FPSCR_FPCC;
/* We must update the target FPR before raising the exception */
if (ve != 0) {
- env->exception_index = POWERPC_EXCP_PROGRAM;
+ cs->exception_index = POWERPC_EXCP_PROGRAM;
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
@@ -207,6 +208,8 @@ static inline void float_zero_divide_excp(CPUPPCState *env)
static inline void float_overflow_excp(CPUPPCState *env)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
+
env->fpscr |= 1 << FPSCR_OX;
/* Update the floating-point exception summary */
env->fpscr |= 1 << FPSCR_FX;
@@ -215,7 +218,7 @@ static inline void float_overflow_excp(CPUPPCState *env)
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
/* We must update the target FPR before raising the exception */
- env->exception_index = POWERPC_EXCP_PROGRAM;
+ cs->exception_index = POWERPC_EXCP_PROGRAM;
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
} else {
env->fpscr |= 1 << FPSCR_XX;
@@ -225,6 +228,8 @@ static inline void float_overflow_excp(CPUPPCState *env)
static inline void float_underflow_excp(CPUPPCState *env)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
+
env->fpscr |= 1 << FPSCR_UX;
/* Update the floating-point exception summary */
env->fpscr |= 1 << FPSCR_FX;
@@ -233,13 +238,15 @@ static inline void float_underflow_excp(CPUPPCState *env)
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
/* We must update the target FPR before raising the exception */
- env->exception_index = POWERPC_EXCP_PROGRAM;
+ cs->exception_index = POWERPC_EXCP_PROGRAM;
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
}
}
static inline void float_inexact_excp(CPUPPCState *env)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
+
env->fpscr |= 1 << FPSCR_XX;
/* Update the floating-point exception summary */
env->fpscr |= 1 << FPSCR_FX;
@@ -247,7 +254,7 @@ static inline void float_inexact_excp(CPUPPCState *env)
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
/* We must update the target FPR before raising the exception */
- env->exception_index = POWERPC_EXCP_PROGRAM;
+ cs->exception_index = POWERPC_EXCP_PROGRAM;
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
}
}
@@ -299,6 +306,7 @@ void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)
void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
int prev;
prev = (env->fpscr >> bit) & 1;
@@ -422,7 +430,7 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
/* We have to update Rc1 before raising the exception */
- env->exception_index = POWERPC_EXCP_PROGRAM;
+ cs->exception_index = POWERPC_EXCP_PROGRAM;
break;
}
}
@@ -430,6 +438,7 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
target_ulong prev, new;
int i;
@@ -451,7 +460,7 @@ void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
}
if ((fpscr_ex & fpscr_eex) != 0) {
env->fpscr |= 1 << FPSCR_FEX;
- env->exception_index = POWERPC_EXCP_PROGRAM;
+ cs->exception_index = POWERPC_EXCP_PROGRAM;
/* XXX: we should compute it properly */
env->error_code = POWERPC_EXCP_FP;
} else {
@@ -467,6 +476,7 @@ void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
void helper_float_check_status(CPUPPCState *env)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
int status = get_float_exception_flags(&env->fp_status);
if (status & float_flag_divbyzero) {
@@ -479,11 +489,11 @@ void helper_float_check_status(CPUPPCState *env)
float_inexact_excp(env);
}
- if (env->exception_index == POWERPC_EXCP_PROGRAM &&
+ if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
(env->error_code & POWERPC_EXCP_FP)) {
/* Differred floating-point exception after target FPR update */
if (msr_fe0 != 0 || msr_fe1 != 0) {
- helper_raise_exception_err(env, env->exception_index,
+ helper_raise_exception_err(env, cs->exception_index,
env->error_code);
}
}
diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
index 6a77dc4..aa87084 100644
--- a/target-ppc/mmu-hash32.c
+++ b/target-ppc/mmu-hash32.c
@@ -222,6 +222,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
target_ulong eaddr, int rwx,
hwaddr *raddr, int *prot)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
LOG_MMU("direct store...\n");
@@ -238,7 +239,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
if (rwx == 2) {
/* No code fetch is allowed in direct-store areas */
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x10000000;
return 1;
}
@@ -249,7 +250,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
break;
case ACCESS_FLOAT:
/* Floating point load/store */
- env->exception_index = POWERPC_EXCP_ALIGN;
+ cs->exception_index = POWERPC_EXCP_ALIGN;
env->error_code = POWERPC_EXCP_ALIGN_FP;
env->spr[SPR_DAR] = eaddr;
return 1;
@@ -272,7 +273,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
return 0;
case ACCESS_EXT:
/* eciwx or ecowx */
- env->exception_index = POWERPC_EXCP_DSI;
+ cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
env->spr[SPR_DAR] = eaddr;
if (rwx == 1) {
@@ -290,7 +291,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
*raddr = eaddr;
return 0;
} else {
- env->exception_index = POWERPC_EXCP_DSI;
+ cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
env->spr[SPR_DAR] = eaddr;
if (rwx == 1) {
@@ -383,6 +384,7 @@ static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,
int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx,
int mmu_idx)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
target_ulong sr;
hwaddr pte_offset;
ppc_hash_pte32_t pte;
@@ -409,10 +411,10 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx,
if (raddr != -1) {
if (need_prot[rwx] & ~prot) {
if (rwx == 2) {
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x08000000;
} else {
- env->exception_index = POWERPC_EXCP_DSI;
+ cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
env->spr[SPR_DAR] = eaddr;
if (rwx == 1) {
@@ -449,7 +451,7 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx,
/* 5. Check for segment level no-execute violation */
if ((rwx == 2) && (sr & SR32_NX)) {
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x10000000;
return 1;
}
@@ -458,10 +460,10 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx,
pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
if (pte_offset == -1) {
if (rwx == 2) {
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x40000000;
} else {
- env->exception_index = POWERPC_EXCP_DSI;
+ cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
env->spr[SPR_DAR] = eaddr;
if (rwx == 1) {
@@ -483,10 +485,10 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx,
/* Access right violation */
LOG_MMU("PTE access rejected\n");
if (rwx == 2) {
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x08000000;
} else {
- env->exception_index = POWERPC_EXCP_DSI;
+ cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
env->spr[SPR_DAR] = eaddr;
if (rwx == 1) {
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 67fc1b5..04dcfb3 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -399,6 +399,7 @@ static hwaddr ppc_hash64_pte_raddr(ppc_slb_t *slb, ppc_hash_pte64_t pte,
int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr,
int rwx, int mmu_idx)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
ppc_slb_t *slb;
hwaddr pte_offset;
ppc_hash_pte64_t pte;
@@ -425,10 +426,10 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr,
if (!slb) {
if (rwx == 2) {
- env->exception_index = POWERPC_EXCP_ISEG;
+ cs->exception_index = POWERPC_EXCP_ISEG;
env->error_code = 0;
} else {
- env->exception_index = POWERPC_EXCP_DSEG;
+ cs->exception_index = POWERPC_EXCP_DSEG;
env->error_code = 0;
env->spr[SPR_DAR] = eaddr;
}
@@ -437,7 +438,7 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr,
/* 3. Check for segment level no-execute violation */
if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x10000000;
return 1;
}
@@ -446,10 +447,10 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr,
pte_offset = ppc_hash64_htab_lookup(env, slb, eaddr, &pte);
if (pte_offset == -1) {
if (rwx == 2) {
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x40000000;
} else {
- env->exception_index = POWERPC_EXCP_DSI;
+ cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
env->spr[SPR_DAR] = eaddr;
if (rwx == 1) {
@@ -472,12 +473,12 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr,
/* Access right violation */
LOG_MMU("PTE access rejected\n");
if (rwx == 2) {
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x08000000;
} else {
target_ulong dsisr = 0;
- env->exception_index = POWERPC_EXCP_DSI;
+ cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
env->spr[SPR_DAR] = eaddr;
if (need_prot[rwx] & ~pp_prot) {
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 04a840b..79a9134 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -1491,6 +1491,7 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
int rw, int mmu_idx)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
mmu_ctx_t ctx;
int access_type;
int ret = 0;
@@ -1510,24 +1511,24 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
mmu_idx, TARGET_PAGE_SIZE);
ret = 0;
} else if (ret < 0) {
- LOG_MMU_STATE(CPU(ppc_env_get_cpu(env)));
+ LOG_MMU_STATE(cs);
if (access_type == ACCESS_CODE) {
switch (ret) {
case -1:
/* No matches in page tables or TLB */
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_6xx:
- env->exception_index = POWERPC_EXCP_IFTLB;
+ cs->exception_index = POWERPC_EXCP_IFTLB;
env->error_code = 1 << 18;
env->spr[SPR_IMISS] = address;
env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
goto tlb_miss;
case POWERPC_MMU_SOFT_74xx:
- env->exception_index = POWERPC_EXCP_IFTLB;
+ cs->exception_index = POWERPC_EXCP_IFTLB;
goto tlb_miss_74xx;
case POWERPC_MMU_SOFT_4xx:
case POWERPC_MMU_SOFT_4xx_Z:
- env->exception_index = POWERPC_EXCP_ITLB;
+ cs->exception_index = POWERPC_EXCP_ITLB;
env->error_code = 0;
env->spr[SPR_40x_DEAR] = address;
env->spr[SPR_40x_ESR] = 0x00000000;
@@ -1536,7 +1537,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
booke206_update_mas_tlb_miss(env, address, rw);
/* fall through */
case POWERPC_MMU_BOOKE:
- env->exception_index = POWERPC_EXCP_ITLB;
+ cs->exception_index = POWERPC_EXCP_ITLB;
env->error_code = 0;
env->spr[SPR_BOOKE_DEAR] = address;
return -1;
@@ -1555,7 +1556,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
break;
case -2:
/* Access rights violation */
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x08000000;
break;
case -3:
@@ -1564,13 +1565,13 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
(env->mmu_model == POWERPC_MMU_BOOKE206)) {
env->spr[SPR_BOOKE_ESR] = 0x00000000;
}
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x10000000;
break;
case -4:
/* Direct store exception */
/* No code fetch is allowed in direct-store areas */
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x10000000;
break;
}
@@ -1581,10 +1582,10 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_6xx:
if (rw == 1) {
- env->exception_index = POWERPC_EXCP_DSTLB;
+ cs->exception_index = POWERPC_EXCP_DSTLB;
env->error_code = 1 << 16;
} else {
- env->exception_index = POWERPC_EXCP_DLTLB;
+ cs->exception_index = POWERPC_EXCP_DLTLB;
env->error_code = 0;
}
env->spr[SPR_DMISS] = address;
@@ -1598,9 +1599,9 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
break;
case POWERPC_MMU_SOFT_74xx:
if (rw == 1) {
- env->exception_index = POWERPC_EXCP_DSTLB;
+ cs->exception_index = POWERPC_EXCP_DSTLB;
} else {
- env->exception_index = POWERPC_EXCP_DLTLB;
+ cs->exception_index = POWERPC_EXCP_DLTLB;
}
tlb_miss_74xx:
/* Implement LRU algorithm */
@@ -1611,7 +1612,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
break;
case POWERPC_MMU_SOFT_4xx:
case POWERPC_MMU_SOFT_4xx_Z:
- env->exception_index = POWERPC_EXCP_DTLB;
+ cs->exception_index = POWERPC_EXCP_DTLB;
env->error_code = 0;
env->spr[SPR_40x_DEAR] = address;
if (rw) {
@@ -1628,7 +1629,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
booke206_update_mas_tlb_miss(env, address, rw);
/* fall through */
case POWERPC_MMU_BOOKE:
- env->exception_index = POWERPC_EXCP_DTLB;
+ cs->exception_index = POWERPC_EXCP_DTLB;
env->error_code = 0;
env->spr[SPR_BOOKE_DEAR] = address;
env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0;
@@ -1644,7 +1645,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
break;
case -2:
/* Access rights violation */
- env->exception_index = POWERPC_EXCP_DSI;
+ cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
if (env->mmu_model == POWERPC_MMU_SOFT_4xx
|| env->mmu_model == POWERPC_MMU_SOFT_4xx_Z) {
@@ -1670,13 +1671,13 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
switch (access_type) {
case ACCESS_FLOAT:
/* Floating point load/store */
- env->exception_index = POWERPC_EXCP_ALIGN;
+ cs->exception_index = POWERPC_EXCP_ALIGN;
env->error_code = POWERPC_EXCP_ALIGN_FP;
env->spr[SPR_DAR] = address;
break;
case ACCESS_RES:
/* lwarx, ldarx or stwcx. */
- env->exception_index = POWERPC_EXCP_DSI;
+ cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
env->spr[SPR_DAR] = address;
if (rw == 1) {
@@ -1687,7 +1688,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
break;
case ACCESS_EXT:
/* eciwx or ecowx */
- env->exception_index = POWERPC_EXCP_DSI;
+ cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
env->spr[SPR_DAR] = address;
if (rw == 1) {
@@ -1698,7 +1699,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
break;
default:
printf("DSI: invalid exception (%d)\n", ret);
- env->exception_index = POWERPC_EXCP_PROGRAM;
+ cs->exception_index = POWERPC_EXCP_PROGRAM;
env->error_code =
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
env->spr[SPR_DAR] = address;
@@ -1709,7 +1710,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
}
#if 0
printf("%s: set exception to %d %02x\n", __func__,
- env->exception, env->error_code);
+ cs->exception, env->error_code);
#endif
ret = 1;
}
@@ -2908,6 +2909,6 @@ void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx,
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
}
- helper_raise_exception_err(env, env->exception_index, env->error_code);
+ helper_raise_exception_err(env, cpu->exception_index, env->error_code);
}
}
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 8b6fbb5..0934a45 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8511,7 +8511,7 @@ static void ppc_cpu_reset(CPUState *s)
env->reserve_addr = (target_ulong)-1ULL;
/* Be sure no exception or interrupt is pending */
env->pending_interrupts = 0;
- env->exception_index = POWERPC_EXCP_NONE;
+ s->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
diff --git a/target-ppc/user_only_helper.c b/target-ppc/user_only_helper.c
index a7c99e0..829f66f 100644
--- a/target-ppc/user_only_helper.c
+++ b/target-ppc/user_only_helper.c
@@ -39,7 +39,7 @@ int ppc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
env->spr[SPR_DAR] = address;
env->spr[SPR_DSISR] = error_code;
}
- env->exception_index = exception;
+ cs->exception_index = exception;
env->error_code = error_code;
return 1;
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index 361d713..c9d3d55 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -88,10 +88,7 @@ S390CPU *cpu_s390x_init(const char *cpu_model)
void s390_cpu_do_interrupt(CPUState *cs)
{
- S390CPU *cpu = S390_CPU(cs);
- CPUS390XState *env = &cpu->env;
-
- env->exception_index = -1;
+ cs->exception_index = -1;
}
int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
@@ -99,7 +96,7 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
{
S390CPU *cpu = S390_CPU(cs);
- cpu->env.exception_index = EXCP_PGM;
+ cs->exception_index = EXCP_PGM;
cpu->env.int_pgm_code = PGM_ADDRESSING;
/* On real machines this value is dropped into LowMem. Since this
is userland, simply put this someplace that cpu_loop can find it. */
@@ -113,7 +110,9 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
static void trigger_pgm_exception(CPUS390XState *env, uint32_t code,
uint32_t ilen)
{
- env->exception_index = EXCP_PGM;
+ CPUState *cs = CPU(s390_env_get_cpu(env));
+
+ cs->exception_index = EXCP_PGM;
env->int_pgm_code = code;
env->int_pgm_ilen = ilen;
}
@@ -427,7 +426,7 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
CPUS390XState *env = &cpu->env;
target_ulong raddr;
int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
- int old_exc = env->exception_index;
+ int old_exc = cs->exception_index;
uint64_t asc = env->psw.mask & PSW_MASK_ASC;
/* 31-Bit mode */
@@ -436,7 +435,7 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
}
mmu_translate(env, vaddr, 2, asc, &raddr, &prot);
- env->exception_index = old_exc;
+ cs->exception_index = old_exc;
return raddr;
}
@@ -454,7 +453,7 @@ void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
}
}
cs->halted = 1;
- env->exception_index = EXCP_HLT;
+ cs->exception_index = EXCP_HLT;
}
env->psw.addr = addr;
@@ -751,43 +750,43 @@ void s390_cpu_do_interrupt(CPUState *cs)
CPUS390XState *env = &cpu->env;
qemu_log_mask(CPU_LOG_INT, "%s: %d at pc=%" PRIx64 "\n",
- __func__, env->exception_index, env->psw.addr);
+ __func__, cs->exception_index, env->psw.addr);
s390_add_running_cpu(cpu);
/* handle machine checks */
if ((env->psw.mask & PSW_MASK_MCHECK) &&
- (env->exception_index == -1)) {
+ (cs->exception_index == -1)) {
if (env->pending_int & INTERRUPT_MCHK) {
- env->exception_index = EXCP_MCHK;
+ cs->exception_index = EXCP_MCHK;
}
}
/* handle external interrupts */
if ((env->psw.mask & PSW_MASK_EXT) &&
- env->exception_index == -1) {
+ cs->exception_index == -1) {
if (env->pending_int & INTERRUPT_EXT) {
/* code is already in env */
- env->exception_index = EXCP_EXT;
+ cs->exception_index = EXCP_EXT;
} else if (env->pending_int & INTERRUPT_TOD) {
cpu_inject_ext(cpu, 0x1004, 0, 0);
- env->exception_index = EXCP_EXT;
+ cs->exception_index = EXCP_EXT;
env->pending_int &= ~INTERRUPT_EXT;
env->pending_int &= ~INTERRUPT_TOD;
} else if (env->pending_int & INTERRUPT_CPUTIMER) {
cpu_inject_ext(cpu, 0x1005, 0, 0);
- env->exception_index = EXCP_EXT;
+ cs->exception_index = EXCP_EXT;
env->pending_int &= ~INTERRUPT_EXT;
env->pending_int &= ~INTERRUPT_TOD;
}
}
/* handle I/O interrupts */
if ((env->psw.mask & PSW_MASK_IO) &&
- (env->exception_index == -1)) {
+ (cs->exception_index == -1)) {
if (env->pending_int & INTERRUPT_IO) {
- env->exception_index = EXCP_IO;
+ cs->exception_index = EXCP_IO;
}
}
- switch (env->exception_index) {
+ switch (cs->exception_index) {
case EXCP_PGM:
do_program_interrupt(env);
break;
@@ -804,7 +803,7 @@ void s390_cpu_do_interrupt(CPUState *cs)
do_mchk_interrupt(env);
break;
}
- env->exception_index = -1;
+ cs->exception_index = -1;
if (!env->pending_int) {
cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index 747ba46..e2748a7 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -1048,8 +1048,9 @@ void HELPER(stura)(CPUS390XState *env, uint64_t addr, uint64_t v1)
/* load real address */
uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr)
{
+ CPUState *cs = CPU(s390_env_get_cpu(env));
uint32_t cc = 0;
- int old_exc = env->exception_index;
+ int old_exc = cs->exception_index;
uint64_t asc = env->psw.mask & PSW_MASK_ASC;
uint64_t ret;
int flags;
@@ -1059,16 +1060,16 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr)
program_interrupt(env, PGM_SPECIAL_OP, 2);
}
- env->exception_index = old_exc;
+ cs->exception_index = old_exc;
if (mmu_translate(env, addr, 0, asc, &ret, &flags)) {
cc = 3;
}
- if (env->exception_index == EXCP_PGM) {
+ if (cs->exception_index == EXCP_PGM) {
ret = env->int_pgm_code | 0x80000000;
} else {
ret |= addr & ~TARGET_PAGE_MASK;
}
- env->exception_index = old_exc;
+ cs->exception_index = old_exc;
env->cc_op = cc;
return ret;
diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
index 1690907..b6bd16f 100644
--- a/target-s390x/misc_helper.c
+++ b/target-s390x/misc_helper.c
@@ -46,9 +46,10 @@
void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
uintptr_t retaddr)
{
+ CPUState *cs = CPU(s390_env_get_cpu(env));
int t;
- env->exception_index = EXCP_PGM;
+ cs->exception_index = EXCP_PGM;
env->int_pgm_code = excp;
/* Use the (ultimate) callers address to find the insn that trapped. */
@@ -65,8 +66,10 @@ void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
/* Raise an exception statically from a TB. */
void HELPER(exception)(CPUS390XState *env, uint32_t excp)
{
+ CPUState *cs = CPU(s390_env_get_cpu(env));
+
HELPER_LOG("%s: exception %d\n", __func__, excp);
- env->exception_index = excp;
+ cs->exception_index = excp;
cpu_loop_exit(env);
}
@@ -154,17 +157,21 @@ static inline void ebcdic_put(uint8_t *p, const char *ascii, int len)
void program_interrupt(CPUS390XState *env, uint32_t code, int ilen)
{
+ S390CPU *cpu = s390_env_get_cpu(env);
+
qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n",
env->psw.addr);
if (kvm_enabled()) {
#ifdef CONFIG_KVM
- kvm_s390_interrupt(s390_env_get_cpu(env), KVM_S390_PROGRAM_INT, code);
+ kvm_s390_interrupt(cpu, KVM_S390_PROGRAM_INT, code);
#endif
} else {
+ CPUState *cs = CPU(cpu);
+
env->int_pgm_code = code;
env->int_pgm_ilen = ilen;
- env->exception_index = EXCP_PGM;
+ cs->exception_index = EXCP_PGM;
cpu_loop_exit(env);
}
}
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 3f8f1fa..0357ceb 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -33,10 +33,7 @@
void superh_cpu_do_interrupt(CPUState *cs)
{
- SuperHCPU *cpu = SUPERH_CPU(cs);
- CPUSH4State *env = &cpu->env;
-
- env->exception_index = -1;
+ cs->exception_index = -1;
}
int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
@@ -46,16 +43,16 @@ int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
CPUSH4State *env = &cpu->env;
env->tea = address;
- env->exception_index = -1;
+ cs->exception_index = -1;
switch (rw) {
case 0:
- env->exception_index = 0x0a0;
+ cs->exception_index = 0x0a0;
break;
case 1:
- env->exception_index = 0x0c0;
+ cs->exception_index = 0x0c0;
break;
case 2:
- env->exception_index = 0x0a0;
+ cs->exception_index = 0x0a0;
break;
}
return 1;
@@ -89,16 +86,16 @@ void superh_cpu_do_interrupt(CPUState *cs)
SuperHCPU *cpu = SUPERH_CPU(cs);
CPUSH4State *env = &cpu->env;
int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD;
- int do_exp, irq_vector = env->exception_index;
+ int do_exp, irq_vector = cs->exception_index;
/* prioritize exceptions over interrupts */
- do_exp = env->exception_index != -1;
- do_irq = do_irq && (env->exception_index == -1);
+ do_exp = cs->exception_index != -1;
+ do_irq = do_irq && (cs->exception_index == -1);
if (env->sr & SR_BL) {
- if (do_exp && env->exception_index != 0x1e0) {
- env->exception_index = 0x000; /* masked exception -> reset */
+ if (do_exp && cs->exception_index != 0x1e0) {
+ cs->exception_index = 0x000; /* masked exception -> reset */
}
if (do_irq && !env->in_sleep) {
return; /* masked */
@@ -116,7 +113,7 @@ void superh_cpu_do_interrupt(CPUState *cs)
if (qemu_loglevel_mask(CPU_LOG_INT)) {
const char *expname;
- switch (env->exception_index) {
+ switch (cs->exception_index) {
case 0x0e0:
expname = "addr_error";
break;
@@ -180,8 +177,8 @@ void superh_cpu_do_interrupt(CPUState *cs)
env->flags = 0;
if (do_exp) {
- env->expevt = env->exception_index;
- switch (env->exception_index) {
+ env->expevt = cs->exception_index;
+ switch (cs->exception_index) {
case 0x000:
case 0x020:
case 0x140:
@@ -472,33 +469,33 @@ int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
switch (ret) {
case MMU_ITLB_MISS:
case MMU_DTLB_MISS_READ:
- env->exception_index = 0x040;
+ cs->exception_index = 0x040;
break;
case MMU_DTLB_MULTIPLE:
case MMU_ITLB_MULTIPLE:
- env->exception_index = 0x140;
+ cs->exception_index = 0x140;
break;
case MMU_ITLB_VIOLATION:
- env->exception_index = 0x0a0;
+ cs->exception_index = 0x0a0;
break;
case MMU_DTLB_MISS_WRITE:
- env->exception_index = 0x060;
+ cs->exception_index = 0x060;
break;
case MMU_DTLB_INITIAL_WRITE:
- env->exception_index = 0x080;
+ cs->exception_index = 0x080;
break;
case MMU_DTLB_VIOLATION_READ:
- env->exception_index = 0x0a0;
+ cs->exception_index = 0x0a0;
break;
case MMU_DTLB_VIOLATION_WRITE:
- env->exception_index = 0x0c0;
+ cs->exception_index = 0x0c0;
break;
case MMU_IADDR_ERROR:
case MMU_DADDR_ERROR_READ:
- env->exception_index = 0x0e0;
+ cs->exception_index = 0x0e0;
break;
case MMU_DADDR_ERROR_WRITE:
- env->exception_index = 0x100;
+ cs->exception_index = 0x100;
break;
default:
cpu_abort(env, "Unhandled MMU fault");
@@ -702,8 +699,10 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
if (entry->vpn == vpn
&& (!use_asid || entry->asid == asid || entry->sh)) {
if (utlb_match_entry) {
+ CPUState *cs = CPU(sh_env_get_cpu(s));
+
/* Multiple TLB Exception */
- s->exception_index = 0x140;
+ cs->exception_index = 0x140;
s->tea = addr;
break;
}
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 35f9067..03633f0 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -69,7 +69,9 @@ void helper_ldtlb(CPUSH4State *env)
static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
uintptr_t retaddr)
{
- env->exception_index = index;
+ CPUState *cs = CPU(sh_env_get_cpu(env));
+
+ cs->exception_index = index;
if (retaddr) {
cpu_restore_state(env, retaddr);
}
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index 57c20af..a393ef0 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -24,13 +24,17 @@
void helper_raise_exception(CPUSPARCState *env, int tt)
{
- env->exception_index = tt;
+ CPUState *cs = CPU(sparc_env_get_cpu(env));
+
+ cs->exception_index = tt;
cpu_loop_exit(env);
}
void helper_debug(CPUSPARCState *env)
{
- env->exception_index = EXCP_DEBUG;
+ CPUState *cs = CPU(sparc_env_get_cpu(env));
+
+ cs->exception_index = EXCP_DEBUG;
cpu_loop_exit(env);
}
@@ -232,7 +236,7 @@ void helper_power_down(CPUSPARCState *env)
CPUState *cs = CPU(sparc_env_get_cpu(env));
cs->halted = 1;
- env->exception_index = EXCP_HLT;
+ cs->exception_index = EXCP_HLT;
env->pc = env->npc;
env->npc = env->pc + 4;
cpu_loop_exit(env);
diff --git a/target-sparc/int32_helper.c b/target-sparc/int32_helper.c
index d532238..f350a90 100644
--- a/target-sparc/int32_helper.c
+++ b/target-sparc/int32_helper.c
@@ -62,7 +62,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
{
SPARCCPU *cpu = SPARC_CPU(cs);
CPUSPARCState *env = &cpu->env;
- int cwp, intno = env->exception_index;
+ int cwp, intno = cs->exception_index;
/* Compute PSR before exposing state. */
if (env->cc_op != CC_OP_FLAGS) {
@@ -105,12 +105,12 @@ void sparc_cpu_do_interrupt(CPUState *cs)
#endif
#if !defined(CONFIG_USER_ONLY)
if (env->psret == 0) {
- if (env->exception_index == 0x80 &&
+ if (cs->exception_index == 0x80 &&
env->def->features & CPU_FEATURE_TA0_SHUTDOWN) {
qemu_system_shutdown_request();
} else {
cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
- env->exception_index);
+ cs->exception_index);
}
return;
}
@@ -125,7 +125,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
env->pc = env->tbr;
env->npc = env->pc + 4;
- env->exception_index = -1;
+ cs->exception_index = -1;
#if !defined(CONFIG_USER_ONLY)
/* IRQ acknowledgment */
diff --git a/target-sparc/int64_helper.c b/target-sparc/int64_helper.c
index bf7dd86..1744245 100644
--- a/target-sparc/int64_helper.c
+++ b/target-sparc/int64_helper.c
@@ -63,7 +63,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
{
SPARCCPU *cpu = SPARC_CPU(cs);
CPUSPARCState *env = &cpu->env;
- int intno = env->exception_index;
+ int intno = cs->exception_index;
trap_state *tsptr;
/* Compute PSR before exposing state. */
@@ -112,7 +112,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
#if !defined(CONFIG_USER_ONLY)
if (env->tl >= env->maxtl) {
cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
- " Error state", env->exception_index, env->tl, env->maxtl);
+ " Error state", cs->exception_index, env->tl, env->maxtl);
return;
}
#endif
@@ -160,7 +160,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
env->pc = env->tbr;
env->npc = env->pc + 4;
- env->exception_index = -1;
+ cs->exception_index = -1;
}
trap_state *cpu_tsptr(CPUSPARCState* env)
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 2f55af9..af7c289 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -1284,6 +1284,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
int sign)
{
+ CPUState *cs = CPU(sparc_env_get_cpu(env));
uint64_t ret = 0;
#if defined(DEBUG_ASI)
target_ulong last_addr = addr;
@@ -1317,7 +1318,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
dump_asi("read ", last_addr, asi, size, ret);
#endif
/* env->exception_index is set in get_physical_address_data(). */
- helper_raise_exception(env, env->exception_index);
+ helper_raise_exception(env, cs->exception_index);
}
/* convert nonfaulting load ASIs to normal load ASIs */
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index 0d88326..ea72657 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -28,12 +28,10 @@
int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int mmu_idx)
{
- SPARCCPU *cpu = SPARC_CPU(cs);
-
if (rw & 2) {
- cpu->env.exception_index = TT_TFAULT;
+ cs->exception_index = TT_TFAULT;
} else {
- cpu->env.exception_index = TT_DFAULT;
+ cs->exception_index = TT_DFAULT;
}
return 1;
}
@@ -238,9 +236,9 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
return 0;
} else {
if (rw & 2) {
- env->exception_index = TT_TFAULT;
+ cs->exception_index = TT_TFAULT;
} else {
- env->exception_index = TT_DFAULT;
+ cs->exception_index = TT_DFAULT;
}
return 1;
}
@@ -489,6 +487,7 @@ static int get_physical_address_data(CPUSPARCState *env,
hwaddr *physical, int *prot,
target_ulong address, int rw, int mmu_idx)
{
+ CPUState *cs = CPU(sparc_env_get_cpu(env));
unsigned int i;
uint64_t context;
uint64_t sfsr = 0;
@@ -553,10 +552,10 @@ static int get_physical_address_data(CPUSPARCState *env,
if (do_fault) {
/* faults above are reported with TT_DFAULT. */
- env->exception_index = TT_DFAULT;
+ cs->exception_index = TT_DFAULT;
} else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) {
do_fault = 1;
- env->exception_index = TT_DPROT;
+ cs->exception_index = TT_DPROT;
trace_mmu_helper_dprot(address, context, mmu_idx, env->tl);
}
@@ -600,7 +599,7 @@ static int get_physical_address_data(CPUSPARCState *env,
* - JPS1: SFAR updated and some fields of SFSR updated
*/
env->dmmu.tag_access = (address & ~0x1fffULL) | context;
- env->exception_index = TT_DMISS;
+ cs->exception_index = TT_DMISS;
return 1;
}
@@ -608,6 +607,7 @@ static int get_physical_address_code(CPUSPARCState *env,
hwaddr *physical, int *prot,
target_ulong address, int mmu_idx)
{
+ CPUState *cs = CPU(sparc_env_get_cpu(env));
unsigned int i;
uint64_t context;
@@ -651,7 +651,7 @@ static int get_physical_address_code(CPUSPARCState *env,
/* FIXME: ASI field in SFSR must be set */
env->immu.sfsr |= SFSR_FT_PRIV_BIT | SFSR_VALID_BIT;
- env->exception_index = TT_TFAULT;
+ cs->exception_index = TT_TFAULT;
env->immu.tag_access = (address & ~0x1fffULL) | context;
@@ -669,7 +669,7 @@ static int get_physical_address_code(CPUSPARCState *env,
/* Context is stored in DMMU (dmmuregs[1]) also for IMMU */
env->immu.tag_access = (address & ~0x1fffULL) | context;
- env->exception_index = TT_TMISS;
+ cs->exception_index = TT_TMISS;
return 1;
}
diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
index 5cd2378..cd2cbef 100644
--- a/target-unicore32/op_helper.c
+++ b/target-unicore32/op_helper.c
@@ -16,7 +16,9 @@
void HELPER(exception)(CPUUniCore32State *env, uint32_t excp)
{
- env->exception_index = excp;
+ CPUState *cs = CPU(uc32_env_get_cpu(env));
+
+ cs->exception_index = excp;
cpu_loop_exit(env);
}
diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
index 408f1b0..2e26fd1 100644
--- a/target-unicore32/softmmu.c
+++ b/target-unicore32/softmmu.c
@@ -79,7 +79,7 @@ void uc32_cpu_do_interrupt(CPUState *cs)
uint32_t addr;
int new_mode;
- switch (env->exception_index) {
+ switch (cs->exception_index) {
case UC32_EXCP_PRIV:
new_mode = ASR_MODE_PRIV;
addr = 0x08;
@@ -99,7 +99,7 @@ void uc32_cpu_do_interrupt(CPUState *cs)
addr = 0x18;
break;
default:
- cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
+ cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
return;
}
/* High vectors. */
@@ -256,9 +256,9 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
env->cp0.c3_faultstatus = ret;
env->cp0.c4_faultaddr = address;
if (access_type == 2) {
- env->exception_index = UC32_EXCP_ITRAP;
+ cs->exception_index = UC32_EXCP_ITRAP;
} else {
- env->exception_index = UC32_EXCP_DTRAP;
+ cs->exception_index = UC32_EXCP_DTRAP;
}
return ret;
}
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index a0f9993..f55095e 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -169,6 +169,8 @@ static void handle_interrupt(CPUXtensaState *env)
(env->config->level_mask[level] &
env->sregs[INTSET] &
env->sregs[INTENABLE])) {
+ CPUState *cs = CPU(xtensa_env_get_cpu(env));
+
if (level > 1) {
env->sregs[EPC1 + level - 1] = env->pc;
env->sregs[EPS2 + level - 2] = env->sregs[PS];
@@ -185,10 +187,10 @@ static void handle_interrupt(CPUXtensaState *env)
} else {
env->sregs[EPC1] = env->pc;
}
- env->exception_index = EXC_DOUBLE;
+ cs->exception_index = EXC_DOUBLE;
} else {
env->sregs[EPC1] = env->pc;
- env->exception_index =
+ cs->exception_index =
(env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
}
env->sregs[PS] |= PS_EXCM;
@@ -202,7 +204,7 @@ void xtensa_cpu_do_interrupt(CPUState *cs)
XtensaCPU *cpu = XTENSA_CPU(cs);
CPUXtensaState *env = &cpu->env;
- if (env->exception_index == EXC_IRQ) {
+ if (cs->exception_index == EXC_IRQ) {
qemu_log_mask(CPU_LOG_INT,
"%s(EXC_IRQ) level = %d, cintlevel = %d, "
"pc = %08x, a0 = %08x, ps = %08x, "
@@ -215,7 +217,7 @@ void xtensa_cpu_do_interrupt(CPUState *cs)
handle_interrupt(env);
}
- switch (env->exception_index) {
+ switch (cs->exception_index) {
case EXC_WINDOW_OVERFLOW4:
case EXC_WINDOW_UNDERFLOW4:
case EXC_WINDOW_OVERFLOW8:
@@ -228,15 +230,15 @@ void xtensa_cpu_do_interrupt(CPUState *cs)
case EXC_DEBUG:
qemu_log_mask(CPU_LOG_INT, "%s(%d) "
"pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
- __func__, env->exception_index,
+ __func__, cs->exception_index,
env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]);
- if (env->config->exception_vector[env->exception_index]) {
+ if (env->config->exception_vector[cs->exception_index]) {
env->pc = relocated_vector(env,
- env->config->exception_vector[env->exception_index]);
+ env->config->exception_vector[cs->exception_index]);
env->exception_taken = 1;
} else {
qemu_log("%s(pc = %08x) bad exception_index: %d\n",
- __func__, env->pc, env->exception_index);
+ __func__, env->pc, cs->exception_index);
}
break;
@@ -245,7 +247,7 @@ void xtensa_cpu_do_interrupt(CPUState *cs)
default:
qemu_log("%s(pc = %08x) unknown exception_index: %d\n",
- __func__, env->pc, env->exception_index);
+ __func__, env->pc, cs->exception_index);
break;
}
check_interrupts(env);
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index cf97025..2e006e4 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -96,7 +96,9 @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
{
- env->exception_index = excp;
+ CPUState *cs = CPU(xtensa_env_get_cpu(env));
+
+ cs->exception_index = excp;
if (excp == EXCP_DEBUG) {
env->exception_taken = 0;
}
diff --git a/user-exec.c b/user-exec.c
index dec636e..dbb9c8d 100644
--- a/user-exec.c
+++ b/user-exec.c
@@ -41,7 +41,9 @@
static void exception_action(CPUArchState *env1)
{
#if defined(TARGET_I386)
- raise_exception_err(env1, env1->exception_index, env1->error_code);
+ CPUState *cpu = ENV_GET_CPU(env1);
+
+ raise_exception_err(env1, cpu->exception_index, env1->error_code);
#else
cpu_loop_exit(env1);
#endif
@@ -71,7 +73,7 @@ void cpu_resume_from_signal(CPUArchState *env1, void *puc)
sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
#endif
}
- env1->exception_index = -1;
+ cpu->exception_index = -1;
siglongjmp(cpu->jmp_env, 1);
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 11/41] cpu: Move exception_index field from CPU_COMMON to CPUState
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 11/41] cpu: Move exception_index " Andreas Färber
@ 2013-09-04 12:47 ` Jia Liu
0 siblings, 0 replies; 68+ messages in thread
From: Jia Liu @ 2013-09-04 12:47 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Anthony Green, Riku Voipio, qemu-devel@nongnu.org,
Alexander Graf, Blue Swirl, Max Filippov, Michael Walle,
open list:e500, Paul Brook, Scott Wood, Edgar E. Iglesias,
Guan Xuetao, Aurelien Jarno, Richard Henderson
On Wed, Sep 4, 2013 at 5:04 PM, Andreas Färber <afaerber@suse.de> wrote:
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
> cpu-exec.c | 50 +++++++++++++++++++++---------------------
> exec.c | 2 +-
> hw/ppc/e500.c | 3 +--
> hw/ppc/ppce500_spin.c | 2 +-
> hw/ppc/spapr_hcall.c | 2 +-
> hw/s390x/s390-virtio.c | 8 +++----
> include/exec/cpu-defs.h | 3 ---
> include/qom/cpu.h | 1 +
> linux-user/signal.c | 7 +++---
> target-alpha/helper.c | 18 ++++++++++-----
> target-alpha/mem_helper.c | 4 +++-
> target-arm/helper.c | 25 ++++++++++-----------
> target-arm/op_helper.c | 16 +++++++++-----
> target-cris/helper.c | 18 +++++++--------
> target-cris/op_helper.c | 6 +++--
> target-i386/excp_helper.c | 4 +++-
> target-i386/helper.c | 6 ++---
> target-i386/mem_helper.c | 5 +++--
> target-i386/misc_helper.c | 6 +++--
> target-i386/seg_helper.c | 8 ++++---
> target-i386/svm_helper.c | 13 ++++++-----
> target-lm32/helper.c | 12 +++++-----
> target-lm32/op_helper.c | 6 +++--
> target-m68k/helper.c | 2 +-
> target-m68k/op_helper.c | 22 +++++++++----------
> target-m68k/qregs.def | 1 -
> target-m68k/translate.c | 5 +++++
> target-microblaze/helper.c | 16 ++++++--------
> target-microblaze/op_helper.c | 4 +++-
> target-mips/helper.c | 31 ++++++++++++++------------
> target-mips/op_helper.c | 9 +++++---
> target-mips/translate.c | 4 +---
> target-moxie/helper.c | 21 ++++++++++--------
> target-openrisc/cpu.c | 2 +-
> target-openrisc/exception.c | 4 +++-
> target-openrisc/interrupt.c | 27 ++++++++++++-----------
> target-openrisc/mmu.c | 3 ++-
> target-ppc/excp_helper.c | 19 +++++++++-------
> target-ppc/fpu_helper.c | 26 +++++++++++++++-------
> target-ppc/mmu-hash32.c | 24 ++++++++++----------
> target-ppc/mmu-hash64.c | 15 +++++++------
> target-ppc/mmu_helper.c | 43 ++++++++++++++++++------------------
> target-ppc/translate_init.c | 2 +-
> target-ppc/user_only_helper.c | 2 +-
> target-s390x/helper.c | 39 ++++++++++++++++-----------------
> target-s390x/mem_helper.c | 9 ++++----
> target-s390x/misc_helper.c | 15 +++++++++----
> target-sh4/helper.c | 51 +++++++++++++++++++++----------------------
> target-sh4/op_helper.c | 4 +++-
> target-sparc/helper.c | 10 ++++++---
> target-sparc/int32_helper.c | 8 +++----
> target-sparc/int64_helper.c | 6 ++---
> target-sparc/ldst_helper.c | 3 ++-
> target-sparc/mmu_helper.c | 22 +++++++++----------
> target-unicore32/op_helper.c | 4 +++-
> target-unicore32/softmmu.c | 8 +++----
> target-xtensa/helper.c | 20 +++++++++--------
> target-xtensa/op_helper.c | 4 +++-
> user-exec.c | 6 +++--
> 59 files changed, 393 insertions(+), 323 deletions(-)
>
> diff --git a/cpu-exec.c b/cpu-exec.c
> index 39e4f8b..0081eaf 100644
> --- a/cpu-exec.c
> +++ b/cpu-exec.c
> @@ -41,7 +41,7 @@ void cpu_resume_from_signal(CPUArchState *env, void *puc)
>
> /* XXX: restore cpu registers saved in host registers */
>
> - env->exception_index = -1;
> + cpu->exception_index = -1;
> siglongjmp(cpu->jmp_env, 1);
> }
> #endif
> @@ -262,16 +262,16 @@ int cpu_exec(CPUArchState *env)
> #else
> #error unsupported target CPU
> #endif
> - env->exception_index = -1;
> + cpu->exception_index = -1;
>
> /* prepare setjmp context for exception handling */
> for(;;) {
> if (sigsetjmp(cpu->jmp_env, 0) == 0) {
> /* if an exception is pending, we execute it here */
> - if (env->exception_index >= 0) {
> - if (env->exception_index >= EXCP_INTERRUPT) {
> + if (cpu->exception_index >= 0) {
> + if (cpu->exception_index >= EXCP_INTERRUPT) {
> /* exit request from the cpu execution loop */
> - ret = env->exception_index;
> + ret = cpu->exception_index;
> if (ret == EXCP_DEBUG) {
> cpu_handle_debug_exception(env);
> }
> @@ -284,11 +284,11 @@ int cpu_exec(CPUArchState *env)
> #if defined(TARGET_I386)
> cc->do_interrupt(cpu);
> #endif
> - ret = env->exception_index;
> + ret = cpu->exception_index;
> break;
> #else
> cc->do_interrupt(cpu);
> - env->exception_index = -1;
> + cpu->exception_index = -1;
> #endif
> }
> }
> @@ -303,7 +303,7 @@ int cpu_exec(CPUArchState *env)
> }
> if (interrupt_request & CPU_INTERRUPT_DEBUG) {
> cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
> - env->exception_index = EXCP_DEBUG;
> + cpu->exception_index = EXCP_DEBUG;
> cpu_loop_exit(env);
> }
> #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
> @@ -312,7 +312,7 @@ int cpu_exec(CPUArchState *env)
> if (interrupt_request & CPU_INTERRUPT_HALT) {
> cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
> cpu->halted = 1;
> - env->exception_index = EXCP_HLT;
> + cpu->exception_index = EXCP_HLT;
> cpu_loop_exit(env);
> }
> #endif
> @@ -327,7 +327,7 @@ int cpu_exec(CPUArchState *env)
> cpu_svm_check_intercept_param(env, SVM_EXIT_INIT,
> 0);
> do_cpu_init(x86_env_get_cpu(env));
> - env->exception_index = EXCP_HALTED;
> + cpu->exception_index = EXCP_HALTED;
> cpu_loop_exit(env);
> } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
> do_cpu_sipi(x86_env_get_cpu(env));
> @@ -396,7 +396,7 @@ int cpu_exec(CPUArchState *env)
> #elif defined(TARGET_LM32)
> if ((interrupt_request & CPU_INTERRUPT_HARD)
> && (env->ie & IE_IE)) {
> - env->exception_index = EXCP_IRQ;
> + cpu->exception_index = EXCP_IRQ;
> cc->do_interrupt(cpu);
> next_tb = 0;
> }
> @@ -405,7 +405,7 @@ int cpu_exec(CPUArchState *env)
> && (env->sregs[SR_MSR] & MSR_IE)
> && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
> && !(env->iflags & (D_FLAG | IMM_FLAG))) {
> - env->exception_index = EXCP_IRQ;
> + cpu->exception_index = EXCP_IRQ;
> cc->do_interrupt(cpu);
> next_tb = 0;
> }
> @@ -413,7 +413,7 @@ int cpu_exec(CPUArchState *env)
> if ((interrupt_request & CPU_INTERRUPT_HARD) &&
> cpu_mips_hw_interrupts_pending(env)) {
> /* Raise it */
> - env->exception_index = EXCP_EXT_INTERRUPT;
> + cpu->exception_index = EXCP_EXT_INTERRUPT;
> env->error_code = 0;
> cc->do_interrupt(cpu);
> next_tb = 0;
> @@ -430,7 +430,7 @@ int cpu_exec(CPUArchState *env)
> idx = EXCP_TICK;
> }
> if (idx >= 0) {
> - env->exception_index = idx;
> + cpu->exception_index = idx;
> cc->do_interrupt(cpu);
> next_tb = 0;
> }
> @@ -445,7 +445,7 @@ int cpu_exec(CPUArchState *env)
> if (((type == TT_EXTINT) &&
> cpu_pil_allowed(env, pil)) ||
> type != TT_EXTINT) {
> - env->exception_index = env->interrupt_index;
> + cpu->exception_index = env->interrupt_index;
> cc->do_interrupt(cpu);
> next_tb = 0;
> }
> @@ -454,7 +454,7 @@ int cpu_exec(CPUArchState *env)
> #elif defined(TARGET_ARM)
> if (interrupt_request & CPU_INTERRUPT_FIQ
> && !(env->uncached_cpsr & CPSR_F)) {
> - env->exception_index = EXCP_FIQ;
> + cpu->exception_index = EXCP_FIQ;
> cc->do_interrupt(cpu);
> next_tb = 0;
> }
> @@ -470,14 +470,14 @@ int cpu_exec(CPUArchState *env)
> if (interrupt_request & CPU_INTERRUPT_HARD
> && ((IS_M(env) && env->regs[15] < 0xfffffff0)
> || !(env->uncached_cpsr & CPSR_I))) {
> - env->exception_index = EXCP_IRQ;
> + cpu->exception_index = EXCP_IRQ;
> cc->do_interrupt(cpu);
> next_tb = 0;
> }
> #elif defined(TARGET_UNICORE32)
> if (interrupt_request & CPU_INTERRUPT_HARD
> && !(env->uncached_asr & ASR_I)) {
> - env->exception_index = UC32_EXCP_INTR;
> + cpu->exception_index = UC32_EXCP_INTR;
> cc->do_interrupt(cpu);
> next_tb = 0;
> }
> @@ -512,7 +512,7 @@ int cpu_exec(CPUArchState *env)
> }
> }
> if (idx >= 0) {
> - env->exception_index = idx;
> + cpu->exception_index = idx;
> env->error_code = 0;
> cc->do_interrupt(cpu);
> next_tb = 0;
> @@ -522,7 +522,7 @@ int cpu_exec(CPUArchState *env)
> if (interrupt_request & CPU_INTERRUPT_HARD
> && (env->pregs[PR_CCS] & I_FLAG)
> && !env->locked_irq) {
> - env->exception_index = EXCP_IRQ;
> + cpu->exception_index = EXCP_IRQ;
> cc->do_interrupt(cpu);
> next_tb = 0;
> }
> @@ -534,7 +534,7 @@ int cpu_exec(CPUArchState *env)
> m_flag_archval = M_FLAG_V32;
> }
> if ((env->pregs[PR_CCS] & m_flag_archval)) {
> - env->exception_index = EXCP_NMI;
> + cpu->exception_index = EXCP_NMI;
> cc->do_interrupt(cpu);
> next_tb = 0;
> }
> @@ -548,7 +548,7 @@ int cpu_exec(CPUArchState *env)
> hardware doesn't rely on this, so we
> provide/save the vector when the interrupt is
> first signalled. */
> - env->exception_index = env->pending_vector;
> + cpu->exception_index = env->pending_vector;
> do_interrupt_m68k_hardirq(env);
> next_tb = 0;
> }
> @@ -560,7 +560,7 @@ int cpu_exec(CPUArchState *env)
> }
> #elif defined(TARGET_XTENSA)
> if (interrupt_request & CPU_INTERRUPT_HARD) {
> - env->exception_index = EXC_IRQ;
> + cpu->exception_index = EXC_IRQ;
> cc->do_interrupt(cpu);
> next_tb = 0;
> }
> @@ -576,7 +576,7 @@ int cpu_exec(CPUArchState *env)
> }
> if (unlikely(cpu->exit_request)) {
> cpu->exit_request = 0;
> - env->exception_index = EXCP_INTERRUPT;
> + cpu->exception_index = EXCP_INTERRUPT;
> cpu_loop_exit(env);
> }
> #if defined(DEBUG_DISAS)
> @@ -662,7 +662,7 @@ int cpu_exec(CPUArchState *env)
> /* Execute remaining instructions. */
> cpu_exec_nocache(env, insns_left, tb);
> }
> - env->exception_index = EXCP_INTERRUPT;
> + cpu->exception_index = EXCP_INTERRUPT;
> next_tb = 0;
> cpu_loop_exit(env);
> }
> diff --git a/exec.c b/exec.c
> index 00c44ea..508f1e2 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -1502,7 +1502,7 @@ static void check_watchpoint(int offset, int len_mask, int flags)
> env->watchpoint_hit = wp;
> tb_check_watchpoint(env);
> if (wp->flags & BP_STOP_BEFORE_ACCESS) {
> - env->exception_index = EXCP_DEBUG;
> + cpu->exception_index = EXCP_DEBUG;
> cpu_loop_exit(env);
> } else {
> cc->get_tb_cpu_state(cpu, &pc, &cs_base, &cpu_flags);
> diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
> index cfdd84b..2d1d478 100644
> --- a/hw/ppc/e500.c
> +++ b/hw/ppc/e500.c
> @@ -468,14 +468,13 @@ static void ppce500_cpu_reset_sec(void *opaque)
> {
> PowerPCCPU *cpu = opaque;
> CPUState *cs = CPU(cpu);
> - CPUPPCState *env = &cpu->env;
>
> cpu_reset(cs);
>
> /* Secondary CPU starts in halted state for now. Needs to change when
> implementing non-kernel boot. */
> cs->halted = 1;
> - env->exception_index = EXCP_HLT;
> + cs->exception_index = EXCP_HLT;
> }
>
> static void ppce500_cpu_reset(void *opaque)
> diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c
> index 78b23fa..f9fdc8c 100644
> --- a/hw/ppc/ppce500_spin.c
> +++ b/hw/ppc/ppce500_spin.c
> @@ -117,7 +117,7 @@ static void spin_kick(void *data)
> mmubooke_create_initial_mapping(env, 0, map_start, map_size);
>
> cpu->halted = 0;
> - env->exception_index = -1;
> + cpu->exception_index = -1;
> cpu->stopped = false;
> qemu_cpu_kick(cpu);
> }
> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> index f10ba8a..d4aa4ea 100644
> --- a/hw/ppc/spapr_hcall.c
> +++ b/hw/ppc/spapr_hcall.c
> @@ -511,7 +511,7 @@ static target_ulong h_cede(PowerPCCPU *cpu, sPAPREnvironment *spapr,
> hreg_compute_hflags(env);
> if (!cpu_has_work(cs)) {
> cs->halted = 1;
> - env->exception_index = EXCP_HLT;
> + cs->exception_index = EXCP_HLT;
> cs->exit_request = 1;
> }
> return H_SUCCESS;
> diff --git a/hw/s390x/s390-virtio.c b/hw/s390x/s390-virtio.c
> index 7adf92a..393f3c8 100644
> --- a/hw/s390x/s390-virtio.c
> +++ b/hw/s390x/s390-virtio.c
> @@ -134,25 +134,23 @@ static unsigned s390_running_cpus;
> void s390_add_running_cpu(S390CPU *cpu)
> {
> CPUState *cs = CPU(cpu);
> - CPUS390XState *env = &cpu->env;
>
> if (cs->halted) {
> s390_running_cpus++;
> cs->halted = 0;
> - env->exception_index = -1;
> + cs->exception_index = -1;
> }
> }
>
> unsigned s390_del_running_cpu(S390CPU *cpu)
> {
> CPUState *cs = CPU(cpu);
> - CPUS390XState *env = &cpu->env;
>
> if (cs->halted == 0) {
> assert(s390_running_cpus >= 1);
> s390_running_cpus--;
> cs->halted = 1;
> - env->exception_index = EXCP_HLT;
> + cs->exception_index = EXCP_HLT;
> }
> return s390_running_cpus;
> }
> @@ -195,7 +193,7 @@ void s390_init_cpus(const char *cpu_model, uint8_t *storage_keys)
>
> ipi_states[i] = cpu;
> cs->halted = 1;
> - cpu->env.exception_index = EXCP_HLT;
> + cs->exception_index = EXCP_HLT;
> cpu->env.storage_keys = storage_keys;
> }
> }
> diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
> index d000a5e..6801968 100644
> --- a/include/exec/cpu-defs.h
> +++ b/include/exec/cpu-defs.h
> @@ -138,9 +138,6 @@ typedef struct CPUWatchpoint {
> QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
> CPUWatchpoint *watchpoint_hit; \
> \
> - /* Core interrupt code */ \
> - int exception_index; \
> - \
> /* user data */ \
> void *opaque; \
> \
> diff --git a/include/qom/cpu.h b/include/qom/cpu.h
> index 288ffa9..8191a80 100644
> --- a/include/qom/cpu.h
> +++ b/include/qom/cpu.h
> @@ -249,6 +249,7 @@ struct CPUState {
> icount_decr_u16 u16;
> } icount_decr;
> uint32_t can_do_io;
> + int32_t exception_index; /* used by m68k TCG */
> };
>
> QTAILQ_HEAD(CPUTailQ, CPUState);
> diff --git a/linux-user/signal.c b/linux-user/signal.c
> index 23d65da..6e51519 100644
> --- a/linux-user/signal.c
> +++ b/linux-user/signal.c
> @@ -773,8 +773,9 @@ static int
> setup_sigcontext(struct target_sigcontext *sc, struct target_fpstate *fpstate,
> CPUX86State *env, abi_ulong mask, abi_ulong fpstate_addr)
> {
> - int err = 0;
> - uint16_t magic;
> + CPUState *cs = CPU(x86_env_get_cpu(env));
> + int err = 0;
> + uint16_t magic;
>
> /* already locked in setup_frame() */
> err |= __put_user(env->segs[R_GS].selector, (unsigned int *)&sc->gs);
> @@ -789,7 +790,7 @@ setup_sigcontext(struct target_sigcontext *sc, struct target_fpstate *fpstate,
> err |= __put_user(env->regs[R_EDX], &sc->edx);
> err |= __put_user(env->regs[R_ECX], &sc->ecx);
> err |= __put_user(env->regs[R_EAX], &sc->eax);
> - err |= __put_user(env->exception_index, &sc->trapno);
> + err |= __put_user(cs->exception_index, &sc->trapno);
> err |= __put_user(env->error_code, &sc->err);
> err |= __put_user(env->eip, &sc->eip);
> err |= __put_user(env->segs[R_CS].selector, (unsigned int *)&sc->cs);
> diff --git a/target-alpha/helper.c b/target-alpha/helper.c
> index ef2dc25..6f103ec 100644
> --- a/target-alpha/helper.c
> +++ b/target-alpha/helper.c
> @@ -173,7 +173,7 @@ int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> {
> AlphaCPU *cpu = ALPHA_CPU(cs);
>
> - cpu->env.exception_index = EXCP_MMFAULT;
> + cs->exception_index = EXCP_MMFAULT;
> cpu->env.trap_arg0 = address;
> return 1;
> }
> @@ -337,7 +337,7 @@ int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int rw,
>
> fail = get_physical_address(env, addr, 1 << rw, mmu_idx, &phys, &prot);
> if (unlikely(fail >= 0)) {
> - env->exception_index = EXCP_MMFAULT;
> + cs->exception_index = EXCP_MMFAULT;
> env->trap_arg0 = addr;
> env->trap_arg1 = fail;
> env->trap_arg2 = (rw == 2 ? -1 : rw);
> @@ -354,7 +354,7 @@ void alpha_cpu_do_interrupt(CPUState *cs)
> {
> AlphaCPU *cpu = ALPHA_CPU(cs);
> CPUAlphaState *env = &cpu->env;
> - int i = env->exception_index;
> + int i = cs->exception_index;
>
> if (qemu_loglevel_mask(CPU_LOG_INT)) {
> static int count;
> @@ -405,7 +405,7 @@ void alpha_cpu_do_interrupt(CPUState *cs)
> ++count, name, env->error_code, env->pc, env->ir[IR_SP]);
> }
>
> - env->exception_index = -1;
> + cs->exception_index = -1;
>
> #if !defined(CONFIG_USER_ONLY)
> switch (i) {
> @@ -507,7 +507,10 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
> We expect that ENV->PC has already been updated. */
> void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error)
> {
> - env->exception_index = excp;
> + AlphaCPU *cpu = alpha_env_get_cpu(env);
> + CPUState *cs = CPU(cpu);
> +
> + cs->exception_index = excp;
> env->error_code = error;
> cpu_loop_exit(env);
> }
> @@ -516,7 +519,10 @@ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error)
> void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr,
> int excp, int error)
> {
> - env->exception_index = excp;
> + AlphaCPU *cpu = alpha_env_get_cpu(env);
> + CPUState *cs = CPU(cpu);
> +
> + cs->exception_index = excp;
> env->error_code = error;
> if (retaddr) {
> cpu_restore_state(env, retaddr);
> diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
> index d140688..22fcbe1 100644
> --- a/target-alpha/mem_helper.c
> +++ b/target-alpha/mem_helper.c
> @@ -91,6 +91,8 @@ uint64_t helper_stq_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
> static void do_unaligned_access(CPUAlphaState *env, target_ulong addr,
> int is_write, int is_user, uintptr_t retaddr)
> {
> + AlphaCPU *cpu = alpha_env_get_cpu(env);
> + CPUState *cs = CPU(cpu);
> uint64_t pc;
> uint32_t insn;
>
> @@ -104,7 +106,7 @@ static void do_unaligned_access(CPUAlphaState *env, target_ulong addr,
> env->trap_arg0 = addr;
> env->trap_arg1 = insn >> 26; /* opcode */
> env->trap_arg2 = (insn >> 21) & 31; /* dest regno */
> - env->exception_index = EXCP_UNALIGN;
> + cs->exception_index = EXCP_UNALIGN;
> env->error_code = 0;
> cpu_loop_exit(env);
> }
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 9d0d8b4..508a7fc 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2072,10 +2072,7 @@ uint32_t HELPER(rbit)(uint32_t x)
>
> void arm_cpu_do_interrupt(CPUState *cs)
> {
> - ARMCPU *cpu = ARM_CPU(cs);
> - CPUARMState *env = &cpu->env;
> -
> - env->exception_index = -1;
> + cs->exception_index = -1;
> }
>
> int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> @@ -2085,10 +2082,10 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> CPUARMState *env = &cpu->env;
>
> if (rw == 2) {
> - env->exception_index = EXCP_PREFETCH_ABORT;
> + cs->exception_index = EXCP_PREFETCH_ABORT;
> env->cp15.c6_insn = address;
> } else {
> - env->exception_index = EXCP_DATA_ABORT;
> + cs->exception_index = EXCP_DATA_ABORT;
> env->cp15.c6_data = address;
> }
> return 1;
> @@ -2270,7 +2267,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
> uint32_t lr;
> uint32_t addr;
>
> - arm_log_exception(env->exception_index);
> + arm_log_exception(cs->exception_index);
>
> lr = 0xfffffff1;
> if (env->v7m.current_sp)
> @@ -2282,7 +2279,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
> handle it. */
> /* TODO: Need to escalate if the current priority is higher than the
> one we're raising. */
> - switch (env->exception_index) {
> + switch (cs->exception_index) {
> case EXCP_UDEF:
> armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
> return;
> @@ -2314,7 +2311,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
> do_v7m_exception_exit(env);
> return;
> default:
> - cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
> + cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
> return; /* Never happens. Keep compiler happy. */
> }
>
> @@ -2355,10 +2352,10 @@ void arm_cpu_do_interrupt(CPUState *cs)
>
> assert(!IS_M(env));
>
> - arm_log_exception(env->exception_index);
> + arm_log_exception(cs->exception_index);
>
> /* TODO: Vectored interrupt controller. */
> - switch (env->exception_index) {
> + switch (cs->exception_index) {
> case EXCP_UDEF:
> new_mode = ARM_CPU_MODE_UND;
> addr = 0x04;
> @@ -2439,7 +2436,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
> offset = 4;
> break;
> default:
> - cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
> + cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
> return; /* Never happens. Keep compiler happy. */
> }
> /* High vectors. */
> @@ -3053,13 +3050,13 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> if (access_type == 2) {
> env->cp15.c5_insn = ret;
> env->cp15.c6_insn = address;
> - env->exception_index = EXCP_PREFETCH_ABORT;
> + cs->exception_index = EXCP_PREFETCH_ABORT;
> } else {
> env->cp15.c5_data = ret;
> if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
> env->cp15.c5_data |= (1 << 11);
> env->cp15.c6_data = address;
> - env->exception_index = EXCP_DATA_ABORT;
> + cs->exception_index = EXCP_DATA_ABORT;
> }
> return 1;
> }
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index 13d34fb..2c2b3b7 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -24,7 +24,10 @@
>
> static void raise_exception(CPUARMState *env, int tt)
> {
> - env->exception_index = tt;
> + ARMCPU *cpu = arm_env_get_cpu(env);
> + CPUState *cs = CPU(cpu);
> +
> + cs->exception_index = tt;
> cpu_loop_exit(env);
> }
>
> @@ -75,15 +78,16 @@ void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> ARMCPU *cpu = arm_env_get_cpu(env);
> + CPUState *cs = CPU(cpu);
> int ret;
>
> - ret = arm_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> + ret = arm_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> if (retaddr) {
> /* now we have a real cpu fault */
> cpu_restore_state(env, retaddr);
> }
> - raise_exception(env, env->exception_index);
> + raise_exception(env, cs->exception_index);
> }
> }
> #endif
> @@ -221,14 +225,16 @@ void HELPER(wfi)(CPUARMState *env)
> {
> CPUState *cs = CPU(arm_env_get_cpu(env));
>
> - env->exception_index = EXCP_HLT;
> + cs->exception_index = EXCP_HLT;
> cs->halted = 1;
> cpu_loop_exit(env);
> }
>
> void HELPER(exception)(CPUARMState *env, uint32_t excp)
> {
> - env->exception_index = excp;
> + CPUState *cs = CPU(arm_env_get_cpu(env));
> +
> + cs->exception_index = excp;
> cpu_loop_exit(env);
> }
>
> diff --git a/target-cris/helper.c b/target-cris/helper.c
> index 72dc839..3c4501c 100644
> --- a/target-cris/helper.c
> +++ b/target-cris/helper.c
> @@ -41,7 +41,7 @@ void cris_cpu_do_interrupt(CPUState *cs)
> CRISCPU *cpu = CRIS_CPU(cs);
> CPUCRISState *env = &cpu->env;
>
> - env->exception_index = -1;
> + cs->exception_index = -1;
> env->pregs[PR_ERP] = env->pc;
> }
>
> @@ -55,7 +55,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> {
> CRISCPU *cpu = CRIS_CPU(cs);
>
> - cpu->env.exception_index = 0xaa;
> + cs->exception_index = 0xaa;
> cpu->env.pregs[PR_EDA] = address;
> cpu_dump_state(cs, stderr, fprintf, 0);
> return 1;
> @@ -88,7 +88,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
> rw, mmu_idx, 0);
> if (miss) {
> - if (env->exception_index == EXCP_BUSFAULT) {
> + if (cs->exception_index == EXCP_BUSFAULT) {
> cpu_abort(env,
> "CRIS: Illegal recursive bus fault."
> "addr=%" VADDR_PRIx " rw=%d\n",
> @@ -96,7 +96,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> }
>
> env->pregs[PR_EDA] = address;
> - env->exception_index = EXCP_BUSFAULT;
> + cs->exception_index = EXCP_BUSFAULT;
> env->fault_vector = res.bf_vec;
> r = 1;
> } else {
> @@ -125,11 +125,11 @@ void crisv10_cpu_do_interrupt(CPUState *cs)
> int ex_vec = -1;
>
> D_LOG("exception index=%d interrupt_req=%d\n",
> - env->exception_index,
> + cs->exception_index,
> cs->interrupt_request);
>
> assert(!(env->pregs[PR_CCS] & PFIX_FLAG));
> - switch (env->exception_index) {
> + switch (cs->exception_index) {
> case EXCP_BREAK:
> /* These exceptions are genereated by the core itself.
> ERP should point to the insn following the brk. */
> @@ -182,10 +182,10 @@ void cris_cpu_do_interrupt(CPUState *cs)
> int ex_vec = -1;
>
> D_LOG("exception index=%d interrupt_req=%d\n",
> - env->exception_index,
> + cs->exception_index,
> cs->interrupt_request);
>
> - switch (env->exception_index) {
> + switch (cs->exception_index) {
> case EXCP_BREAK:
> /* These exceptions are genereated by the core itself.
> ERP should point to the insn following the brk. */
> @@ -248,7 +248,7 @@ void cris_cpu_do_interrupt(CPUState *cs)
>
> /* Clear the excption_index to avoid spurios hw_aborts for recursive
> bus faults. */
> - env->exception_index = -1;
> + cs->exception_index = -1;
>
> D_LOG("%s isr=%x vec=%x ccs=%x pid=%d erp=%x\n",
> __func__, env->pc, ex_vec,
> diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
> index 4a6215d..9b20b94 100644
> --- a/target-cris/op_helper.c
> +++ b/target-cris/op_helper.c
> @@ -79,8 +79,10 @@ void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx,
>
> void helper_raise_exception(CPUCRISState *env, uint32_t index)
> {
> - env->exception_index = index;
> - cpu_loop_exit(env);
> + CPUState *cs = CPU(cris_env_get_cpu(env));
> +
> + cs->exception_index = index;
> + cpu_loop_exit(env);
> }
>
> void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
> diff --git a/target-i386/excp_helper.c b/target-i386/excp_helper.c
> index 5319aef..ec76eba 100644
> --- a/target-i386/excp_helper.c
> +++ b/target-i386/excp_helper.c
> @@ -94,6 +94,8 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno,
> int is_int, int error_code,
> int next_eip_addend)
> {
> + CPUState *cs = CPU(x86_env_get_cpu(env));
> +
> if (!is_int) {
> cpu_svm_check_intercept_param(env, SVM_EXIT_EXCP_BASE + intno,
> error_code);
> @@ -102,7 +104,7 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno,
> cpu_svm_check_intercept_param(env, SVM_EXIT_SWINT, 0);
> }
>
> - env->exception_index = intno;
> + cs->exception_index = intno;
> env->error_code = error_code;
> env->exception_is_int = is_int;
> env->exception_next_eip = env->eip + next_eip_addend;
> diff --git a/target-i386/helper.c b/target-i386/helper.c
> index 8c2ad94..864d9f8 100644
> --- a/target-i386/helper.c
> +++ b/target-i386/helper.c
> @@ -496,7 +496,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
> env->cr[2] = addr;
> env->error_code = (is_write << PG_ERROR_W_BIT);
> env->error_code |= PG_ERROR_U_MASK;
> - env->exception_index = EXCP0E_PAGE;
> + cs->exception_index = EXCP0E_PAGE;
> return 1;
> }
>
> @@ -555,7 +555,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
> sext = (int64_t)addr >> 47;
> if (sext != 0 && sext != -1) {
> env->error_code = 0;
> - env->exception_index = EXCP0D_GPF;
> + cs->exception_index = EXCP0D_GPF;
> return 1;
> }
>
> @@ -885,7 +885,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
> env->cr[2] = addr;
> }
> env->error_code = error_code;
> - env->exception_index = EXCP0E_PAGE;
> + cs->exception_index = EXCP0E_PAGE;
> return 1;
> }
>
> diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c
> index 5b25ccd..c0d3b45 100644
> --- a/target-i386/mem_helper.c
> +++ b/target-i386/mem_helper.c
> @@ -136,15 +136,16 @@ void tlb_fill(CPUX86State *env, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> X86CPU *cpu = x86_env_get_cpu(env);
> + CPUState *cs = CPU(cpu);
> int ret;
>
> - ret = x86_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> + ret = x86_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (ret) {
> if (retaddr) {
> /* now we have a real cpu fault */
> cpu_restore_state(env, retaddr);
> }
> - raise_exception_err(env, env->exception_index, env->error_code);
> + raise_exception_err(env, cs->exception_index, env->error_code);
> }
> }
> #endif
> diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c
> index 93933fd..a058c43 100644
> --- a/target-i386/misc_helper.c
> +++ b/target-i386/misc_helper.c
> @@ -573,7 +573,7 @@ static void do_hlt(X86CPU *cpu)
>
> env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
> cs->halted = 1;
> - env->exception_index = EXCP_HLT;
> + cs->exception_index = EXCP_HLT;
> cpu_loop_exit(env);
> }
>
> @@ -620,6 +620,8 @@ void helper_mwait(CPUX86State *env, int next_eip_addend)
>
> void helper_debug(CPUX86State *env)
> {
> - env->exception_index = EXCP_DEBUG;
> + CPUState *cs = CPU(x86_env_get_cpu(env));
> +
> + cs->exception_index = EXCP_DEBUG;
> cpu_loop_exit(env);
> }
> diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
> index e789102..b689e94 100644
> --- a/target-i386/seg_helper.c
> +++ b/target-i386/seg_helper.c
> @@ -935,7 +935,9 @@ static void do_interrupt64(CPUX86State *env, int intno, int is_int,
> #if defined(CONFIG_USER_ONLY)
> void helper_syscall(CPUX86State *env, int next_eip_addend)
> {
> - env->exception_index = EXCP_SYSCALL;
> + CPUState *cs = CPU(x86_env_get_cpu(env));
> +
> + cs->exception_index = EXCP_SYSCALL;
> env->exception_next_eip = env->eip + next_eip_addend;
> cpu_loop_exit(env);
> }
> @@ -1244,7 +1246,7 @@ void x86_cpu_do_interrupt(CPUState *cs)
> /* if user mode only, we simulate a fake exception
> which will be handled outside the cpu execution
> loop */
> - do_interrupt_user(env, env->exception_index,
> + do_interrupt_user(env, cs->exception_index,
> env->exception_is_int,
> env->error_code,
> env->exception_next_eip);
> @@ -1254,7 +1256,7 @@ void x86_cpu_do_interrupt(CPUState *cs)
> /* simulate a real cpu exception. On i386, it can
> trigger new exceptions, but we do not handle
> double or triple faults yet. */
> - do_interrupt_all(cpu, env->exception_index,
> + do_interrupt_all(cpu, cs->exception_index,
> env->exception_is_int,
> env->error_code,
> env->exception_next_eip, 0);
> diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
> index 4a7de42..3c12cb8 100644
> --- a/target-i386/svm_helper.c
> +++ b/target-i386/svm_helper.c
> @@ -122,6 +122,7 @@ static inline void svm_load_seg_cache(CPUX86State *env, hwaddr addr,
>
> void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
> {
> + CPUState *cs = CPU(x86_env_get_cpu(env));
> target_ulong addr;
> uint32_t event_inj;
> uint32_t int_ctl;
> @@ -290,7 +291,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
> /* FIXME: need to implement valid_err */
> switch (event_inj & SVM_EVTINJ_TYPE_MASK) {
> case SVM_EVTINJ_TYPE_INTR:
> - env->exception_index = vector;
> + cs->exception_index = vector;
> env->error_code = event_inj_err;
> env->exception_is_int = 0;
> env->exception_next_eip = -1;
> @@ -299,7 +300,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
> do_interrupt_x86_hardirq(env, vector, 1);
> break;
> case SVM_EVTINJ_TYPE_NMI:
> - env->exception_index = EXCP02_NMI;
> + cs->exception_index = EXCP02_NMI;
> env->error_code = event_inj_err;
> env->exception_is_int = 0;
> env->exception_next_eip = env->eip;
> @@ -307,7 +308,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
> cpu_loop_exit(env);
> break;
> case SVM_EVTINJ_TYPE_EXEPT:
> - env->exception_index = vector;
> + cs->exception_index = vector;
> env->error_code = event_inj_err;
> env->exception_is_int = 0;
> env->exception_next_eip = -1;
> @@ -315,7 +316,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
> cpu_loop_exit(env);
> break;
> case SVM_EVTINJ_TYPE_SOFT:
> - env->exception_index = vector;
> + cs->exception_index = vector;
> env->error_code = event_inj_err;
> env->exception_is_int = 1;
> env->exception_next_eip = env->eip;
> @@ -323,7 +324,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
> cpu_loop_exit(env);
> break;
> }
> - qemu_log_mask(CPU_LOG_TB_IN_ASM, " %#x %#x\n", env->exception_index,
> + qemu_log_mask(CPU_LOG_TB_IN_ASM, " %#x %#x\n", cs->exception_index,
> env->error_code);
> }
> }
> @@ -705,7 +706,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
> #GP fault is delivered inside the host. */
>
> /* remove any pending exception */
> - env->exception_index = -1;
> + cs->exception_index = -1;
> env->error_code = 0;
> env->old_exception = -1;
>
> diff --git a/target-lm32/helper.c b/target-lm32/helper.c
> index 55a3de6..b2093a8 100644
> --- a/target-lm32/helper.c
> +++ b/target-lm32/helper.c
> @@ -57,9 +57,9 @@ void lm32_cpu_do_interrupt(CPUState *cs)
> CPULM32State *env = &cpu->env;
>
> qemu_log_mask(CPU_LOG_INT,
> - "exception at pc=%x type=%x\n", env->pc, env->exception_index);
> + "exception at pc=%x type=%x\n", env->pc, cs->exception_index);
>
> - switch (env->exception_index) {
> + switch (cs->exception_index) {
> case EXCP_INSN_BUS_ERROR:
> case EXCP_DATA_BUS_ERROR:
> case EXCP_DIVIDE_BY_ZERO:
> @@ -70,9 +70,9 @@ void lm32_cpu_do_interrupt(CPUState *cs)
> env->ie |= (env->ie & IE_IE) ? IE_EIE : 0;
> env->ie &= ~IE_IE;
> if (env->dc & DC_RE) {
> - env->pc = env->deba + (env->exception_index * 32);
> + env->pc = env->deba + (cs->exception_index * 32);
> } else {
> - env->pc = env->eba + (env->exception_index * 32);
> + env->pc = env->eba + (cs->exception_index * 32);
> }
> log_cpu_state_mask(CPU_LOG_INT, cs, 0);
> break;
> @@ -82,12 +82,12 @@ void lm32_cpu_do_interrupt(CPUState *cs)
> env->regs[R_BA] = env->pc;
> env->ie |= (env->ie & IE_IE) ? IE_BIE : 0;
> env->ie &= ~IE_IE;
> - env->pc = env->deba + (env->exception_index * 32);
> + env->pc = env->deba + (cs->exception_index * 32);
> log_cpu_state_mask(CPU_LOG_INT, cs, 0);
> break;
> default:
> cpu_abort(env, "unhandled exception type=%d\n",
> - env->exception_index);
> + cs->exception_index);
> break;
> }
> }
> diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
> index 215215e..c7ad910 100644
> --- a/target-lm32/op_helper.c
> +++ b/target-lm32/op_helper.c
> @@ -21,7 +21,9 @@
>
> void HELPER(raise_exception)(CPULM32State *env, uint32_t index)
> {
> - env->exception_index = index;
> + CPUState *cs = CPU(lm32_env_get_cpu(env));
> +
> + cs->exception_index = index;
> cpu_loop_exit(env);
> }
>
> @@ -30,7 +32,7 @@ void HELPER(hlt)(CPULM32State *env)
> CPUState *cs = CPU(lm32_env_get_cpu(env));
>
> cs->halted = 1;
> - env->exception_index = EXCP_HLT;
> + cs->exception_index = EXCP_HLT;
> cpu_loop_exit(env);
> }
>
> diff --git a/target-m68k/helper.c b/target-m68k/helper.c
> index 25a0570..003a298 100644
> --- a/target-m68k/helper.c
> +++ b/target-m68k/helper.c
> @@ -283,7 +283,7 @@ int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> {
> M68kCPU *cpu = M68K_CPU(cs);
>
> - cpu->env.exception_index = EXCP_ACCESS;
> + cs->exception_index = EXCP_ACCESS;
> cpu->env.mmu.ar = address;
> return 1;
> }
> diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
> index bc10f38..466ad0c 100644
> --- a/target-m68k/op_helper.c
> +++ b/target-m68k/op_helper.c
> @@ -23,10 +23,7 @@
>
> void m68k_cpu_do_interrupt(CPUState *cs)
> {
> - M68kCPU *cpu = M68K_CPU(cs);
> - CPUM68KState *env = &cpu->env;
> -
> - env->exception_index = -1;
> + cs->exception_index = -1;
> }
>
> void do_interrupt_m68k_hardirq(CPUM68KState *env)
> @@ -88,7 +85,7 @@ static void do_rte(CPUM68KState *env)
>
> static void do_interrupt_all(CPUM68KState *env, int is_hw)
> {
> - CPUState *cs;
> + CPUState *cs = CPU(m68k_env_get_cpu(env));
> uint32_t sp;
> uint32_t fmt;
> uint32_t retaddr;
> @@ -98,7 +95,7 @@ static void do_interrupt_all(CPUM68KState *env, int is_hw)
> retaddr = env->pc;
>
> if (!is_hw) {
> - switch (env->exception_index) {
> + switch (cs->exception_index) {
> case EXCP_RTE:
> /* Return from an exception. */
> do_rte(env);
> @@ -113,20 +110,19 @@ static void do_interrupt_all(CPUM68KState *env, int is_hw)
> do_m68k_semihosting(env, env->dregs[0]);
> return;
> }
> - cs = CPU(m68k_env_get_cpu(env));
> cs->halted = 1;
> - env->exception_index = EXCP_HLT;
> + cs->exception_index = EXCP_HLT;
> cpu_loop_exit(env);
> return;
> }
> - if (env->exception_index >= EXCP_TRAP0
> - && env->exception_index <= EXCP_TRAP15) {
> + if (cs->exception_index >= EXCP_TRAP0
> + && cs->exception_index <= EXCP_TRAP15) {
> /* Move the PC after the trap instruction. */
> retaddr += 2;
> }
> }
>
> - vector = env->exception_index << 2;
> + vector = cs->exception_index << 2;
>
> sp = env->aregs[7];
>
> @@ -169,7 +165,9 @@ void do_interrupt_m68k_hardirq(CPUM68KState *env)
>
> static void raise_exception(CPUM68KState *env, int tt)
> {
> - env->exception_index = tt;
> + CPUState *cs = CPU(m68k_env_get_cpu(env));
> +
> + cs->exception_index = tt;
> cpu_loop_exit(env);
> }
>
> diff --git a/target-m68k/qregs.def b/target-m68k/qregs.def
> index 4235b02..204663e 100644
> --- a/target-m68k/qregs.def
> +++ b/target-m68k/qregs.def
> @@ -7,6 +7,5 @@ DEFO32(CC_SRC, cc_src)
> DEFO32(CC_X, cc_x)
> DEFO32(DIV1, div1)
> DEFO32(DIV2, div2)
> -DEFO32(EXCEPTION, exception_index)
> DEFO32(MACSR, macsr)
> DEFO32(MAC_MASK, mac_mask)
> diff --git a/target-m68k/translate.c b/target-m68k/translate.c
> index 0be0a96..f3cdee0 100644
> --- a/target-m68k/translate.c
> +++ b/target-m68k/translate.c
> @@ -43,6 +43,7 @@
> #undef DEFF64
>
> static TCGv_i32 cpu_halted;
> +static TCGv_i32 cpu_exception_index;
>
> static TCGv_ptr cpu_env;
>
> @@ -81,6 +82,10 @@ void m68k_tcg_init(void)
> cpu_halted = tcg_global_mem_new_i32(TCG_AREG0,
> -offsetof(M68kCPU, env) +
> offsetof(CPUState, halted), "HALTED");
> + cpu_exception_index = tcg_global_mem_new_i32(TCG_AREG0,
> + -offsetof(M68kCPU, env) +
> + offsetof(CPUState, exception_index),
> + "EXCEPTION");
>
> cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
>
> diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
> index d03f369..4825415 100644
> --- a/target-microblaze/helper.c
> +++ b/target-microblaze/helper.c
> @@ -31,7 +31,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
> MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
> CPUMBState *env = &cpu->env;
>
> - env->exception_index = -1;
> + cs->exception_index = -1;
> env->res_addr = RES_ADDR_NONE;
> env->regs[14] = env->sregs[SR_PC];
> }
> @@ -39,9 +39,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
> int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> int mmu_idx)
> {
> - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
> -
> - cpu->env.exception_index = 0xaa;
> + cs->exception_index = 0xaa;
> cpu_dump_state(cs, stderr, fprintf, 0);
> return 1;
> }
> @@ -99,12 +97,12 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> break;
> }
>
> - if (env->exception_index == EXCP_MMU) {
> + if (cs->exception_index == EXCP_MMU) {
> cpu_abort(env, "recursive faults\n");
> }
>
> /* TLB miss. */
> - env->exception_index = EXCP_MMU;
> + cs->exception_index = EXCP_MMU;
> }
> } else {
> /* MMU disabled or not available. */
> @@ -127,7 +125,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
> assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
> /* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */
> env->res_addr = RES_ADDR_NONE;
> - switch (env->exception_index) {
> + switch (cs->exception_index) {
> case EXCP_HW_EXCP:
> if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
> qemu_log("Exception raised on system without exceptions!\n");
> @@ -253,7 +251,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
> env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
> env->sregs[SR_MSR] |= t;
> env->sregs[SR_MSR] |= MSR_BIP;
> - if (env->exception_index == EXCP_HW_BREAK) {
> + if (cs->exception_index == EXCP_HW_BREAK) {
> env->regs[16] = env->sregs[SR_PC];
> env->sregs[SR_MSR] |= MSR_BIP;
> env->sregs[SR_PC] = cpu->base_vectors + 0x18;
> @@ -262,7 +260,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
> break;
> default:
> cpu_abort(env, "unhandled exception type=%d\n",
> - env->exception_index);
> + cs->exception_index);
> break;
> }
> }
> diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
> index b70b2ea..318185a 100644
> --- a/target-microblaze/op_helper.c
> +++ b/target-microblaze/op_helper.c
> @@ -95,7 +95,9 @@ uint32_t helper_get(uint32_t id, uint32_t ctrl)
>
> void helper_raise_exception(CPUMBState *env, uint32_t index)
> {
> - env->exception_index = index;
> + CPUState *cs = CPU(mb_env_get_cpu(env));
> +
> + cs->exception_index = index;
> cpu_loop_exit(env);
> }
>
> diff --git a/target-mips/helper.c b/target-mips/helper.c
> index d8e9166..698c3d1 100644
> --- a/target-mips/helper.c
> +++ b/target-mips/helper.c
> @@ -204,6 +204,7 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
> static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
> int rw, int tlb_error)
> {
> + CPUState *cs = CPU(mips_env_get_cpu(env));
> int exception = 0, error_code = 0;
>
> switch (tlb_error) {
> @@ -249,7 +250,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
> ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
> ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
> #endif
> - env->exception_index = exception;
> + cs->exception_index = exception;
> env->error_code = error_code;
> }
>
> @@ -404,27 +405,29 @@ static void set_hflags_for_handler (CPUMIPSState *env)
>
> void mips_cpu_do_interrupt(CPUState *cs)
> {
> +#if !defined(CONFIG_USER_ONLY)
> MIPSCPU *cpu = MIPS_CPU(cs);
> CPUMIPSState *env = &cpu->env;
> -#if !defined(CONFIG_USER_ONLY)
> target_ulong offset;
> int cause = -1;
> const char *name;
>
> - if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
> - if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
> + if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
> + if (cs->exception_index < 0 || cs->exception_index > EXCP_LAST) {
> name = "unknown";
> - else
> - name = excp_names[env->exception_index];
> + } else {
> + name = excp_names[cs->exception_index];
> + }
>
> qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
> __func__, env->active_tc.PC, env->CP0_EPC, name);
> }
> - if (env->exception_index == EXCP_EXT_INTERRUPT &&
> - (env->hflags & MIPS_HFLAG_DM))
> - env->exception_index = EXCP_DINT;
> + if (cs->exception_index == EXCP_EXT_INTERRUPT &&
> + (env->hflags & MIPS_HFLAG_DM)) {
> + cs->exception_index = EXCP_DINT;
> + }
> offset = 0x180;
> - switch (env->exception_index) {
> + switch (cs->exception_index) {
> case EXCP_DSS:
> env->CP0_Debug |= 1 << CP0DB_DSS;
> /* Debug single step cannot be raised inside a delay slot and
> @@ -632,11 +635,11 @@ void mips_cpu_do_interrupt(CPUState *cs)
> env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
> break;
> default:
> - qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index);
> - printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
> + qemu_log("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
> + printf("Invalid MIPS exception %d. Exiting\n", cs->exception_index);
> exit(1);
> }
> - if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
> + if (qemu_log_enabled() && cs->exception_index != EXCP_EXT_INTERRUPT) {
> qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
> " S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
> __func__, env->active_tc.PC, env->CP0_EPC, cause,
> @@ -644,7 +647,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
> env->CP0_DEPC);
> }
> #endif
> - env->exception_index = EXCP_NONE;
> + cs->exception_index = EXCP_NONE;
> }
>
> #if !defined(CONFIG_USER_ONLY)
> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
> index 34ac4c6..eeb98a6 100644
> --- a/target-mips/op_helper.c
> +++ b/target-mips/op_helper.c
> @@ -38,10 +38,12 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
> int error_code,
> uintptr_t pc)
> {
> + CPUState *cs = CPU(mips_env_get_cpu(env));
> +
> if (exception < EXCP_SC) {
> qemu_log("%s: %d %d\n", __func__, exception, error_code);
> }
> - env->exception_index = exception;
> + cs->exception_index = exception;
> env->error_code = error_code;
>
> if (pc) {
> @@ -2135,11 +2137,12 @@ void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> MIPSCPU *cpu = mips_env_get_cpu(env);
> + CPUState *cs = CPU(cpu);
> int ret;
>
> - ret = mips_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> + ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (ret) {
> - do_raise_exception_err(env, env->exception_index,
> + do_raise_exception_err(env, cs->exception_index,
> env->error_code, retaddr);
> }
> }
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index ad43d59..716d50c 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -15922,10 +15922,8 @@ MIPSCPU *cpu_mips_init(const char *cpu_model)
>
> void cpu_state_reset(CPUMIPSState *env)
> {
> -#ifndef CONFIG_USER_ONLY
> MIPSCPU *cpu = mips_env_get_cpu(env);
> CPUState *cs = CPU(cpu);
> -#endif
>
> /* Reset registers to their default values */
> env->CP0_PRid = env->cpu_model->CP0_PRid;
> @@ -16049,7 +16047,7 @@ void cpu_state_reset(CPUMIPSState *env)
> }
> #endif
> compute_hflags(env);
> - env->exception_index = EXCP_NONE;
> + cs->exception_index = EXCP_NONE;
> }
>
> void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, int pc_pos)
> diff --git a/target-moxie/helper.c b/target-moxie/helper.c
> index 8160475..3b14f37 100644
> --- a/target-moxie/helper.c
> +++ b/target-moxie/helper.c
> @@ -63,7 +63,9 @@ void tlb_fill(CPUMoxieState *env, target_ulong addr, int is_write, int mmu_idx,
>
> void helper_raise_exception(CPUMoxieState *env, int ex)
> {
> - env->exception_index = ex;
> + CPUState *cs = CPU(moxie_env_get_cpu(env));
> +
> + cs->exception_index = ex;
> /* Stash the exception type. */
> env->sregs[2] = ex;
> /* Stash the address where the exception occurred. */
> @@ -98,7 +100,9 @@ uint32_t helper_udiv(CPUMoxieState *env, uint32_t a, uint32_t b)
>
> void helper_debug(CPUMoxieState *env)
> {
> - env->exception_index = EXCP_DEBUG;
> + CPUState *cs = CPU(moxie_env_get_cpu(env));
> +
> + cs->exception_index = EXCP_DEBUG;
> cpu_loop_exit(env);
> }
>
> @@ -106,7 +110,9 @@ void helper_debug(CPUMoxieState *env)
>
> void moxie_cpu_do_interrupt(CPUState *cs)
> {
> - env->exception_index = -1;
> + CPUState *cs = CPU(moxie_env_get_cpu(env));
> +
> + cs->exception_index = -1;
> }
>
> int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> @@ -114,7 +120,7 @@ int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> {
> MoxieCPU *cpu = MOXIE_CPU(cs);
>
> - cpu->env.exception_index = 0xaa;
> + cs->exception_index = 0xaa;
> cpu->env.debug1 = address;
> cpu_dump_state(cs, stderr, fprintf, 0);
> return 1;
> @@ -138,7 +144,7 @@ int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> if (miss) {
> /* handle the miss. */
> phy = 0;
> - env->exception_index = MOXIE_EX_MMU_MISS;
> + cs->exception_index = MOXIE_EX_MMU_MISS;
> } else {
> phy = res.phy;
> r = 0;
> @@ -150,10 +156,7 @@ int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
>
> void moxie_cpu_do_interrupt(CPUState *cs)
> {
> - MoxieCPU *cpu = MOXIE_CPU(cs);
> - CPUMoxieState *env = &cpu->env;
> -
> - switch (env->exception_index) {
> + switch (cs->exception_index) {
> case MOXIE_EX_BREAK:
> break;
> default:
> diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
> index ee1591d..b233969 100644
> --- a/target-openrisc/cpu.c
> +++ b/target-openrisc/cpu.c
> @@ -69,7 +69,7 @@ static void openrisc_cpu_reset(CPUState *s)
>
> cpu->env.pc = 0x100;
> cpu->env.sr = SR_FO | SR_SM;
> - cpu->env.exception_index = -1;
> + s->exception_index = -1;
>
> cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
> cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S;
> diff --git a/target-openrisc/exception.c b/target-openrisc/exception.c
> index 58e53c6..b96f3f8 100644
> --- a/target-openrisc/exception.c
> +++ b/target-openrisc/exception.c
> @@ -22,6 +22,8 @@
>
> void QEMU_NORETURN raise_exception(OpenRISCCPU *cpu, uint32_t excp)
> {
> - cpu->env.exception_index = excp;
> + CPUState *cs = CPU(cpu);
> +
> + cs->exception_index = excp;
> cpu_loop_exit(&cpu->env);
> }
> diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
> index 16ef4b3..64f2ca6 100644
> --- a/target-openrisc/interrupt.c
> +++ b/target-openrisc/interrupt.c
> @@ -27,25 +27,26 @@
>
> void openrisc_cpu_do_interrupt(CPUState *cs)
> {
> +#ifndef CONFIG_USER_ONLY
> OpenRISCCPU *cpu = OPENRISC_CPU(cs);
> CPUOpenRISCState *env = &cpu->env;
> -#ifndef CONFIG_USER_ONLY
> +
> if (env->flags & D_FLAG) { /* Delay Slot insn */
> env->flags &= ~D_FLAG;
> env->sr |= SR_DSX;
> - if (env->exception_index == EXCP_TICK ||
> - env->exception_index == EXCP_INT ||
> - env->exception_index == EXCP_SYSCALL ||
> - env->exception_index == EXCP_FPE) {
> + if (cs->exception_index == EXCP_TICK ||
> + cs->exception_index == EXCP_INT ||
> + cs->exception_index == EXCP_SYSCALL ||
> + cs->exception_index == EXCP_FPE) {
> env->epcr = env->jmp_pc;
> } else {
> env->epcr = env->pc - 4;
> }
> } else {
> - if (env->exception_index == EXCP_TICK ||
> - env->exception_index == EXCP_INT ||
> - env->exception_index == EXCP_SYSCALL ||
> - env->exception_index == EXCP_FPE) {
> + if (cs->exception_index == EXCP_TICK ||
> + cs->exception_index == EXCP_INT ||
> + cs->exception_index == EXCP_SYSCALL ||
> + cs->exception_index == EXCP_FPE) {
> env->epcr = env->npc;
> } else {
> env->epcr = env->pc;
> @@ -65,12 +66,12 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
> env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
> env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
>
> - if (env->exception_index > 0 && env->exception_index < EXCP_NR) {
> - env->pc = (env->exception_index << 8);
> + if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) {
> + env->pc = (cs->exception_index << 8);
> } else {
> - cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
> + cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
> }
> #endif
>
> - env->exception_index = -1;
> + cs->exception_index = -1;
> }
> diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c
> index 0f13c5d..b1830da 100644
> --- a/target-openrisc/mmu.c
> +++ b/target-openrisc/mmu.c
> @@ -146,6 +146,7 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu,
> target_ulong address,
> int rw, int tlb_error)
> {
> + CPUState *cs = CPU(cpu);
> int exception = 0;
>
> switch (tlb_error) {
> @@ -176,7 +177,7 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu,
> #endif
> }
>
> - cpu->env.exception_index = exception;
> + cs->exception_index = exception;
> cpu->env.eear = address;
> }
>
> diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
> index c959460..0ec2615 100644
> --- a/target-ppc/excp_helper.c
> +++ b/target-ppc/excp_helper.c
> @@ -43,13 +43,15 @@ void ppc_cpu_do_interrupt(CPUState *cs)
> PowerPCCPU *cpu = POWERPC_CPU(cs);
> CPUPPCState *env = &cpu->env;
>
> - env->exception_index = POWERPC_EXCP_NONE;
> + cs->exception_index = POWERPC_EXCP_NONE;
> env->error_code = 0;
> }
>
> void ppc_hw_interrupt(CPUPPCState *env)
> {
> - env->exception_index = POWERPC_EXCP_NONE;
> + CPUState *cs = CPU(ppc_env_get_cpu(env));
> +
> + cs->exception_index = POWERPC_EXCP_NONE;
> env->error_code = 0;
> }
> #else /* defined(CONFIG_USER_ONLY) */
> @@ -68,8 +70,8 @@ static inline void dump_syscall(CPUPPCState *env)
> */
> static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
> {
> + CPUState *cs = CPU(cpu);
> CPUPPCState *env = &cpu->env;
> - CPUState *cs;
> target_ulong msr, new_msr, vector;
> int srr0, srr1, asrr0, asrr1;
> int lpes0, lpes1, lev;
> @@ -135,7 +137,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
> fprintf(stderr, "Machine check while not allowed. "
> "Entering checkstop state\n");
> }
> - cs = CPU(cpu);
> cs->halted = 1;
> cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
> }
> @@ -202,7 +203,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
> case POWERPC_EXCP_FP:
> if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
> LOG_EXCP("Ignore floating point exception\n");
> - env->exception_index = POWERPC_EXCP_NONE;
> + cs->exception_index = POWERPC_EXCP_NONE;
> env->error_code = 0;
> return;
> }
> @@ -655,7 +656,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
> hreg_compute_hflags(env);
> env->nip = vector;
> /* Reset exception state */
> - env->exception_index = POWERPC_EXCP_NONE;
> + cs->exception_index = POWERPC_EXCP_NONE;
> env->error_code = 0;
>
> if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
> @@ -672,7 +673,7 @@ void ppc_cpu_do_interrupt(CPUState *cs)
> PowerPCCPU *cpu = POWERPC_CPU(cs);
> CPUPPCState *env = &cpu->env;
>
> - powerpc_excp(cpu, env->excp_model, env->exception_index);
> + powerpc_excp(cpu, env->excp_model, cs->exception_index);
> }
>
> void ppc_hw_interrupt(CPUPPCState *env)
> @@ -808,10 +809,12 @@ static void cpu_dump_rfi(target_ulong RA, target_ulong msr)
> void helper_raise_exception_err(CPUPPCState *env, uint32_t exception,
> uint32_t error_code)
> {
> + CPUState *cs = CPU(ppc_env_get_cpu(env));
> +
> #if 0
> printf("Raise exception %3x code : %d\n", exception, error_code);
> #endif
> - env->exception_index = exception;
> + cs->exception_index = exception;
> env->error_code = error_code;
> cpu_loop_exit(env);
> }
> diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
> index 4f60218..314e66f 100644
> --- a/target-ppc/fpu_helper.c
> +++ b/target-ppc/fpu_helper.c
> @@ -108,6 +108,7 @@ uint32_t helper_compute_fprf(CPUPPCState *env, uint64_t arg, uint32_t set_fprf)
> /* Floating-point invalid operations exception */
> static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op)
> {
> + CPUState *cs = CPU(ppc_env_get_cpu(env));
> uint64_t ret = 0;
> int ve;
>
> @@ -142,7 +143,7 @@ static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op)
> env->fpscr |= 0x11 << FPSCR_FPCC;
> /* We must update the target FPR before raising the exception */
> if (ve != 0) {
> - env->exception_index = POWERPC_EXCP_PROGRAM;
> + cs->exception_index = POWERPC_EXCP_PROGRAM;
> env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
> /* Update the floating-point enabled exception summary */
> env->fpscr |= 1 << FPSCR_FEX;
> @@ -207,6 +208,8 @@ static inline void float_zero_divide_excp(CPUPPCState *env)
>
> static inline void float_overflow_excp(CPUPPCState *env)
> {
> + CPUState *cs = CPU(ppc_env_get_cpu(env));
> +
> env->fpscr |= 1 << FPSCR_OX;
> /* Update the floating-point exception summary */
> env->fpscr |= 1 << FPSCR_FX;
> @@ -215,7 +218,7 @@ static inline void float_overflow_excp(CPUPPCState *env)
> /* Update the floating-point enabled exception summary */
> env->fpscr |= 1 << FPSCR_FEX;
> /* We must update the target FPR before raising the exception */
> - env->exception_index = POWERPC_EXCP_PROGRAM;
> + cs->exception_index = POWERPC_EXCP_PROGRAM;
> env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
> } else {
> env->fpscr |= 1 << FPSCR_XX;
> @@ -225,6 +228,8 @@ static inline void float_overflow_excp(CPUPPCState *env)
>
> static inline void float_underflow_excp(CPUPPCState *env)
> {
> + CPUState *cs = CPU(ppc_env_get_cpu(env));
> +
> env->fpscr |= 1 << FPSCR_UX;
> /* Update the floating-point exception summary */
> env->fpscr |= 1 << FPSCR_FX;
> @@ -233,13 +238,15 @@ static inline void float_underflow_excp(CPUPPCState *env)
> /* Update the floating-point enabled exception summary */
> env->fpscr |= 1 << FPSCR_FEX;
> /* We must update the target FPR before raising the exception */
> - env->exception_index = POWERPC_EXCP_PROGRAM;
> + cs->exception_index = POWERPC_EXCP_PROGRAM;
> env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
> }
> }
>
> static inline void float_inexact_excp(CPUPPCState *env)
> {
> + CPUState *cs = CPU(ppc_env_get_cpu(env));
> +
> env->fpscr |= 1 << FPSCR_XX;
> /* Update the floating-point exception summary */
> env->fpscr |= 1 << FPSCR_FX;
> @@ -247,7 +254,7 @@ static inline void float_inexact_excp(CPUPPCState *env)
> /* Update the floating-point enabled exception summary */
> env->fpscr |= 1 << FPSCR_FEX;
> /* We must update the target FPR before raising the exception */
> - env->exception_index = POWERPC_EXCP_PROGRAM;
> + cs->exception_index = POWERPC_EXCP_PROGRAM;
> env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
> }
> }
> @@ -299,6 +306,7 @@ void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)
>
> void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
> {
> + CPUState *cs = CPU(ppc_env_get_cpu(env));
> int prev;
>
> prev = (env->fpscr >> bit) & 1;
> @@ -422,7 +430,7 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
> /* Update the floating-point enabled exception summary */
> env->fpscr |= 1 << FPSCR_FEX;
> /* We have to update Rc1 before raising the exception */
> - env->exception_index = POWERPC_EXCP_PROGRAM;
> + cs->exception_index = POWERPC_EXCP_PROGRAM;
> break;
> }
> }
> @@ -430,6 +438,7 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
>
> void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
> {
> + CPUState *cs = CPU(ppc_env_get_cpu(env));
> target_ulong prev, new;
> int i;
>
> @@ -451,7 +460,7 @@ void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
> }
> if ((fpscr_ex & fpscr_eex) != 0) {
> env->fpscr |= 1 << FPSCR_FEX;
> - env->exception_index = POWERPC_EXCP_PROGRAM;
> + cs->exception_index = POWERPC_EXCP_PROGRAM;
> /* XXX: we should compute it properly */
> env->error_code = POWERPC_EXCP_FP;
> } else {
> @@ -467,6 +476,7 @@ void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
>
> void helper_float_check_status(CPUPPCState *env)
> {
> + CPUState *cs = CPU(ppc_env_get_cpu(env));
> int status = get_float_exception_flags(&env->fp_status);
>
> if (status & float_flag_divbyzero) {
> @@ -479,11 +489,11 @@ void helper_float_check_status(CPUPPCState *env)
> float_inexact_excp(env);
> }
>
> - if (env->exception_index == POWERPC_EXCP_PROGRAM &&
> + if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
> (env->error_code & POWERPC_EXCP_FP)) {
> /* Differred floating-point exception after target FPR update */
> if (msr_fe0 != 0 || msr_fe1 != 0) {
> - helper_raise_exception_err(env, env->exception_index,
> + helper_raise_exception_err(env, cs->exception_index,
> env->error_code);
> }
> }
> diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
> index 6a77dc4..aa87084 100644
> --- a/target-ppc/mmu-hash32.c
> +++ b/target-ppc/mmu-hash32.c
> @@ -222,6 +222,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
> target_ulong eaddr, int rwx,
> hwaddr *raddr, int *prot)
> {
> + CPUState *cs = CPU(ppc_env_get_cpu(env));
> int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
>
> LOG_MMU("direct store...\n");
> @@ -238,7 +239,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
>
> if (rwx == 2) {
> /* No code fetch is allowed in direct-store areas */
> - env->exception_index = POWERPC_EXCP_ISI;
> + cs->exception_index = POWERPC_EXCP_ISI;
> env->error_code = 0x10000000;
> return 1;
> }
> @@ -249,7 +250,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
> break;
> case ACCESS_FLOAT:
> /* Floating point load/store */
> - env->exception_index = POWERPC_EXCP_ALIGN;
> + cs->exception_index = POWERPC_EXCP_ALIGN;
> env->error_code = POWERPC_EXCP_ALIGN_FP;
> env->spr[SPR_DAR] = eaddr;
> return 1;
> @@ -272,7 +273,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
> return 0;
> case ACCESS_EXT:
> /* eciwx or ecowx */
> - env->exception_index = POWERPC_EXCP_DSI;
> + cs->exception_index = POWERPC_EXCP_DSI;
> env->error_code = 0;
> env->spr[SPR_DAR] = eaddr;
> if (rwx == 1) {
> @@ -290,7 +291,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
> *raddr = eaddr;
> return 0;
> } else {
> - env->exception_index = POWERPC_EXCP_DSI;
> + cs->exception_index = POWERPC_EXCP_DSI;
> env->error_code = 0;
> env->spr[SPR_DAR] = eaddr;
> if (rwx == 1) {
> @@ -383,6 +384,7 @@ static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,
> int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx,
> int mmu_idx)
> {
> + CPUState *cs = CPU(ppc_env_get_cpu(env));
> target_ulong sr;
> hwaddr pte_offset;
> ppc_hash_pte32_t pte;
> @@ -409,10 +411,10 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx,
> if (raddr != -1) {
> if (need_prot[rwx] & ~prot) {
> if (rwx == 2) {
> - env->exception_index = POWERPC_EXCP_ISI;
> + cs->exception_index = POWERPC_EXCP_ISI;
> env->error_code = 0x08000000;
> } else {
> - env->exception_index = POWERPC_EXCP_DSI;
> + cs->exception_index = POWERPC_EXCP_DSI;
> env->error_code = 0;
> env->spr[SPR_DAR] = eaddr;
> if (rwx == 1) {
> @@ -449,7 +451,7 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx,
>
> /* 5. Check for segment level no-execute violation */
> if ((rwx == 2) && (sr & SR32_NX)) {
> - env->exception_index = POWERPC_EXCP_ISI;
> + cs->exception_index = POWERPC_EXCP_ISI;
> env->error_code = 0x10000000;
> return 1;
> }
> @@ -458,10 +460,10 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx,
> pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
> if (pte_offset == -1) {
> if (rwx == 2) {
> - env->exception_index = POWERPC_EXCP_ISI;
> + cs->exception_index = POWERPC_EXCP_ISI;
> env->error_code = 0x40000000;
> } else {
> - env->exception_index = POWERPC_EXCP_DSI;
> + cs->exception_index = POWERPC_EXCP_DSI;
> env->error_code = 0;
> env->spr[SPR_DAR] = eaddr;
> if (rwx == 1) {
> @@ -483,10 +485,10 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx,
> /* Access right violation */
> LOG_MMU("PTE access rejected\n");
> if (rwx == 2) {
> - env->exception_index = POWERPC_EXCP_ISI;
> + cs->exception_index = POWERPC_EXCP_ISI;
> env->error_code = 0x08000000;
> } else {
> - env->exception_index = POWERPC_EXCP_DSI;
> + cs->exception_index = POWERPC_EXCP_DSI;
> env->error_code = 0;
> env->spr[SPR_DAR] = eaddr;
> if (rwx == 1) {
> diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
> index 67fc1b5..04dcfb3 100644
> --- a/target-ppc/mmu-hash64.c
> +++ b/target-ppc/mmu-hash64.c
> @@ -399,6 +399,7 @@ static hwaddr ppc_hash64_pte_raddr(ppc_slb_t *slb, ppc_hash_pte64_t pte,
> int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr,
> int rwx, int mmu_idx)
> {
> + CPUState *cs = CPU(ppc_env_get_cpu(env));
> ppc_slb_t *slb;
> hwaddr pte_offset;
> ppc_hash_pte64_t pte;
> @@ -425,10 +426,10 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr,
>
> if (!slb) {
> if (rwx == 2) {
> - env->exception_index = POWERPC_EXCP_ISEG;
> + cs->exception_index = POWERPC_EXCP_ISEG;
> env->error_code = 0;
> } else {
> - env->exception_index = POWERPC_EXCP_DSEG;
> + cs->exception_index = POWERPC_EXCP_DSEG;
> env->error_code = 0;
> env->spr[SPR_DAR] = eaddr;
> }
> @@ -437,7 +438,7 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr,
>
> /* 3. Check for segment level no-execute violation */
> if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
> - env->exception_index = POWERPC_EXCP_ISI;
> + cs->exception_index = POWERPC_EXCP_ISI;
> env->error_code = 0x10000000;
> return 1;
> }
> @@ -446,10 +447,10 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr,
> pte_offset = ppc_hash64_htab_lookup(env, slb, eaddr, &pte);
> if (pte_offset == -1) {
> if (rwx == 2) {
> - env->exception_index = POWERPC_EXCP_ISI;
> + cs->exception_index = POWERPC_EXCP_ISI;
> env->error_code = 0x40000000;
> } else {
> - env->exception_index = POWERPC_EXCP_DSI;
> + cs->exception_index = POWERPC_EXCP_DSI;
> env->error_code = 0;
> env->spr[SPR_DAR] = eaddr;
> if (rwx == 1) {
> @@ -472,12 +473,12 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr,
> /* Access right violation */
> LOG_MMU("PTE access rejected\n");
> if (rwx == 2) {
> - env->exception_index = POWERPC_EXCP_ISI;
> + cs->exception_index = POWERPC_EXCP_ISI;
> env->error_code = 0x08000000;
> } else {
> target_ulong dsisr = 0;
>
> - env->exception_index = POWERPC_EXCP_DSI;
> + cs->exception_index = POWERPC_EXCP_DSI;
> env->error_code = 0;
> env->spr[SPR_DAR] = eaddr;
> if (need_prot[rwx] & ~pp_prot) {
> diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
> index 04a840b..79a9134 100644
> --- a/target-ppc/mmu_helper.c
> +++ b/target-ppc/mmu_helper.c
> @@ -1491,6 +1491,7 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
> static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> int rw, int mmu_idx)
> {
> + CPUState *cs = CPU(ppc_env_get_cpu(env));
> mmu_ctx_t ctx;
> int access_type;
> int ret = 0;
> @@ -1510,24 +1511,24 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> mmu_idx, TARGET_PAGE_SIZE);
> ret = 0;
> } else if (ret < 0) {
> - LOG_MMU_STATE(CPU(ppc_env_get_cpu(env)));
> + LOG_MMU_STATE(cs);
> if (access_type == ACCESS_CODE) {
> switch (ret) {
> case -1:
> /* No matches in page tables or TLB */
> switch (env->mmu_model) {
> case POWERPC_MMU_SOFT_6xx:
> - env->exception_index = POWERPC_EXCP_IFTLB;
> + cs->exception_index = POWERPC_EXCP_IFTLB;
> env->error_code = 1 << 18;
> env->spr[SPR_IMISS] = address;
> env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
> goto tlb_miss;
> case POWERPC_MMU_SOFT_74xx:
> - env->exception_index = POWERPC_EXCP_IFTLB;
> + cs->exception_index = POWERPC_EXCP_IFTLB;
> goto tlb_miss_74xx;
> case POWERPC_MMU_SOFT_4xx:
> case POWERPC_MMU_SOFT_4xx_Z:
> - env->exception_index = POWERPC_EXCP_ITLB;
> + cs->exception_index = POWERPC_EXCP_ITLB;
> env->error_code = 0;
> env->spr[SPR_40x_DEAR] = address;
> env->spr[SPR_40x_ESR] = 0x00000000;
> @@ -1536,7 +1537,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> booke206_update_mas_tlb_miss(env, address, rw);
> /* fall through */
> case POWERPC_MMU_BOOKE:
> - env->exception_index = POWERPC_EXCP_ITLB;
> + cs->exception_index = POWERPC_EXCP_ITLB;
> env->error_code = 0;
> env->spr[SPR_BOOKE_DEAR] = address;
> return -1;
> @@ -1555,7 +1556,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> break;
> case -2:
> /* Access rights violation */
> - env->exception_index = POWERPC_EXCP_ISI;
> + cs->exception_index = POWERPC_EXCP_ISI;
> env->error_code = 0x08000000;
> break;
> case -3:
> @@ -1564,13 +1565,13 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> (env->mmu_model == POWERPC_MMU_BOOKE206)) {
> env->spr[SPR_BOOKE_ESR] = 0x00000000;
> }
> - env->exception_index = POWERPC_EXCP_ISI;
> + cs->exception_index = POWERPC_EXCP_ISI;
> env->error_code = 0x10000000;
> break;
> case -4:
> /* Direct store exception */
> /* No code fetch is allowed in direct-store areas */
> - env->exception_index = POWERPC_EXCP_ISI;
> + cs->exception_index = POWERPC_EXCP_ISI;
> env->error_code = 0x10000000;
> break;
> }
> @@ -1581,10 +1582,10 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> switch (env->mmu_model) {
> case POWERPC_MMU_SOFT_6xx:
> if (rw == 1) {
> - env->exception_index = POWERPC_EXCP_DSTLB;
> + cs->exception_index = POWERPC_EXCP_DSTLB;
> env->error_code = 1 << 16;
> } else {
> - env->exception_index = POWERPC_EXCP_DLTLB;
> + cs->exception_index = POWERPC_EXCP_DLTLB;
> env->error_code = 0;
> }
> env->spr[SPR_DMISS] = address;
> @@ -1598,9 +1599,9 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> break;
> case POWERPC_MMU_SOFT_74xx:
> if (rw == 1) {
> - env->exception_index = POWERPC_EXCP_DSTLB;
> + cs->exception_index = POWERPC_EXCP_DSTLB;
> } else {
> - env->exception_index = POWERPC_EXCP_DLTLB;
> + cs->exception_index = POWERPC_EXCP_DLTLB;
> }
> tlb_miss_74xx:
> /* Implement LRU algorithm */
> @@ -1611,7 +1612,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> break;
> case POWERPC_MMU_SOFT_4xx:
> case POWERPC_MMU_SOFT_4xx_Z:
> - env->exception_index = POWERPC_EXCP_DTLB;
> + cs->exception_index = POWERPC_EXCP_DTLB;
> env->error_code = 0;
> env->spr[SPR_40x_DEAR] = address;
> if (rw) {
> @@ -1628,7 +1629,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> booke206_update_mas_tlb_miss(env, address, rw);
> /* fall through */
> case POWERPC_MMU_BOOKE:
> - env->exception_index = POWERPC_EXCP_DTLB;
> + cs->exception_index = POWERPC_EXCP_DTLB;
> env->error_code = 0;
> env->spr[SPR_BOOKE_DEAR] = address;
> env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0;
> @@ -1644,7 +1645,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> break;
> case -2:
> /* Access rights violation */
> - env->exception_index = POWERPC_EXCP_DSI;
> + cs->exception_index = POWERPC_EXCP_DSI;
> env->error_code = 0;
> if (env->mmu_model == POWERPC_MMU_SOFT_4xx
> || env->mmu_model == POWERPC_MMU_SOFT_4xx_Z) {
> @@ -1670,13 +1671,13 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> switch (access_type) {
> case ACCESS_FLOAT:
> /* Floating point load/store */
> - env->exception_index = POWERPC_EXCP_ALIGN;
> + cs->exception_index = POWERPC_EXCP_ALIGN;
> env->error_code = POWERPC_EXCP_ALIGN_FP;
> env->spr[SPR_DAR] = address;
> break;
> case ACCESS_RES:
> /* lwarx, ldarx or stwcx. */
> - env->exception_index = POWERPC_EXCP_DSI;
> + cs->exception_index = POWERPC_EXCP_DSI;
> env->error_code = 0;
> env->spr[SPR_DAR] = address;
> if (rw == 1) {
> @@ -1687,7 +1688,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> break;
> case ACCESS_EXT:
> /* eciwx or ecowx */
> - env->exception_index = POWERPC_EXCP_DSI;
> + cs->exception_index = POWERPC_EXCP_DSI;
> env->error_code = 0;
> env->spr[SPR_DAR] = address;
> if (rw == 1) {
> @@ -1698,7 +1699,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> break;
> default:
> printf("DSI: invalid exception (%d)\n", ret);
> - env->exception_index = POWERPC_EXCP_PROGRAM;
> + cs->exception_index = POWERPC_EXCP_PROGRAM;
> env->error_code =
> POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
> env->spr[SPR_DAR] = address;
> @@ -1709,7 +1710,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> }
> #if 0
> printf("%s: set exception to %d %02x\n", __func__,
> - env->exception, env->error_code);
> + cs->exception, env->error_code);
> #endif
> ret = 1;
> }
> @@ -2908,6 +2909,6 @@ void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx,
> /* now we have a real cpu fault */
> cpu_restore_state(env, retaddr);
> }
> - helper_raise_exception_err(env, env->exception_index, env->error_code);
> + helper_raise_exception_err(env, cpu->exception_index, env->error_code);
> }
> }
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 8b6fbb5..0934a45 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8511,7 +8511,7 @@ static void ppc_cpu_reset(CPUState *s)
> env->reserve_addr = (target_ulong)-1ULL;
> /* Be sure no exception or interrupt is pending */
> env->pending_interrupts = 0;
> - env->exception_index = POWERPC_EXCP_NONE;
> + s->exception_index = POWERPC_EXCP_NONE;
> env->error_code = 0;
>
> #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
> diff --git a/target-ppc/user_only_helper.c b/target-ppc/user_only_helper.c
> index a7c99e0..829f66f 100644
> --- a/target-ppc/user_only_helper.c
> +++ b/target-ppc/user_only_helper.c
> @@ -39,7 +39,7 @@ int ppc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> env->spr[SPR_DAR] = address;
> env->spr[SPR_DSISR] = error_code;
> }
> - env->exception_index = exception;
> + cs->exception_index = exception;
> env->error_code = error_code;
>
> return 1;
> diff --git a/target-s390x/helper.c b/target-s390x/helper.c
> index 361d713..c9d3d55 100644
> --- a/target-s390x/helper.c
> +++ b/target-s390x/helper.c
> @@ -88,10 +88,7 @@ S390CPU *cpu_s390x_init(const char *cpu_model)
>
> void s390_cpu_do_interrupt(CPUState *cs)
> {
> - S390CPU *cpu = S390_CPU(cs);
> - CPUS390XState *env = &cpu->env;
> -
> - env->exception_index = -1;
> + cs->exception_index = -1;
> }
>
> int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> @@ -99,7 +96,7 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> {
> S390CPU *cpu = S390_CPU(cs);
>
> - cpu->env.exception_index = EXCP_PGM;
> + cs->exception_index = EXCP_PGM;
> cpu->env.int_pgm_code = PGM_ADDRESSING;
> /* On real machines this value is dropped into LowMem. Since this
> is userland, simply put this someplace that cpu_loop can find it. */
> @@ -113,7 +110,9 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> static void trigger_pgm_exception(CPUS390XState *env, uint32_t code,
> uint32_t ilen)
> {
> - env->exception_index = EXCP_PGM;
> + CPUState *cs = CPU(s390_env_get_cpu(env));
> +
> + cs->exception_index = EXCP_PGM;
> env->int_pgm_code = code;
> env->int_pgm_ilen = ilen;
> }
> @@ -427,7 +426,7 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
> CPUS390XState *env = &cpu->env;
> target_ulong raddr;
> int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
> - int old_exc = env->exception_index;
> + int old_exc = cs->exception_index;
> uint64_t asc = env->psw.mask & PSW_MASK_ASC;
>
> /* 31-Bit mode */
> @@ -436,7 +435,7 @@ hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
> }
>
> mmu_translate(env, vaddr, 2, asc, &raddr, &prot);
> - env->exception_index = old_exc;
> + cs->exception_index = old_exc;
>
> return raddr;
> }
> @@ -454,7 +453,7 @@ void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
> }
> }
> cs->halted = 1;
> - env->exception_index = EXCP_HLT;
> + cs->exception_index = EXCP_HLT;
> }
>
> env->psw.addr = addr;
> @@ -751,43 +750,43 @@ void s390_cpu_do_interrupt(CPUState *cs)
> CPUS390XState *env = &cpu->env;
>
> qemu_log_mask(CPU_LOG_INT, "%s: %d at pc=%" PRIx64 "\n",
> - __func__, env->exception_index, env->psw.addr);
> + __func__, cs->exception_index, env->psw.addr);
>
> s390_add_running_cpu(cpu);
> /* handle machine checks */
> if ((env->psw.mask & PSW_MASK_MCHECK) &&
> - (env->exception_index == -1)) {
> + (cs->exception_index == -1)) {
> if (env->pending_int & INTERRUPT_MCHK) {
> - env->exception_index = EXCP_MCHK;
> + cs->exception_index = EXCP_MCHK;
> }
> }
> /* handle external interrupts */
> if ((env->psw.mask & PSW_MASK_EXT) &&
> - env->exception_index == -1) {
> + cs->exception_index == -1) {
> if (env->pending_int & INTERRUPT_EXT) {
> /* code is already in env */
> - env->exception_index = EXCP_EXT;
> + cs->exception_index = EXCP_EXT;
> } else if (env->pending_int & INTERRUPT_TOD) {
> cpu_inject_ext(cpu, 0x1004, 0, 0);
> - env->exception_index = EXCP_EXT;
> + cs->exception_index = EXCP_EXT;
> env->pending_int &= ~INTERRUPT_EXT;
> env->pending_int &= ~INTERRUPT_TOD;
> } else if (env->pending_int & INTERRUPT_CPUTIMER) {
> cpu_inject_ext(cpu, 0x1005, 0, 0);
> - env->exception_index = EXCP_EXT;
> + cs->exception_index = EXCP_EXT;
> env->pending_int &= ~INTERRUPT_EXT;
> env->pending_int &= ~INTERRUPT_TOD;
> }
> }
> /* handle I/O interrupts */
> if ((env->psw.mask & PSW_MASK_IO) &&
> - (env->exception_index == -1)) {
> + (cs->exception_index == -1)) {
> if (env->pending_int & INTERRUPT_IO) {
> - env->exception_index = EXCP_IO;
> + cs->exception_index = EXCP_IO;
> }
> }
>
> - switch (env->exception_index) {
> + switch (cs->exception_index) {
> case EXCP_PGM:
> do_program_interrupt(env);
> break;
> @@ -804,7 +803,7 @@ void s390_cpu_do_interrupt(CPUState *cs)
> do_mchk_interrupt(env);
> break;
> }
> - env->exception_index = -1;
> + cs->exception_index = -1;
>
> if (!env->pending_int) {
> cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
> diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
> index 747ba46..e2748a7 100644
> --- a/target-s390x/mem_helper.c
> +++ b/target-s390x/mem_helper.c
> @@ -1048,8 +1048,9 @@ void HELPER(stura)(CPUS390XState *env, uint64_t addr, uint64_t v1)
> /* load real address */
> uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr)
> {
> + CPUState *cs = CPU(s390_env_get_cpu(env));
> uint32_t cc = 0;
> - int old_exc = env->exception_index;
> + int old_exc = cs->exception_index;
> uint64_t asc = env->psw.mask & PSW_MASK_ASC;
> uint64_t ret;
> int flags;
> @@ -1059,16 +1060,16 @@ uint64_t HELPER(lra)(CPUS390XState *env, uint64_t addr)
> program_interrupt(env, PGM_SPECIAL_OP, 2);
> }
>
> - env->exception_index = old_exc;
> + cs->exception_index = old_exc;
> if (mmu_translate(env, addr, 0, asc, &ret, &flags)) {
> cc = 3;
> }
> - if (env->exception_index == EXCP_PGM) {
> + if (cs->exception_index == EXCP_PGM) {
> ret = env->int_pgm_code | 0x80000000;
> } else {
> ret |= addr & ~TARGET_PAGE_MASK;
> }
> - env->exception_index = old_exc;
> + cs->exception_index = old_exc;
>
> env->cc_op = cc;
> return ret;
> diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
> index 1690907..b6bd16f 100644
> --- a/target-s390x/misc_helper.c
> +++ b/target-s390x/misc_helper.c
> @@ -46,9 +46,10 @@
> void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
> uintptr_t retaddr)
> {
> + CPUState *cs = CPU(s390_env_get_cpu(env));
> int t;
>
> - env->exception_index = EXCP_PGM;
> + cs->exception_index = EXCP_PGM;
> env->int_pgm_code = excp;
>
> /* Use the (ultimate) callers address to find the insn that trapped. */
> @@ -65,8 +66,10 @@ void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
> /* Raise an exception statically from a TB. */
> void HELPER(exception)(CPUS390XState *env, uint32_t excp)
> {
> + CPUState *cs = CPU(s390_env_get_cpu(env));
> +
> HELPER_LOG("%s: exception %d\n", __func__, excp);
> - env->exception_index = excp;
> + cs->exception_index = excp;
> cpu_loop_exit(env);
> }
>
> @@ -154,17 +157,21 @@ static inline void ebcdic_put(uint8_t *p, const char *ascii, int len)
>
> void program_interrupt(CPUS390XState *env, uint32_t code, int ilen)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> +
> qemu_log_mask(CPU_LOG_INT, "program interrupt at %#" PRIx64 "\n",
> env->psw.addr);
>
> if (kvm_enabled()) {
> #ifdef CONFIG_KVM
> - kvm_s390_interrupt(s390_env_get_cpu(env), KVM_S390_PROGRAM_INT, code);
> + kvm_s390_interrupt(cpu, KVM_S390_PROGRAM_INT, code);
> #endif
> } else {
> + CPUState *cs = CPU(cpu);
> +
> env->int_pgm_code = code;
> env->int_pgm_ilen = ilen;
> - env->exception_index = EXCP_PGM;
> + cs->exception_index = EXCP_PGM;
> cpu_loop_exit(env);
> }
> }
> diff --git a/target-sh4/helper.c b/target-sh4/helper.c
> index 3f8f1fa..0357ceb 100644
> --- a/target-sh4/helper.c
> +++ b/target-sh4/helper.c
> @@ -33,10 +33,7 @@
>
> void superh_cpu_do_interrupt(CPUState *cs)
> {
> - SuperHCPU *cpu = SUPERH_CPU(cs);
> - CPUSH4State *env = &cpu->env;
> -
> - env->exception_index = -1;
> + cs->exception_index = -1;
> }
>
> int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> @@ -46,16 +43,16 @@ int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> CPUSH4State *env = &cpu->env;
>
> env->tea = address;
> - env->exception_index = -1;
> + cs->exception_index = -1;
> switch (rw) {
> case 0:
> - env->exception_index = 0x0a0;
> + cs->exception_index = 0x0a0;
> break;
> case 1:
> - env->exception_index = 0x0c0;
> + cs->exception_index = 0x0c0;
> break;
> case 2:
> - env->exception_index = 0x0a0;
> + cs->exception_index = 0x0a0;
> break;
> }
> return 1;
> @@ -89,16 +86,16 @@ void superh_cpu_do_interrupt(CPUState *cs)
> SuperHCPU *cpu = SUPERH_CPU(cs);
> CPUSH4State *env = &cpu->env;
> int do_irq = cs->interrupt_request & CPU_INTERRUPT_HARD;
> - int do_exp, irq_vector = env->exception_index;
> + int do_exp, irq_vector = cs->exception_index;
>
> /* prioritize exceptions over interrupts */
>
> - do_exp = env->exception_index != -1;
> - do_irq = do_irq && (env->exception_index == -1);
> + do_exp = cs->exception_index != -1;
> + do_irq = do_irq && (cs->exception_index == -1);
>
> if (env->sr & SR_BL) {
> - if (do_exp && env->exception_index != 0x1e0) {
> - env->exception_index = 0x000; /* masked exception -> reset */
> + if (do_exp && cs->exception_index != 0x1e0) {
> + cs->exception_index = 0x000; /* masked exception -> reset */
> }
> if (do_irq && !env->in_sleep) {
> return; /* masked */
> @@ -116,7 +113,7 @@ void superh_cpu_do_interrupt(CPUState *cs)
>
> if (qemu_loglevel_mask(CPU_LOG_INT)) {
> const char *expname;
> - switch (env->exception_index) {
> + switch (cs->exception_index) {
> case 0x0e0:
> expname = "addr_error";
> break;
> @@ -180,8 +177,8 @@ void superh_cpu_do_interrupt(CPUState *cs)
> env->flags = 0;
>
> if (do_exp) {
> - env->expevt = env->exception_index;
> - switch (env->exception_index) {
> + env->expevt = cs->exception_index;
> + switch (cs->exception_index) {
> case 0x000:
> case 0x020:
> case 0x140:
> @@ -472,33 +469,33 @@ int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> switch (ret) {
> case MMU_ITLB_MISS:
> case MMU_DTLB_MISS_READ:
> - env->exception_index = 0x040;
> + cs->exception_index = 0x040;
> break;
> case MMU_DTLB_MULTIPLE:
> case MMU_ITLB_MULTIPLE:
> - env->exception_index = 0x140;
> + cs->exception_index = 0x140;
> break;
> case MMU_ITLB_VIOLATION:
> - env->exception_index = 0x0a0;
> + cs->exception_index = 0x0a0;
> break;
> case MMU_DTLB_MISS_WRITE:
> - env->exception_index = 0x060;
> + cs->exception_index = 0x060;
> break;
> case MMU_DTLB_INITIAL_WRITE:
> - env->exception_index = 0x080;
> + cs->exception_index = 0x080;
> break;
> case MMU_DTLB_VIOLATION_READ:
> - env->exception_index = 0x0a0;
> + cs->exception_index = 0x0a0;
> break;
> case MMU_DTLB_VIOLATION_WRITE:
> - env->exception_index = 0x0c0;
> + cs->exception_index = 0x0c0;
> break;
> case MMU_IADDR_ERROR:
> case MMU_DADDR_ERROR_READ:
> - env->exception_index = 0x0e0;
> + cs->exception_index = 0x0e0;
> break;
> case MMU_DADDR_ERROR_WRITE:
> - env->exception_index = 0x100;
> + cs->exception_index = 0x100;
> break;
> default:
> cpu_abort(env, "Unhandled MMU fault");
> @@ -702,8 +699,10 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
> if (entry->vpn == vpn
> && (!use_asid || entry->asid == asid || entry->sh)) {
> if (utlb_match_entry) {
> + CPUState *cs = CPU(sh_env_get_cpu(s));
> +
> /* Multiple TLB Exception */
> - s->exception_index = 0x140;
> + cs->exception_index = 0x140;
> s->tea = addr;
> break;
> }
> diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
> index 35f9067..03633f0 100644
> --- a/target-sh4/op_helper.c
> +++ b/target-sh4/op_helper.c
> @@ -69,7 +69,9 @@ void helper_ldtlb(CPUSH4State *env)
> static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
> uintptr_t retaddr)
> {
> - env->exception_index = index;
> + CPUState *cs = CPU(sh_env_get_cpu(env));
> +
> + cs->exception_index = index;
> if (retaddr) {
> cpu_restore_state(env, retaddr);
> }
> diff --git a/target-sparc/helper.c b/target-sparc/helper.c
> index 57c20af..a393ef0 100644
> --- a/target-sparc/helper.c
> +++ b/target-sparc/helper.c
> @@ -24,13 +24,17 @@
>
> void helper_raise_exception(CPUSPARCState *env, int tt)
> {
> - env->exception_index = tt;
> + CPUState *cs = CPU(sparc_env_get_cpu(env));
> +
> + cs->exception_index = tt;
> cpu_loop_exit(env);
> }
>
> void helper_debug(CPUSPARCState *env)
> {
> - env->exception_index = EXCP_DEBUG;
> + CPUState *cs = CPU(sparc_env_get_cpu(env));
> +
> + cs->exception_index = EXCP_DEBUG;
> cpu_loop_exit(env);
> }
>
> @@ -232,7 +236,7 @@ void helper_power_down(CPUSPARCState *env)
> CPUState *cs = CPU(sparc_env_get_cpu(env));
>
> cs->halted = 1;
> - env->exception_index = EXCP_HLT;
> + cs->exception_index = EXCP_HLT;
> env->pc = env->npc;
> env->npc = env->pc + 4;
> cpu_loop_exit(env);
> diff --git a/target-sparc/int32_helper.c b/target-sparc/int32_helper.c
> index d532238..f350a90 100644
> --- a/target-sparc/int32_helper.c
> +++ b/target-sparc/int32_helper.c
> @@ -62,7 +62,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
> {
> SPARCCPU *cpu = SPARC_CPU(cs);
> CPUSPARCState *env = &cpu->env;
> - int cwp, intno = env->exception_index;
> + int cwp, intno = cs->exception_index;
>
> /* Compute PSR before exposing state. */
> if (env->cc_op != CC_OP_FLAGS) {
> @@ -105,12 +105,12 @@ void sparc_cpu_do_interrupt(CPUState *cs)
> #endif
> #if !defined(CONFIG_USER_ONLY)
> if (env->psret == 0) {
> - if (env->exception_index == 0x80 &&
> + if (cs->exception_index == 0x80 &&
> env->def->features & CPU_FEATURE_TA0_SHUTDOWN) {
> qemu_system_shutdown_request();
> } else {
> cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
> - env->exception_index);
> + cs->exception_index);
> }
> return;
> }
> @@ -125,7 +125,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
> env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
> env->pc = env->tbr;
> env->npc = env->pc + 4;
> - env->exception_index = -1;
> + cs->exception_index = -1;
>
> #if !defined(CONFIG_USER_ONLY)
> /* IRQ acknowledgment */
> diff --git a/target-sparc/int64_helper.c b/target-sparc/int64_helper.c
> index bf7dd86..1744245 100644
> --- a/target-sparc/int64_helper.c
> +++ b/target-sparc/int64_helper.c
> @@ -63,7 +63,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
> {
> SPARCCPU *cpu = SPARC_CPU(cs);
> CPUSPARCState *env = &cpu->env;
> - int intno = env->exception_index;
> + int intno = cs->exception_index;
> trap_state *tsptr;
>
> /* Compute PSR before exposing state. */
> @@ -112,7 +112,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
> #if !defined(CONFIG_USER_ONLY)
> if (env->tl >= env->maxtl) {
> cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
> - " Error state", env->exception_index, env->tl, env->maxtl);
> + " Error state", cs->exception_index, env->tl, env->maxtl);
> return;
> }
> #endif
> @@ -160,7 +160,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
> env->tbr |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
> env->pc = env->tbr;
> env->npc = env->pc + 4;
> - env->exception_index = -1;
> + cs->exception_index = -1;
> }
>
> trap_state *cpu_tsptr(CPUSPARCState* env)
> diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
> index 2f55af9..af7c289 100644
> --- a/target-sparc/ldst_helper.c
> +++ b/target-sparc/ldst_helper.c
> @@ -1284,6 +1284,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
> uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
> int sign)
> {
> + CPUState *cs = CPU(sparc_env_get_cpu(env));
> uint64_t ret = 0;
> #if defined(DEBUG_ASI)
> target_ulong last_addr = addr;
> @@ -1317,7 +1318,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
> dump_asi("read ", last_addr, asi, size, ret);
> #endif
> /* env->exception_index is set in get_physical_address_data(). */
> - helper_raise_exception(env, env->exception_index);
> + helper_raise_exception(env, cs->exception_index);
> }
>
> /* convert nonfaulting load ASIs to normal load ASIs */
> diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
> index 0d88326..ea72657 100644
> --- a/target-sparc/mmu_helper.c
> +++ b/target-sparc/mmu_helper.c
> @@ -28,12 +28,10 @@
> int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> int mmu_idx)
> {
> - SPARCCPU *cpu = SPARC_CPU(cs);
> -
> if (rw & 2) {
> - cpu->env.exception_index = TT_TFAULT;
> + cs->exception_index = TT_TFAULT;
> } else {
> - cpu->env.exception_index = TT_DFAULT;
> + cs->exception_index = TT_DFAULT;
> }
> return 1;
> }
> @@ -238,9 +236,9 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> return 0;
> } else {
> if (rw & 2) {
> - env->exception_index = TT_TFAULT;
> + cs->exception_index = TT_TFAULT;
> } else {
> - env->exception_index = TT_DFAULT;
> + cs->exception_index = TT_DFAULT;
> }
> return 1;
> }
> @@ -489,6 +487,7 @@ static int get_physical_address_data(CPUSPARCState *env,
> hwaddr *physical, int *prot,
> target_ulong address, int rw, int mmu_idx)
> {
> + CPUState *cs = CPU(sparc_env_get_cpu(env));
> unsigned int i;
> uint64_t context;
> uint64_t sfsr = 0;
> @@ -553,10 +552,10 @@ static int get_physical_address_data(CPUSPARCState *env,
>
> if (do_fault) {
> /* faults above are reported with TT_DFAULT. */
> - env->exception_index = TT_DFAULT;
> + cs->exception_index = TT_DFAULT;
> } else if (!TTE_IS_W_OK(env->dtlb[i].tte) && (rw == 1)) {
> do_fault = 1;
> - env->exception_index = TT_DPROT;
> + cs->exception_index = TT_DPROT;
>
> trace_mmu_helper_dprot(address, context, mmu_idx, env->tl);
> }
> @@ -600,7 +599,7 @@ static int get_physical_address_data(CPUSPARCState *env,
> * - JPS1: SFAR updated and some fields of SFSR updated
> */
> env->dmmu.tag_access = (address & ~0x1fffULL) | context;
> - env->exception_index = TT_DMISS;
> + cs->exception_index = TT_DMISS;
> return 1;
> }
>
> @@ -608,6 +607,7 @@ static int get_physical_address_code(CPUSPARCState *env,
> hwaddr *physical, int *prot,
> target_ulong address, int mmu_idx)
> {
> + CPUState *cs = CPU(sparc_env_get_cpu(env));
> unsigned int i;
> uint64_t context;
>
> @@ -651,7 +651,7 @@ static int get_physical_address_code(CPUSPARCState *env,
>
> /* FIXME: ASI field in SFSR must be set */
> env->immu.sfsr |= SFSR_FT_PRIV_BIT | SFSR_VALID_BIT;
> - env->exception_index = TT_TFAULT;
> + cs->exception_index = TT_TFAULT;
>
> env->immu.tag_access = (address & ~0x1fffULL) | context;
>
> @@ -669,7 +669,7 @@ static int get_physical_address_code(CPUSPARCState *env,
>
> /* Context is stored in DMMU (dmmuregs[1]) also for IMMU */
> env->immu.tag_access = (address & ~0x1fffULL) | context;
> - env->exception_index = TT_TMISS;
> + cs->exception_index = TT_TMISS;
> return 1;
> }
>
> diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
> index 5cd2378..cd2cbef 100644
> --- a/target-unicore32/op_helper.c
> +++ b/target-unicore32/op_helper.c
> @@ -16,7 +16,9 @@
>
> void HELPER(exception)(CPUUniCore32State *env, uint32_t excp)
> {
> - env->exception_index = excp;
> + CPUState *cs = CPU(uc32_env_get_cpu(env));
> +
> + cs->exception_index = excp;
> cpu_loop_exit(env);
> }
>
> diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
> index 408f1b0..2e26fd1 100644
> --- a/target-unicore32/softmmu.c
> +++ b/target-unicore32/softmmu.c
> @@ -79,7 +79,7 @@ void uc32_cpu_do_interrupt(CPUState *cs)
> uint32_t addr;
> int new_mode;
>
> - switch (env->exception_index) {
> + switch (cs->exception_index) {
> case UC32_EXCP_PRIV:
> new_mode = ASR_MODE_PRIV;
> addr = 0x08;
> @@ -99,7 +99,7 @@ void uc32_cpu_do_interrupt(CPUState *cs)
> addr = 0x18;
> break;
> default:
> - cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
> + cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
> return;
> }
> /* High vectors. */
> @@ -256,9 +256,9 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> env->cp0.c3_faultstatus = ret;
> env->cp0.c4_faultaddr = address;
> if (access_type == 2) {
> - env->exception_index = UC32_EXCP_ITRAP;
> + cs->exception_index = UC32_EXCP_ITRAP;
> } else {
> - env->exception_index = UC32_EXCP_DTRAP;
> + cs->exception_index = UC32_EXCP_DTRAP;
> }
> return ret;
> }
> diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
> index a0f9993..f55095e 100644
> --- a/target-xtensa/helper.c
> +++ b/target-xtensa/helper.c
> @@ -169,6 +169,8 @@ static void handle_interrupt(CPUXtensaState *env)
> (env->config->level_mask[level] &
> env->sregs[INTSET] &
> env->sregs[INTENABLE])) {
> + CPUState *cs = CPU(xtensa_env_get_cpu(env));
> +
> if (level > 1) {
> env->sregs[EPC1 + level - 1] = env->pc;
> env->sregs[EPS2 + level - 2] = env->sregs[PS];
> @@ -185,10 +187,10 @@ static void handle_interrupt(CPUXtensaState *env)
> } else {
> env->sregs[EPC1] = env->pc;
> }
> - env->exception_index = EXC_DOUBLE;
> + cs->exception_index = EXC_DOUBLE;
> } else {
> env->sregs[EPC1] = env->pc;
> - env->exception_index =
> + cs->exception_index =
> (env->sregs[PS] & PS_UM) ? EXC_USER : EXC_KERNEL;
> }
> env->sregs[PS] |= PS_EXCM;
> @@ -202,7 +204,7 @@ void xtensa_cpu_do_interrupt(CPUState *cs)
> XtensaCPU *cpu = XTENSA_CPU(cs);
> CPUXtensaState *env = &cpu->env;
>
> - if (env->exception_index == EXC_IRQ) {
> + if (cs->exception_index == EXC_IRQ) {
> qemu_log_mask(CPU_LOG_INT,
> "%s(EXC_IRQ) level = %d, cintlevel = %d, "
> "pc = %08x, a0 = %08x, ps = %08x, "
> @@ -215,7 +217,7 @@ void xtensa_cpu_do_interrupt(CPUState *cs)
> handle_interrupt(env);
> }
>
> - switch (env->exception_index) {
> + switch (cs->exception_index) {
> case EXC_WINDOW_OVERFLOW4:
> case EXC_WINDOW_UNDERFLOW4:
> case EXC_WINDOW_OVERFLOW8:
> @@ -228,15 +230,15 @@ void xtensa_cpu_do_interrupt(CPUState *cs)
> case EXC_DEBUG:
> qemu_log_mask(CPU_LOG_INT, "%s(%d) "
> "pc = %08x, a0 = %08x, ps = %08x, ccount = %08x\n",
> - __func__, env->exception_index,
> + __func__, cs->exception_index,
> env->pc, env->regs[0], env->sregs[PS], env->sregs[CCOUNT]);
> - if (env->config->exception_vector[env->exception_index]) {
> + if (env->config->exception_vector[cs->exception_index]) {
> env->pc = relocated_vector(env,
> - env->config->exception_vector[env->exception_index]);
> + env->config->exception_vector[cs->exception_index]);
> env->exception_taken = 1;
> } else {
> qemu_log("%s(pc = %08x) bad exception_index: %d\n",
> - __func__, env->pc, env->exception_index);
> + __func__, env->pc, cs->exception_index);
> }
> break;
>
> @@ -245,7 +247,7 @@ void xtensa_cpu_do_interrupt(CPUState *cs)
>
> default:
> qemu_log("%s(pc = %08x) unknown exception_index: %d\n",
> - __func__, env->pc, env->exception_index);
> + __func__, env->pc, cs->exception_index);
> break;
> }
> check_interrupts(env);
> diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
> index cf97025..2e006e4 100644
> --- a/target-xtensa/op_helper.c
> +++ b/target-xtensa/op_helper.c
> @@ -96,7 +96,9 @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
>
> void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
> {
> - env->exception_index = excp;
> + CPUState *cs = CPU(xtensa_env_get_cpu(env));
> +
> + cs->exception_index = excp;
> if (excp == EXCP_DEBUG) {
> env->exception_taken = 0;
> }
> diff --git a/user-exec.c b/user-exec.c
> index dec636e..dbb9c8d 100644
> --- a/user-exec.c
> +++ b/user-exec.c
> @@ -41,7 +41,9 @@
> static void exception_action(CPUArchState *env1)
> {
> #if defined(TARGET_I386)
> - raise_exception_err(env1, env1->exception_index, env1->error_code);
> + CPUState *cpu = ENV_GET_CPU(env1);
> +
> + raise_exception_err(env1, cpu->exception_index, env1->error_code);
> #else
> cpu_loop_exit(env1);
> #endif
> @@ -71,7 +73,7 @@ void cpu_resume_from_signal(CPUArchState *env1, void *puc)
> sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
> #endif
> }
> - env1->exception_index = -1;
> + cpu->exception_index = -1;
> siglongjmp(cpu->jmp_env, 1);
> }
target-openrisc: Tested-by: Jia Liu <proljc@gmail.com>
>
> --
> 1.8.1.4
>
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [RFC qom-cpu 12/41] cpu: Move cpu_copy() into linux-user
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (10 preceding siblings ...)
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 11/41] cpu: Move exception_index " Andreas Färber
@ 2013-09-04 9:04 ` Andreas Färber
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 13/41] cpu: Drop cpu_model_str from CPU_COMMON Andreas Färber
` (31 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Riku Voipio, Andreas Färber
It is only used there and is deemed very fragile if not incorrect in its
current memcpy() form. Moving it into linux-user will allow to move
parts into target_cpu.h headers and only copy what the ABI mandates.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
exec.c | 32 --------------------------------
linux-user/main.c | 31 +++++++++++++++++++++++++++++++
2 files changed, 31 insertions(+), 32 deletions(-)
diff --git a/exec.c b/exec.c
index 508f1e2..93958c3 100644
--- a/exec.c
+++ b/exec.c
@@ -625,38 +625,6 @@ void cpu_abort(CPUArchState *env, const char *fmt, ...)
abort();
}
-CPUArchState *cpu_copy(CPUArchState *env)
-{
- CPUArchState *new_env = cpu_init(env->cpu_model_str);
-#if defined(TARGET_HAS_ICE)
- CPUBreakpoint *bp;
- CPUWatchpoint *wp;
-#endif
-
- /* Reset non arch specific state */
- cpu_reset(ENV_GET_CPU(new_env));
-
- /* Copy arch specific state into the new CPU */
- memcpy(new_env, env, sizeof(CPUArchState));
-
- /* Clone all break/watchpoints.
- Note: Once we support ptrace with hw-debug register access, make sure
- BP_CPU break/watchpoints are handled correctly on clone. */
- QTAILQ_INIT(&env->breakpoints);
- QTAILQ_INIT(&env->watchpoints);
-#if defined(TARGET_HAS_ICE)
- QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
- cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
- }
- QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
- cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1,
- wp->flags, NULL);
- }
-#endif
-
- return new_env;
-}
-
#if !defined(CONFIG_USER_ONLY)
static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t end,
uintptr_t length)
diff --git a/linux-user/main.c b/linux-user/main.c
index 5c2f7b2..afc3ce4 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3189,6 +3189,37 @@ void init_task_state(TaskState *ts)
ts->sigqueue_table[i].next = NULL;
}
+CPUArchState *cpu_copy(CPUArchState *env)
+{
+ CPUArchState *new_env = cpu_init(env->cpu_model_str);
+#if defined(TARGET_HAS_ICE)
+ CPUBreakpoint *bp;
+ CPUWatchpoint *wp;
+#endif
+
+ /* Reset non arch specific state */
+ cpu_reset(ENV_GET_CPU(new_env));
+
+ memcpy(new_env, env, sizeof(CPUArchState));
+
+ /* Clone all break/watchpoints.
+ Note: Once we support ptrace with hw-debug register access, make sure
+ BP_CPU break/watchpoints are handled correctly on clone. */
+ QTAILQ_INIT(&env->breakpoints);
+ QTAILQ_INIT(&env->watchpoints);
+#if defined(TARGET_HAS_ICE)
+ QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
+ }
+ QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
+ cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1,
+ wp->flags, NULL);
+ }
+#endif
+
+ return new_env;
+}
+
static void handle_arg_help(const char *arg)
{
usage();
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 13/41] cpu: Drop cpu_model_str from CPU_COMMON
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (11 preceding siblings ...)
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 12/41] cpu: Move cpu_copy() into linux-user Andreas Färber
@ 2013-09-04 9:04 ` Andreas Färber
2013-09-04 12:47 ` Jia Liu
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 14/41] cpu: Move opaque field from CPU_COMMON to CPUState Andreas Färber
` (30 subsequent siblings)
43 siblings, 1 reply; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:04 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Anthony Green, Riku Voipio,
Alexander Graf, Blue Swirl, open list:PowerPC, Paul Brook,
Guan Xuetao, Andreas Färber, Aurelien Jarno,
Richard Henderson
Since this is only read in cpu_copy() and linux-user has a global
cpu_model, drop the field from generic code.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
include/exec/cpu-defs.h | 2 --
linux-user/main.c | 4 ++--
target-alpha/cpu.c | 4 ----
target-arm/helper.c | 3 ---
target-i386/cpu.c | 3 ---
target-m68k/helper.c | 1 -
target-mips/translate.c | 1 -
target-moxie/cpu.c | 1 -
target-openrisc/cpu.c | 1 -
target-ppc/translate_init.c | 3 ---
target-s390x/helper.c | 3 ---
target-sh4/cpu.c | 3 ---
target-sparc/cpu.c | 1 -
target-unicore32/helper.c | 1 -
14 files changed, 2 insertions(+), 29 deletions(-)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 6801968..512f2ed 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -140,7 +140,5 @@ typedef struct CPUWatchpoint {
\
/* user data */ \
void *opaque; \
- \
- const char *cpu_model_str;
#endif
diff --git a/linux-user/main.c b/linux-user/main.c
index afc3ce4..d556881 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -42,7 +42,7 @@ const char *filename;
const char *argv0;
int gdbstub_port;
envlist_t *envlist;
-const char *cpu_model;
+static const char *cpu_model;
unsigned long mmap_min_addr;
#if defined(CONFIG_USE_GUEST_BASE)
unsigned long guest_base;
@@ -3191,7 +3191,7 @@ void init_task_state(TaskState *ts)
CPUArchState *cpu_copy(CPUArchState *env)
{
- CPUArchState *new_env = cpu_init(env->cpu_model_str);
+ CPUArchState *new_env = cpu_init(cpu_model);
#if defined(TARGET_HAS_ICE)
CPUBreakpoint *bp;
CPUWatchpoint *wp;
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index e880983..9931f9f 100644
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -182,7 +182,6 @@ static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model)
AlphaCPU *cpu_alpha_init(const char *cpu_model)
{
AlphaCPU *cpu;
- CPUAlphaState *env;
ObjectClass *cpu_class;
cpu_class = alpha_cpu_class_by_name(cpu_model);
@@ -191,9 +190,6 @@ AlphaCPU *cpu_alpha_init(const char *cpu_model)
cpu_class = object_class_by_name(TYPE("ev67"));
}
cpu = ALPHA_CPU(object_new(object_class_get_name(cpu_class)));
- env = &cpu->env;
-
- env->cpu_model_str = cpu_model;
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 508a7fc..bc00858 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1748,7 +1748,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
ARMCPU *cpu_arm_init(const char *cpu_model)
{
ARMCPU *cpu;
- CPUARMState *env;
ObjectClass *oc;
oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
@@ -1756,8 +1755,6 @@ ARMCPU *cpu_arm_init(const char *cpu_model)
return NULL;
}
cpu = ARM_CPU(object_new(object_class_get_name(oc)));
- env = &cpu->env;
- env->cpu_model_str = cpu_model;
/* TODO this should be set centrally, once possible */
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 3ed5a11..89e3217 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1896,7 +1896,6 @@ X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
Error **errp)
{
X86CPU *cpu = NULL;
- CPUX86State *env;
gchar **model_pieces;
char *name, *features;
char *typename;
@@ -1919,8 +1918,6 @@ X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
object_unref(OBJECT(cpu));
#endif
- env = &cpu->env;
- env->cpu_model_str = cpu_model;
cpu_x86_register(cpu, name, &error);
if (error) {
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 003a298..e38065c 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -110,7 +110,6 @@ M68kCPU *cpu_m68k_init(const char *cpu_model)
}
cpu = M68K_CPU(object_new(object_class_get_name(oc)));
env = &cpu->env;
- env->cpu_model_str = cpu_model;
register_m68k_insns(env);
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 716d50c..453918d 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -15907,7 +15907,6 @@ MIPSCPU *cpu_mips_init(const char *cpu_model)
cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU));
env = &cpu->env;
env->cpu_model = def;
- env->cpu_model_str = cpu_model;
#ifndef CONFIG_USER_ONLY
mmu_init(env, def);
diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
index e07a4df..ab9d2cc 100644
--- a/target-moxie/cpu.c
+++ b/target-moxie/cpu.c
@@ -157,7 +157,6 @@ MoxieCPU *cpu_moxie_init(const char *cpu_model)
return NULL;
}
cpu = MOXIE_CPU(object_new(object_class_get_name(oc)));
- cpu->env.cpu_model_str = cpu_model;
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index b233969..b7104e3 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -241,7 +241,6 @@ OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
return NULL;
}
cpu = OPENRISC_CPU(object_new(object_class_get_name(oc)));
- cpu->env.cpu_model_str = cpu_model;
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 0934a45..db5e526 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8267,7 +8267,6 @@ static ObjectClass *ppc_cpu_class_by_name(const char *name)
PowerPCCPU *cpu_ppc_init(const char *cpu_model)
{
PowerPCCPU *cpu;
- CPUPPCState *env;
ObjectClass *oc;
Error *err = NULL;
@@ -8277,8 +8276,6 @@ PowerPCCPU *cpu_ppc_init(const char *cpu_model)
}
cpu = POWERPC_CPU(object_new(object_class_get_name(oc)));
- env = &cpu->env;
- env->cpu_model_str = cpu_model;
object_property_set_bool(OBJECT(cpu), true, "realized", &err);
if (err != NULL) {
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index c9d3d55..e1ed6c0 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -73,11 +73,8 @@ void s390x_cpu_timer(void *opaque)
S390CPU *cpu_s390x_init(const char *cpu_model)
{
S390CPU *cpu;
- CPUS390XState *env;
cpu = S390_CPU(object_new(TYPE_S390_CPU));
- env = &cpu->env;
- env->cpu_model_str = cpu_model;
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index 7f98f80..1f1b8fd 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -172,7 +172,6 @@ static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
SuperHCPU *cpu_sh4_init(const char *cpu_model)
{
SuperHCPU *cpu;
- CPUSH4State *env;
ObjectClass *oc;
oc = superh_cpu_class_by_name(cpu_model);
@@ -180,8 +179,6 @@ SuperHCPU *cpu_sh4_init(const char *cpu_model)
return NULL;
}
cpu = SUPERH_CPU(object_new(object_class_get_name(oc)));
- env = &cpu->env;
- env->cpu_model_str = cpu_model;
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index c8d8c55..9443713 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -84,7 +84,6 @@ static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
env->def->features |= CPU_FEATURE_FLOAT128;
}
#endif
- env->cpu_model_str = cpu_model;
env->version = def->iu_version;
env->fsr = def->fpu_version;
env->nwindows = def->nwindows;
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index 4e90cf3..eece271 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -37,7 +37,6 @@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
}
cpu = UNICORE32_CPU(object_new(object_class_get_name(oc)));
env = &cpu->env;
- env->cpu_model_str = cpu_model;
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 13/41] cpu: Drop cpu_model_str from CPU_COMMON
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 13/41] cpu: Drop cpu_model_str from CPU_COMMON Andreas Färber
@ 2013-09-04 12:47 ` Jia Liu
0 siblings, 0 replies; 68+ messages in thread
From: Jia Liu @ 2013-09-04 12:47 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Anthony Green, Riku Voipio, qemu-devel@nongnu.org,
Alexander Graf, Blue Swirl, open list:PowerPC, Paul Brook,
Guan Xuetao, Aurelien Jarno, Richard Henderson
On Wed, Sep 4, 2013 at 5:04 PM, Andreas Färber <afaerber@suse.de> wrote:
> Since this is only read in cpu_copy() and linux-user has a global
> cpu_model, drop the field from generic code.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
> include/exec/cpu-defs.h | 2 --
> linux-user/main.c | 4 ++--
> target-alpha/cpu.c | 4 ----
> target-arm/helper.c | 3 ---
> target-i386/cpu.c | 3 ---
> target-m68k/helper.c | 1 -
> target-mips/translate.c | 1 -
> target-moxie/cpu.c | 1 -
> target-openrisc/cpu.c | 1 -
> target-ppc/translate_init.c | 3 ---
> target-s390x/helper.c | 3 ---
> target-sh4/cpu.c | 3 ---
> target-sparc/cpu.c | 1 -
> target-unicore32/helper.c | 1 -
> 14 files changed, 2 insertions(+), 29 deletions(-)
>
> diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
> index 6801968..512f2ed 100644
> --- a/include/exec/cpu-defs.h
> +++ b/include/exec/cpu-defs.h
> @@ -140,7 +140,5 @@ typedef struct CPUWatchpoint {
> \
> /* user data */ \
> void *opaque; \
> - \
> - const char *cpu_model_str;
>
> #endif
> diff --git a/linux-user/main.c b/linux-user/main.c
> index afc3ce4..d556881 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -42,7 +42,7 @@ const char *filename;
> const char *argv0;
> int gdbstub_port;
> envlist_t *envlist;
> -const char *cpu_model;
> +static const char *cpu_model;
> unsigned long mmap_min_addr;
> #if defined(CONFIG_USE_GUEST_BASE)
> unsigned long guest_base;
> @@ -3191,7 +3191,7 @@ void init_task_state(TaskState *ts)
>
> CPUArchState *cpu_copy(CPUArchState *env)
> {
> - CPUArchState *new_env = cpu_init(env->cpu_model_str);
> + CPUArchState *new_env = cpu_init(cpu_model);
> #if defined(TARGET_HAS_ICE)
> CPUBreakpoint *bp;
> CPUWatchpoint *wp;
> diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
> index e880983..9931f9f 100644
> --- a/target-alpha/cpu.c
> +++ b/target-alpha/cpu.c
> @@ -182,7 +182,6 @@ static ObjectClass *alpha_cpu_class_by_name(const char *cpu_model)
> AlphaCPU *cpu_alpha_init(const char *cpu_model)
> {
> AlphaCPU *cpu;
> - CPUAlphaState *env;
> ObjectClass *cpu_class;
>
> cpu_class = alpha_cpu_class_by_name(cpu_model);
> @@ -191,9 +190,6 @@ AlphaCPU *cpu_alpha_init(const char *cpu_model)
> cpu_class = object_class_by_name(TYPE("ev67"));
> }
> cpu = ALPHA_CPU(object_new(object_class_get_name(cpu_class)));
> - env = &cpu->env;
> -
> - env->cpu_model_str = cpu_model;
>
> object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 508a7fc..bc00858 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1748,7 +1748,6 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> ARMCPU *cpu_arm_init(const char *cpu_model)
> {
> ARMCPU *cpu;
> - CPUARMState *env;
> ObjectClass *oc;
>
> oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
> @@ -1756,8 +1755,6 @@ ARMCPU *cpu_arm_init(const char *cpu_model)
> return NULL;
> }
> cpu = ARM_CPU(object_new(object_class_get_name(oc)));
> - env = &cpu->env;
> - env->cpu_model_str = cpu_model;
>
> /* TODO this should be set centrally, once possible */
> object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 3ed5a11..89e3217 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -1896,7 +1896,6 @@ X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
> Error **errp)
> {
> X86CPU *cpu = NULL;
> - CPUX86State *env;
> gchar **model_pieces;
> char *name, *features;
> char *typename;
> @@ -1919,8 +1918,6 @@ X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
> qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
> object_unref(OBJECT(cpu));
> #endif
> - env = &cpu->env;
> - env->cpu_model_str = cpu_model;
>
> cpu_x86_register(cpu, name, &error);
> if (error) {
> diff --git a/target-m68k/helper.c b/target-m68k/helper.c
> index 003a298..e38065c 100644
> --- a/target-m68k/helper.c
> +++ b/target-m68k/helper.c
> @@ -110,7 +110,6 @@ M68kCPU *cpu_m68k_init(const char *cpu_model)
> }
> cpu = M68K_CPU(object_new(object_class_get_name(oc)));
> env = &cpu->env;
> - env->cpu_model_str = cpu_model;
>
> register_m68k_insns(env);
>
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 716d50c..453918d 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -15907,7 +15907,6 @@ MIPSCPU *cpu_mips_init(const char *cpu_model)
> cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU));
> env = &cpu->env;
> env->cpu_model = def;
> - env->cpu_model_str = cpu_model;
>
> #ifndef CONFIG_USER_ONLY
> mmu_init(env, def);
> diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
> index e07a4df..ab9d2cc 100644
> --- a/target-moxie/cpu.c
> +++ b/target-moxie/cpu.c
> @@ -157,7 +157,6 @@ MoxieCPU *cpu_moxie_init(const char *cpu_model)
> return NULL;
> }
> cpu = MOXIE_CPU(object_new(object_class_get_name(oc)));
> - cpu->env.cpu_model_str = cpu_model;
>
> object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
>
> diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
> index b233969..b7104e3 100644
> --- a/target-openrisc/cpu.c
> +++ b/target-openrisc/cpu.c
> @@ -241,7 +241,6 @@ OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
> return NULL;
> }
> cpu = OPENRISC_CPU(object_new(object_class_get_name(oc)));
> - cpu->env.cpu_model_str = cpu_model;
>
> object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
>
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 0934a45..db5e526 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8267,7 +8267,6 @@ static ObjectClass *ppc_cpu_class_by_name(const char *name)
> PowerPCCPU *cpu_ppc_init(const char *cpu_model)
> {
> PowerPCCPU *cpu;
> - CPUPPCState *env;
> ObjectClass *oc;
> Error *err = NULL;
>
> @@ -8277,8 +8276,6 @@ PowerPCCPU *cpu_ppc_init(const char *cpu_model)
> }
>
> cpu = POWERPC_CPU(object_new(object_class_get_name(oc)));
> - env = &cpu->env;
> - env->cpu_model_str = cpu_model;
>
> object_property_set_bool(OBJECT(cpu), true, "realized", &err);
> if (err != NULL) {
> diff --git a/target-s390x/helper.c b/target-s390x/helper.c
> index c9d3d55..e1ed6c0 100644
> --- a/target-s390x/helper.c
> +++ b/target-s390x/helper.c
> @@ -73,11 +73,8 @@ void s390x_cpu_timer(void *opaque)
> S390CPU *cpu_s390x_init(const char *cpu_model)
> {
> S390CPU *cpu;
> - CPUS390XState *env;
>
> cpu = S390_CPU(object_new(TYPE_S390_CPU));
> - env = &cpu->env;
> - env->cpu_model_str = cpu_model;
>
> object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
>
> diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
> index 7f98f80..1f1b8fd 100644
> --- a/target-sh4/cpu.c
> +++ b/target-sh4/cpu.c
> @@ -172,7 +172,6 @@ static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
> SuperHCPU *cpu_sh4_init(const char *cpu_model)
> {
> SuperHCPU *cpu;
> - CPUSH4State *env;
> ObjectClass *oc;
>
> oc = superh_cpu_class_by_name(cpu_model);
> @@ -180,8 +179,6 @@ SuperHCPU *cpu_sh4_init(const char *cpu_model)
> return NULL;
> }
> cpu = SUPERH_CPU(object_new(object_class_get_name(oc)));
> - env = &cpu->env;
> - env->cpu_model_str = cpu_model;
>
> object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
>
> diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
> index c8d8c55..9443713 100644
> --- a/target-sparc/cpu.c
> +++ b/target-sparc/cpu.c
> @@ -84,7 +84,6 @@ static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
> env->def->features |= CPU_FEATURE_FLOAT128;
> }
> #endif
> - env->cpu_model_str = cpu_model;
> env->version = def->iu_version;
> env->fsr = def->fpu_version;
> env->nwindows = def->nwindows;
> diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
> index 4e90cf3..eece271 100644
> --- a/target-unicore32/helper.c
> +++ b/target-unicore32/helper.c
> @@ -37,7 +37,6 @@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
> }
> cpu = UNICORE32_CPU(object_new(object_class_get_name(oc)));
> env = &cpu->env;
> - env->cpu_model_str = cpu_model;
>
> object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
>
target-openrisc: Tested-by: Jia Liu <proljc@gmail.com>
> --
> 1.8.1.4
>
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [RFC qom-cpu 14/41] cpu: Move opaque field from CPU_COMMON to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (12 preceding siblings ...)
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 13/41] cpu: Drop cpu_model_str from CPU_COMMON Andreas Färber
@ 2013-09-04 9:04 ` Andreas Färber
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 15/41] cpu: Move watchpoint fields " Andreas Färber
` (29 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:04 UTC (permalink / raw)
To: qemu-devel
Cc: Blue Swirl, Peter Maydell, Riku Voipio, Andreas Färber,
Paul Brook
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
bsd-user/main.c | 2 +-
gdbstub.c | 3 +--
include/exec/cpu-defs.h | 3 ---
include/qom/cpu.h | 3 +++
linux-user/elfload.c | 10 ++++++----
linux-user/linuxload.c | 3 +--
linux-user/m68k/target_cpu.h | 4 +++-
linux-user/main.c | 6 +++---
linux-user/signal.c | 17 +++++++++++------
linux-user/syscall.c | 30 ++++++++++++++++++------------
linux-user/vm86.c | 27 ++++++++++++++++++---------
target-arm/arm-semi.c | 9 +++++----
target-m68k/m68k-semi.c | 3 ++-
13 files changed, 72 insertions(+), 48 deletions(-)
diff --git a/bsd-user/main.c b/bsd-user/main.c
index f9246aa..f81ba55 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -1000,7 +1000,7 @@ int main(int argc, char **argv)
memset(ts, 0, sizeof(TaskState));
init_task_state(ts);
ts->info = info;
- env->opaque = ts;
+ cpu->opaque = ts;
#if defined(TARGET_I386)
cpu_x86_set_cpl(env, 3);
diff --git a/gdbstub.c b/gdbstub.c
index 2b7f22b..dac99b3 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1089,8 +1089,7 @@ static int gdb_handle_packet(GDBState *s, const char *line_buf)
}
#ifdef CONFIG_USER_ONLY
else if (strncmp(p, "Offsets", 7) == 0) {
- CPUArchState *env = s->c_cpu->env_ptr;
- TaskState *ts = env->opaque;
+ TaskState *ts = s->c_cpu->opaque;
snprintf(buf, sizeof(buf),
"Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 512f2ed..be9569c 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -137,8 +137,5 @@ typedef struct CPUWatchpoint {
\
QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
CPUWatchpoint *watchpoint_hit; \
- \
- /* user data */ \
- void *opaque; \
#endif
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 8191a80..828c833 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -187,6 +187,7 @@ struct kvm_run;
* @gdb_num_regs: Number of total registers accessible to GDB.
* @gdb_num_g_regs: Number of registers in GDB 'g' packets.
* @next_cpu: Next CPU sharing TB cache.
+ * @opaque: User data.
* @mem_io_pc: Host Program Counter at which the memory was accessed.
* @mem_io_vaddr: Target virtual address at which the memory was accessed.
* @kvm_fd: vCPU file descriptor for KVM.
@@ -230,6 +231,8 @@ struct CPUState {
int gdb_num_g_regs;
QTAILQ_ENTRY(CPUState) node;
+ void *opaque;
+
/* In order to avoid passing too many arguments to the MMIO helpers,
* we store some rarely used information in the CPU context.
*/
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 72d9270..41eff49 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -2611,7 +2611,8 @@ static int write_note(struct memelfnote *men, int fd)
static void fill_thread_info(struct elf_note_info *info, const CPUArchState *env)
{
- TaskState *ts = (TaskState *)env->opaque;
+ CPUState *cpu = ENV_GET_CPU((CPUArchState *)env);
+ TaskState *ts = (TaskState *)cpu->opaque;
struct elf_thread_status *ets;
ets = g_malloc0(sizeof (*ets));
@@ -2630,8 +2631,8 @@ static int fill_note_info(struct elf_note_info *info,
long signr, const CPUArchState *env)
{
#define NUMNOTES 3
- CPUState *cpu = NULL;
- TaskState *ts = (TaskState *)env->opaque;
+ CPUState *cpu = ENV_GET_CPU((CPUArchState *)env);
+ TaskState *ts = (TaskState *)cpu->opaque;
int i;
(void) memset(info, 0, sizeof (*info));
@@ -2759,7 +2760,8 @@ static int write_note_info(struct elf_note_info *info, int fd)
*/
static int elf_core_dump(int signr, const CPUArchState *env)
{
- const TaskState *ts = (const TaskState *)env->opaque;
+ const CPUState *cpu = ENV_GET_CPU((CPUArchState *)env);
+ const TaskState *ts = (const TaskState *)cpu->opaque;
struct vm_area_struct *vma = NULL;
char corefile[PATH_MAX];
struct elf_note_info info;
diff --git a/linux-user/linuxload.c b/linux-user/linuxload.c
index 5cd6d91..9caa268 100644
--- a/linux-user/linuxload.c
+++ b/linux-user/linuxload.c
@@ -89,8 +89,7 @@ static int prepare_binprm(struct linux_binprm *bprm)
abi_ulong loader_build_argptr(int envc, int argc, abi_ulong sp,
abi_ulong stringp, int push_ptr)
{
- CPUArchState *env = thread_cpu->env_ptr;
- TaskState *ts = (TaskState *)env->opaque;
+ TaskState *ts = (TaskState *)thread_cpu->opaque;
int n = sizeof(abi_ulong);
abi_ulong envp;
abi_ulong argv;
diff --git a/linux-user/m68k/target_cpu.h b/linux-user/m68k/target_cpu.h
index cad9c90..bb4d3fa 100644
--- a/linux-user/m68k/target_cpu.h
+++ b/linux-user/m68k/target_cpu.h
@@ -31,7 +31,9 @@ static inline void cpu_clone_regs(CPUM68KState *env, target_ulong newsp)
static inline void cpu_set_tls(CPUM68KState *env, target_ulong newtls)
{
- TaskState *ts = env->opaque;
+ CPUState *cs = CPU(m68k_env_get_cpu(env));
+ TaskState *ts = cs->opaque;
+
ts->tp_value = newtls;
}
diff --git a/linux-user/main.c b/linux-user/main.c
index d556881..ac78024 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -676,7 +676,7 @@ void cpu_loop(CPUARMState *env)
switch(trapnr) {
case EXCP_UDEF:
{
- TaskState *ts = env->opaque;
+ TaskState *ts = cs->opaque;
uint32_t opcode;
int rc;
@@ -2721,7 +2721,7 @@ void cpu_loop(CPUM68KState *env)
int trapnr;
unsigned int n;
target_siginfo_t info;
- TaskState *ts = env->opaque;
+ TaskState *ts = cs->opaque;
for(;;) {
trapnr = cpu_m68k_exec(env);
@@ -3753,7 +3753,7 @@ int main(int argc, char **argv, char **envp)
/* build Task State */
ts->info = info;
ts->bprm = &bprm;
- env->opaque = ts;
+ cpu->opaque = ts;
task_settid(ts);
ret = loader_exec(filename, target_argv, target_environ, regs,
diff --git a/linux-user/signal.c b/linux-user/signal.c
index 6e51519..a46216f 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -370,7 +370,8 @@ void signal_init(void)
static inline struct sigqueue *alloc_sigqueue(CPUArchState *env)
{
- TaskState *ts = env->opaque;
+ CPUState *cpu = ENV_GET_CPU(env);
+ TaskState *ts = cpu->opaque;
struct sigqueue *q = ts->first_free;
if (!q)
return NULL;
@@ -380,7 +381,9 @@ static inline struct sigqueue *alloc_sigqueue(CPUArchState *env)
static inline void free_sigqueue(CPUArchState *env, struct sigqueue *q)
{
- TaskState *ts = env->opaque;
+ CPUState *cpu = ENV_GET_CPU(env);
+ TaskState *ts = cpu->opaque;
+
q->next = ts->first_free;
ts->first_free = q;
}
@@ -388,8 +391,9 @@ static inline void free_sigqueue(CPUArchState *env, struct sigqueue *q)
/* abort execution with signal */
static void QEMU_NORETURN force_sig(int target_sig)
{
- CPUArchState *env = thread_cpu->env_ptr;
- TaskState *ts = (TaskState *)env->opaque;
+ CPUState *cpu = thread_cpu;
+ CPUArchState *env = cpu->env_ptr;
+ TaskState *ts = (TaskState *)cpu->opaque;
int host_sig, core_dumped = 0;
struct sigaction act;
host_sig = target_to_host_signal(target_sig);
@@ -439,7 +443,8 @@ static void QEMU_NORETURN force_sig(int target_sig)
as possible */
int queue_signal(CPUArchState *env, int sig, target_siginfo_t *info)
{
- TaskState *ts = env->opaque;
+ CPUState *cpu = ENV_GET_CPU(env);
+ TaskState *ts = cpu->opaque;
struct emulated_sigtable *k;
struct sigqueue *q, **pq;
abi_ulong handler;
@@ -5399,7 +5404,7 @@ void process_pending_signals(CPUArchState *cpu_env)
struct emulated_sigtable *k;
struct target_sigaction *sa;
struct sigqueue *q;
- TaskState *ts = cpu_env->opaque;
+ TaskState *ts = cpu->opaque;
if (!ts->signal_pending)
return;
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index ecead51..c25eb4b 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -4246,7 +4246,7 @@ static void *clone_func(void *arg)
env = info->env;
cpu = ENV_GET_CPU(env);
thread_cpu = cpu;
- ts = (TaskState *)env->opaque;
+ ts = (TaskState *)cpu->opaque;
info->tid = gettid();
cpu->host_tid = info->tid;
task_settid(ts);
@@ -4274,8 +4274,10 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp,
abi_ulong parent_tidptr, target_ulong newtls,
abi_ulong child_tidptr)
{
+ CPUState *cpu = ENV_GET_CPU(env);
int ret;
TaskState *ts;
+ CPUState *new_cpu;
CPUArchState *new_env;
unsigned int nptl_flags;
sigset_t sigmask;
@@ -4285,7 +4287,7 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp,
flags &= ~(CLONE_VFORK | CLONE_VM);
if (flags & CLONE_VM) {
- TaskState *parent_ts = (TaskState *)env->opaque;
+ TaskState *parent_ts = (TaskState *)cpu->opaque;
new_thread_info info;
pthread_attr_t attr;
@@ -4295,7 +4297,8 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp,
new_env = cpu_copy(env);
/* Init regs that differ from the parent. */
cpu_clone_regs(new_env, newsp);
- new_env->opaque = ts;
+ new_cpu = ENV_GET_CPU(new_env);
+ new_cpu->opaque = ts;
ts->bprm = parent_ts->bprm;
ts->info = parent_ts->info;
nptl_flags = flags;
@@ -4367,7 +4370,7 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp,
put_user_u32(gettid(), child_tidptr);
if (flags & CLONE_PARENT_SETTID)
put_user_u32(gettid(), parent_tidptr);
- ts = (TaskState *)env->opaque;
+ ts = (TaskState *)cpu->opaque;
if (flags & CLONE_SETTLS)
cpu_set_tls (env, newtls);
if (flags & CLONE_CHILD_CLEARTID)
@@ -4898,7 +4901,8 @@ int get_osversion(void)
static int open_self_maps(void *cpu_env, int fd)
{
#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICORE32)
- TaskState *ts = ((CPUArchState *)cpu_env)->opaque;
+ CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env);
+ TaskState *ts = cpu->opaque;
#endif
FILE *fp;
char *line = NULL;
@@ -4950,7 +4954,8 @@ static int open_self_maps(void *cpu_env, int fd)
static int open_self_stat(void *cpu_env, int fd)
{
- TaskState *ts = ((CPUArchState *)cpu_env)->opaque;
+ CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env);
+ TaskState *ts = cpu->opaque;
abi_ulong start_stack = ts->info->start_stack;
int i;
@@ -4986,7 +4991,8 @@ static int open_self_stat(void *cpu_env, int fd)
static int open_self_auxv(void *cpu_env, int fd)
{
- TaskState *ts = ((CPUArchState *)cpu_env)->opaque;
+ CPUState *cpu = ENV_GET_CPU((CPUArchState *)cpu_env);
+ TaskState *ts = cpu->opaque;
abi_ulong auxv = ts->info->saved_auxv;
abi_ulong len = ts->info->auxv_len;
char *ptr;
@@ -5120,14 +5126,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
/* Remove the CPU from the list. */
QTAILQ_REMOVE(&cpus, cpu, node);
cpu_list_unlock();
- ts = ((CPUArchState *)cpu_env)->opaque;
+ ts = cpu->opaque;
if (ts->child_tidptr) {
put_user_u32(0, ts->child_tidptr);
sys_futex(g2h(ts->child_tidptr), FUTEX_WAKE, INT_MAX,
NULL, NULL, 0);
}
thread_cpu = NULL;
- object_unref(OBJECT(ENV_GET_CPU(cpu_env)));
+ object_unref(OBJECT(cpu));
g_free(ts);
pthread_exit(NULL);
}
@@ -6424,7 +6430,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
break;
case TARGET_NR_mprotect:
{
- TaskState *ts = ((CPUArchState *)cpu_env)->opaque;
+ TaskState *ts = cpu->opaque;
/* Special hack to detect libc making the stack executable. */
if ((arg3 & PROT_GROWSDOWN)
&& arg1 >= ts->info->stack_limit
@@ -8508,7 +8514,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
break;
#elif defined(TARGET_M68K)
{
- TaskState *ts = ((CPUArchState *)cpu_env)->opaque;
+ TaskState *ts = cpu->opaque;
ts->tp_value = arg1;
ret = 0;
break;
@@ -8524,7 +8530,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
break;
#elif defined(TARGET_M68K)
{
- TaskState *ts = ((CPUArchState *)cpu_env)->opaque;
+ TaskState *ts = cpu->opaque;
ret = ts->tp_value;
break;
}
diff --git a/linux-user/vm86.c b/linux-user/vm86.c
index 2c4ffeb..45ef559 100644
--- a/linux-user/vm86.c
+++ b/linux-user/vm86.c
@@ -72,7 +72,8 @@ static inline unsigned int vm_getl(uint32_t segptr, unsigned int reg16)
void save_v86_state(CPUX86State *env)
{
- TaskState *ts = env->opaque;
+ CPUState *cs = CPU(x86_env_get_cpu(env));
+ TaskState *ts = cs->opaque;
struct target_vm86plus_struct * target_v86;
if (!lock_user_struct(VERIFY_WRITE, target_v86, ts->target_v86, 0))
@@ -131,7 +132,8 @@ static inline void return_to_32bit(CPUX86State *env, int retval)
static inline int set_IF(CPUX86State *env)
{
- TaskState *ts = env->opaque;
+ CPUState *cs = CPU(x86_env_get_cpu(env));
+ TaskState *ts = cs->opaque;
ts->v86flags |= VIF_MASK;
if (ts->v86flags & VIP_MASK) {
@@ -143,7 +145,8 @@ static inline int set_IF(CPUX86State *env)
static inline void clear_IF(CPUX86State *env)
{
- TaskState *ts = env->opaque;
+ CPUState *cs = CPU(x86_env_get_cpu(env));
+ TaskState *ts = cs->opaque;
ts->v86flags &= ~VIF_MASK;
}
@@ -160,7 +163,8 @@ static inline void clear_AC(CPUX86State *env)
static inline int set_vflags_long(unsigned long eflags, CPUX86State *env)
{
- TaskState *ts = env->opaque;
+ CPUState *cs = CPU(x86_env_get_cpu(env));
+ TaskState *ts = cs->opaque;
set_flags(ts->v86flags, eflags, ts->v86mask);
set_flags(env->eflags, eflags, SAFE_MASK);
@@ -173,7 +177,8 @@ static inline int set_vflags_long(unsigned long eflags, CPUX86State *env)
static inline int set_vflags_short(unsigned short flags, CPUX86State *env)
{
- TaskState *ts = env->opaque;
+ CPUState *cs = CPU(x86_env_get_cpu(env));
+ TaskState *ts = cs->opaque;
set_flags(ts->v86flags, flags, ts->v86mask & 0xffff);
set_flags(env->eflags, flags, SAFE_MASK);
@@ -186,7 +191,8 @@ static inline int set_vflags_short(unsigned short flags, CPUX86State *env)
static inline unsigned int get_vflags(CPUX86State *env)
{
- TaskState *ts = env->opaque;
+ CPUState *cs = CPU(x86_env_get_cpu(env));
+ TaskState *ts = cs->opaque;
unsigned int flags;
flags = env->eflags & RETURN_MASK;
@@ -202,7 +208,8 @@ static inline unsigned int get_vflags(CPUX86State *env)
support TSS interrupt revectoring, so this code is always executed) */
static void do_int(CPUX86State *env, int intno)
{
- TaskState *ts = env->opaque;
+ CPUState *cs = CPU(x86_env_get_cpu(env));
+ TaskState *ts = cs->opaque;
uint32_t int_addr, segoffs, ssp;
unsigned int sp;
@@ -260,7 +267,8 @@ void handle_vm86_trap(CPUX86State *env, int trapno)
void handle_vm86_fault(CPUX86State *env)
{
- TaskState *ts = env->opaque;
+ CPUState *cs = CPU(x86_env_get_cpu(env));
+ TaskState *ts = cs->opaque;
uint32_t csp, ssp;
unsigned int ip, sp, newflags, newip, newcs, opcode, intno;
int data32, pref_done;
@@ -384,7 +392,8 @@ void handle_vm86_fault(CPUX86State *env)
int do_vm86(CPUX86State *env, long subfunction, abi_ulong vm86_addr)
{
- TaskState *ts = env->opaque;
+ CPUState *cs = CPU(x86_env_get_cpu(env));
+ TaskState *ts = cs->opaque;
struct target_vm86plus_struct * target_v86;
int ret;
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index ee469c4..ebb5235 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -127,7 +127,7 @@ static void arm_semi_cb(CPUState *cs, target_ulong ret, target_ulong err)
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
#ifdef CONFIG_USER_ONLY
- TaskState *ts = env->opaque;
+ TaskState *ts = cs->opaque;
#endif
if (ret == (target_ulong)-1) {
@@ -164,7 +164,7 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err)
cpu_memory_rw_debug(cs, env->regs[13]-64+32, (uint8_t *)&size, 4, 0);
env->regs[0] = be32_to_cpu(size);
#ifdef CONFIG_USER_ONLY
- ((TaskState *)env->opaque)->swi_errno = err;
+ ((TaskState *)cs->opaque)->swi_errno = err;
#else
syscall_err = err;
#endif
@@ -183,6 +183,7 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulong ret, target_ulong err)
uint32_t do_arm_semihosting(CPUARMState *env)
{
ARMCPU *cpu = arm_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
target_ulong args;
target_ulong arg0, arg1, arg2, arg3;
char * s;
@@ -190,7 +191,7 @@ uint32_t do_arm_semihosting(CPUARMState *env)
uint32_t ret;
uint32_t len;
#ifdef CONFIG_USER_ONLY
- TaskState *ts = env->opaque;
+ TaskState *ts = cs->opaque;
#else
CPUARMState *ts = env;
#endif
@@ -554,7 +555,7 @@ uint32_t do_arm_semihosting(CPUARMState *env)
exit(0);
default:
fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr);
- cpu_dump_state(CPU(cpu), stderr, fprintf, 0);
+ cpu_dump_state(cs, stderr, fprintf, 0);
abort();
}
}
diff --git a/target-m68k/m68k-semi.c b/target-m68k/m68k-semi.c
index 94c4983..2dea3ca 100644
--- a/target-m68k/m68k-semi.c
+++ b/target-m68k/m68k-semi.c
@@ -428,7 +428,8 @@ void do_m68k_semihosting(CPUM68KState *env, int nr)
case HOSTED_INIT_SIM:
#if defined(CONFIG_USER_ONLY)
{
- TaskState *ts = env->opaque;
+ CPUState *cs = CPU(m68k_env_get_cpu(env));
+ TaskState *ts = cs->opaque;
/* Allocate the heap using sbrk. */
if (!ts->heap_limit) {
abi_ulong ret;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 15/41] cpu: Move watchpoint fields from CPU_COMMON to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (13 preceding siblings ...)
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 14/41] cpu: Move opaque field from CPU_COMMON to CPUState Andreas Färber
@ 2013-09-04 9:04 ` Andreas Färber
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 16/41] cpu: Move breakpoints field " Andreas Färber
` (28 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:04 UTC (permalink / raw)
To: qemu-devel
Cc: Marcelo Tosatti, open list:X86, Gleb Natapov, Riku Voipio,
Max Filippov, Paolo Bonzini, Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cpu-exec.c | 5 +++--
exec.c | 33 ++++++++++++++++++++-------------
gdbstub.c | 8 ++++----
include/exec/cpu-defs.h | 10 ----------
include/qom/cpu.h | 10 ++++++++++
linux-user/main.c | 5 +++--
target-i386/cpu.h | 2 +-
target-i386/helper.c | 7 ++++---
target-i386/kvm.c | 8 ++++----
target-xtensa/cpu.h | 2 +-
target-xtensa/helper.c | 8 +++++---
11 files changed, 55 insertions(+), 43 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 0081eaf..209380d 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -183,10 +183,11 @@ void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
static void cpu_handle_debug_exception(CPUArchState *env)
{
+ CPUState *cpu = ENV_GET_CPU(env);
CPUWatchpoint *wp;
- if (!env->watchpoint_hit) {
- QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
+ if (!cpu->watchpoint_hit) {
+ QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
wp->flags &= ~BP_WATCHPOINT_HIT;
}
}
diff --git a/exec.c b/exec.c
index 93958c3..5b70bf8 100644
--- a/exec.c
+++ b/exec.c
@@ -379,7 +379,7 @@ void cpu_exec_init(CPUArchState *env)
cpu->cpu_index = cpu_index;
cpu->numa_node = 0;
QTAILQ_INIT(&env->breakpoints);
- QTAILQ_INIT(&env->watchpoints);
+ QTAILQ_INIT(&cpu->watchpoints);
#ifndef CONFIG_USER_ONLY
cpu->thread_id = qemu_get_thread_id();
#endif
@@ -432,6 +432,7 @@ int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len
int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
int flags, CPUWatchpoint **watchpoint)
{
+ CPUState *cpu = ENV_GET_CPU(env);
target_ulong len_mask = ~(len - 1);
CPUWatchpoint *wp;
@@ -449,10 +450,11 @@ int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len
wp->flags = flags;
/* keep all GDB-injected watchpoints in front */
- if (flags & BP_GDB)
- QTAILQ_INSERT_HEAD(&env->watchpoints, wp, entry);
- else
- QTAILQ_INSERT_TAIL(&env->watchpoints, wp, entry);
+ if (flags & BP_GDB) {
+ QTAILQ_INSERT_HEAD(&cpu->watchpoints, wp, entry);
+ } else {
+ QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
+ }
tlb_flush_page(env, addr);
@@ -465,10 +467,11 @@ int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len
int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len,
int flags)
{
+ CPUState *cpu = ENV_GET_CPU(env);
target_ulong len_mask = ~(len - 1);
CPUWatchpoint *wp;
- QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
+ QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
if (addr == wp->vaddr && len_mask == wp->len_mask
&& flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
cpu_watchpoint_remove_by_ref(env, wp);
@@ -481,7 +484,9 @@ int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len
/* Remove a specific watchpoint by reference. */
void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint)
{
- QTAILQ_REMOVE(&env->watchpoints, watchpoint, entry);
+ CPUState *cpu = ENV_GET_CPU(env);
+
+ QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
tlb_flush_page(env, watchpoint->vaddr);
@@ -491,9 +496,10 @@ void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint)
/* Remove all matching watchpoints. */
void cpu_watchpoint_remove_all(CPUArchState *env, int mask)
{
+ CPUState *cpu = ENV_GET_CPU(env);
CPUWatchpoint *wp, *next;
- QTAILQ_FOREACH_SAFE(wp, &env->watchpoints, entry, next) {
+ QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
if (wp->flags & mask)
cpu_watchpoint_remove_by_ref(env, wp);
}
@@ -677,6 +683,7 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env,
int prot,
target_ulong *address)
{
+ CPUState *cpu = ENV_GET_CPU(env);
hwaddr iotlb;
CPUWatchpoint *wp;
@@ -696,7 +703,7 @@ hwaddr memory_region_section_get_iotlb(CPUArchState *env,
/* Make accesses to pages with watchpoints go via the
watchpoint trap routines. */
- QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
+ QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
if (vaddr == (wp->vaddr & TARGET_PAGE_MASK)) {
/* Avoid trapping reads of pages with a write breakpoint. */
if ((prot & PAGE_WRITE) || (wp->flags & BP_MEM_READ)) {
@@ -1454,7 +1461,7 @@ static void check_watchpoint(int offset, int len_mask, int flags)
CPUWatchpoint *wp;
int cpu_flags;
- if (env->watchpoint_hit) {
+ if (cpu->watchpoint_hit) {
/* We re-entered the check after replacing the TB. Now raise
* the debug interrupt so that is will trigger after the
* current instruction. */
@@ -1462,12 +1469,12 @@ static void check_watchpoint(int offset, int len_mask, int flags)
return;
}
vaddr = (cpu->mem_io_vaddr & TARGET_PAGE_MASK) + offset;
- QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
+ QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
if ((vaddr == (wp->vaddr & len_mask) ||
(vaddr & wp->len_mask) == wp->vaddr) && (wp->flags & flags)) {
wp->flags |= BP_WATCHPOINT_HIT;
- if (!env->watchpoint_hit) {
- env->watchpoint_hit = wp;
+ if (!cpu->watchpoint_hit) {
+ cpu->watchpoint_hit = wp;
tb_check_watchpoint(env);
if (wp->flags & BP_STOP_BEFORE_ACCESS) {
cpu->exception_index = EXCP_DEBUG;
diff --git a/gdbstub.c b/gdbstub.c
index dac99b3..05b76e0 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1207,8 +1207,8 @@ static void gdb_vm_state_change(void *opaque, int running, RunState state)
}
switch (state) {
case RUN_STATE_DEBUG:
- if (env->watchpoint_hit) {
- switch (env->watchpoint_hit->flags & BP_MEM_ACCESS) {
+ if (cpu->watchpoint_hit) {
+ switch (cpu->watchpoint_hit->flags & BP_MEM_ACCESS) {
case BP_MEM_READ:
type = "r";
break;
@@ -1222,8 +1222,8 @@ static void gdb_vm_state_change(void *opaque, int running, RunState state)
snprintf(buf, sizeof(buf),
"T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";",
GDB_SIGNAL_TRAP, cpu_index(cpu), type,
- env->watchpoint_hit->vaddr);
- env->watchpoint_hit = NULL;
+ (target_ulong)cpu->watchpoint_hit->vaddr);
+ cpu->watchpoint_hit = NULL;
goto send_packet;
}
tb_flush(env);
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index be9569c..338b8cb 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -119,13 +119,6 @@ typedef struct CPUBreakpoint {
QTAILQ_ENTRY(CPUBreakpoint) entry;
} CPUBreakpoint;
-typedef struct CPUWatchpoint {
- target_ulong vaddr;
- target_ulong len_mask;
- int flags; /* BP_* */
- QTAILQ_ENTRY(CPUWatchpoint) entry;
-} CPUWatchpoint;
-
#define CPU_TEMP_BUF_NLONGS 128
#define CPU_COMMON \
/* soft mmu support */ \
@@ -134,8 +127,5 @@ typedef struct CPUWatchpoint {
/* from this point: preserved by CPU reset */ \
/* ice debug support */ \
QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \
- \
- QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
- CPUWatchpoint *watchpoint_hit; \
#endif
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 828c833..ae6602a 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -154,6 +154,13 @@ typedef struct icount_decr_u16 {
} icount_decr_u16;
#endif
+typedef struct CPUWatchpoint {
+ vaddr vaddr;
+ vaddr len_mask;
+ int flags; /* BP_* */
+ QTAILQ_ENTRY(CPUWatchpoint) entry;
+} CPUWatchpoint;
+
struct KVMState;
struct kvm_run;
@@ -231,6 +238,9 @@ struct CPUState {
int gdb_num_g_regs;
QTAILQ_ENTRY(CPUState) node;
+ QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;
+ CPUWatchpoint *watchpoint_hit;
+
void *opaque;
/* In order to avoid passing too many arguments to the MMIO helpers,
diff --git a/linux-user/main.c b/linux-user/main.c
index ac78024..c8723e7 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3191,6 +3191,7 @@ void init_task_state(TaskState *ts)
CPUArchState *cpu_copy(CPUArchState *env)
{
+ CPUState *cpu = ENV_GET_CPU(env);
CPUArchState *new_env = cpu_init(cpu_model);
#if defined(TARGET_HAS_ICE)
CPUBreakpoint *bp;
@@ -3206,12 +3207,12 @@ CPUArchState *cpu_copy(CPUArchState *env)
Note: Once we support ptrace with hw-debug register access, make sure
BP_CPU break/watchpoints are handled correctly on clone. */
QTAILQ_INIT(&env->breakpoints);
- QTAILQ_INIT(&env->watchpoints);
+ QTAILQ_INIT(&cpu->watchpoints);
#if defined(TARGET_HAS_ICE)
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
}
- QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
+ QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1,
wp->flags, NULL);
}
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 3620699..36e62b1 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -850,7 +850,7 @@ typedef struct CPUX86State {
target_ulong dr[8]; /* debug registers */
union {
CPUBreakpoint *cpu_breakpoint[4];
- CPUWatchpoint *cpu_watchpoint[4];
+ struct CPUWatchpoint *cpu_watchpoint[4];
}; /* break/watchpoints for dr[0..3] */
uint32_t smbase;
int old_exception; /* exception in flight */
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 864d9f8..2a5ffc2 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -1083,11 +1083,12 @@ bool check_hw_breakpoints(CPUX86State *env, bool force_dr6_update)
void breakpoint_handler(CPUX86State *env)
{
+ CPUState *cs = CPU(x86_env_get_cpu(env));
CPUBreakpoint *bp;
- if (env->watchpoint_hit) {
- if (env->watchpoint_hit->flags & BP_CPU) {
- env->watchpoint_hit = NULL;
+ if (cs->watchpoint_hit) {
+ if (cs->watchpoint_hit->flags & BP_CPU) {
+ cs->watchpoint_hit = NULL;
if (check_hw_breakpoints(env, false)) {
raise_exception(env, EXCP01_DB);
} else {
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 749aa09..64aa43b 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -2199,13 +2199,13 @@ static int kvm_handle_debug(X86CPU *cpu,
break;
case 0x1:
ret = EXCP_DEBUG;
- env->watchpoint_hit = &hw_watchpoint;
+ cs->watchpoint_hit = &hw_watchpoint;
hw_watchpoint.vaddr = hw_breakpoint[n].addr;
hw_watchpoint.flags = BP_MEM_WRITE;
break;
case 0x3:
ret = EXCP_DEBUG;
- env->watchpoint_hit = &hw_watchpoint;
+ cs->watchpoint_hit = &hw_watchpoint;
hw_watchpoint.vaddr = hw_breakpoint[n].addr;
hw_watchpoint.flags = BP_MEM_ACCESS;
break;
@@ -2213,11 +2213,11 @@ static int kvm_handle_debug(X86CPU *cpu,
}
}
}
- } else if (kvm_find_sw_breakpoint(CPU(cpu), arch_info->pc)) {
+ } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
ret = EXCP_DEBUG;
}
if (ret == 0) {
- cpu_synchronize_state(CPU(cpu));
+ cpu_synchronize_state(cs);
assert(env->exception_injected == -1);
/* pass to guest */
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 5d2a059..007a805 100644
--- a/target-xtensa/cpu.h
+++ b/target-xtensa/cpu.h
@@ -355,7 +355,7 @@ typedef struct CPUXtensaState {
int exception_taken;
/* Watchpoints for DBREAK registers */
- CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
+ struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
CPU_COMMON
} CPUXtensaState;
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index f55095e..c44cf71 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -81,11 +81,13 @@ static uint32_t check_hw_breakpoints(CPUXtensaState *env)
void xtensa_breakpoint_handler(CPUXtensaState *env)
{
- if (env->watchpoint_hit) {
- if (env->watchpoint_hit->flags & BP_CPU) {
+ CPUState *cs = CPU(xtensa_env_get_cpu(env));
+
+ if (cs->watchpoint_hit) {
+ if (cs->watchpoint_hit->flags & BP_CPU) {
uint32_t cause;
- env->watchpoint_hit = NULL;
+ cs->watchpoint_hit = NULL;
cause = check_hw_breakpoints(env);
if (cause) {
debug_exception_env(env, cause);
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 16/41] cpu: Move breakpoints field from CPU_COMMON to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (14 preceding siblings ...)
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 15/41] cpu: Move watchpoint fields " Andreas Färber
@ 2013-09-04 9:04 ` Andreas Färber
2013-09-04 12:48 ` Jia Liu
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 17/41] cpu: Move tlb_flush_{addr, mask} fields from CPU_COMMON_TLB " Andreas Färber
` (27 subsequent siblings)
43 siblings, 1 reply; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:04 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Anthony Green, Riku Voipio,
Alexander Graf, Blue Swirl, Max Filippov, Michael Walle,
open list:PowerPC, Paul Brook, Edgar E. Iglesias, Guan Xuetao,
Andreas Färber, Aurelien Jarno, Richard Henderson
Most targets were using offsetof(CPUFooState, breakpoints) to determine
how much of CPUFooState to clear on reset. Use the next field after
CPU_COMMON instead, if any, or sizeof(CPUFooState) otherwise.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
exec.c | 21 +++++++++++++--------
include/exec/cpu-defs.h | 10 ----------
include/qom/cpu.h | 9 +++++++++
linux-user/main.c | 4 ++--
target-alpha/translate.c | 4 ++--
target-arm/cpu.c | 2 +-
target-arm/translate.c | 4 ++--
target-cris/cpu.c | 2 +-
target-cris/cpu.h | 4 ++--
target-cris/translate.c | 5 +++--
target-i386/cpu.c | 2 +-
target-i386/cpu.h | 3 ++-
target-i386/helper.c | 3 ++-
target-i386/translate.c | 4 ++--
target-lm32/cpu.c | 2 +-
target-lm32/cpu.h | 1 +
target-lm32/translate.c | 5 +++--
target-m68k/cpu.c | 2 +-
target-m68k/cpu.h | 1 +
target-m68k/translate.c | 4 ++--
target-microblaze/cpu.c | 2 +-
target-microblaze/translate.c | 5 +++--
target-mips/cpu.c | 2 +-
target-mips/cpu.h | 1 +
target-mips/translate.c | 4 ++--
target-moxie/cpu.c | 2 +-
target-moxie/translate.c | 4 ++--
target-openrisc/cpu.c | 6 +++++-
target-openrisc/cpu.h | 1 +
target-openrisc/translate.c | 5 +++--
target-ppc/translate.c | 4 ++--
target-s390x/cpu.c | 4 ++--
target-s390x/translate.c | 4 ++--
target-sh4/cpu.c | 2 +-
target-sh4/cpu.h | 1 +
target-sh4/translate.c | 4 ++--
target-sparc/cpu.c | 2 +-
target-sparc/cpu.h | 1 +
target-sparc/translate.c | 4 ++--
target-unicore32/translate.c | 4 ++--
target-xtensa/translate.c | 5 +++--
41 files changed, 90 insertions(+), 69 deletions(-)
diff --git a/exec.c b/exec.c
index 5b70bf8..6ae5a21 100644
--- a/exec.c
+++ b/exec.c
@@ -378,7 +378,7 @@ void cpu_exec_init(CPUArchState *env)
}
cpu->cpu_index = cpu_index;
cpu->numa_node = 0;
- QTAILQ_INIT(&env->breakpoints);
+ QTAILQ_INIT(&cpu->breakpoints);
QTAILQ_INIT(&cpu->watchpoints);
#ifndef CONFIG_USER_ONLY
cpu->thread_id = qemu_get_thread_id();
@@ -511,6 +511,7 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
CPUBreakpoint **breakpoint)
{
#if defined(TARGET_HAS_ICE)
+ CPUState *cpu = ENV_GET_CPU(env);
CPUBreakpoint *bp;
bp = g_malloc(sizeof(*bp));
@@ -520,12 +521,12 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
/* keep all GDB-injected breakpoints in front */
if (flags & BP_GDB) {
- QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry);
+ QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
} else {
- QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry);
+ QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
}
- breakpoint_invalidate(ENV_GET_CPU(env), pc);
+ breakpoint_invalidate(cpu, pc);
if (breakpoint) {
*breakpoint = bp;
@@ -540,9 +541,10 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags)
{
#if defined(TARGET_HAS_ICE)
+ CPUState *cpu = ENV_GET_CPU(env);
CPUBreakpoint *bp;
- QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
if (bp->pc == pc && bp->flags == flags) {
cpu_breakpoint_remove_by_ref(env, bp);
return 0;
@@ -558,9 +560,11 @@ int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags)
void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint)
{
#if defined(TARGET_HAS_ICE)
- QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry);
+ CPUState *cpu = ENV_GET_CPU(env);
- breakpoint_invalidate(ENV_GET_CPU(env), breakpoint->pc);
+ QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
+
+ breakpoint_invalidate(cpu, breakpoint->pc);
g_free(breakpoint);
#endif
@@ -570,9 +574,10 @@ void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint)
void cpu_breakpoint_remove_all(CPUArchState *env, int mask)
{
#if defined(TARGET_HAS_ICE)
+ CPUState *cpu = ENV_GET_CPU(env);
CPUBreakpoint *bp, *next;
- QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) {
+ QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
if (bp->flags & mask)
cpu_breakpoint_remove_by_ref(env, bp);
}
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 338b8cb..d090594 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -113,19 +113,9 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
#endif
-typedef struct CPUBreakpoint {
- target_ulong pc;
- int flags; /* BP_* */
- QTAILQ_ENTRY(CPUBreakpoint) entry;
-} CPUBreakpoint;
-
#define CPU_TEMP_BUF_NLONGS 128
#define CPU_COMMON \
/* soft mmu support */ \
CPU_COMMON_TLB \
- \
- /* from this point: preserved by CPU reset */ \
- /* ice debug support */ \
- QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \
#endif
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index ae6602a..fc3d345 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -154,6 +154,12 @@ typedef struct icount_decr_u16 {
} icount_decr_u16;
#endif
+typedef struct CPUBreakpoint {
+ vaddr pc;
+ int flags; /* BP_* */
+ QTAILQ_ENTRY(CPUBreakpoint) entry;
+} CPUBreakpoint;
+
typedef struct CPUWatchpoint {
vaddr vaddr;
vaddr len_mask;
@@ -238,6 +244,9 @@ struct CPUState {
int gdb_num_g_regs;
QTAILQ_ENTRY(CPUState) node;
+ /* ice debug support */
+ QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;
+
QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;
CPUWatchpoint *watchpoint_hit;
diff --git a/linux-user/main.c b/linux-user/main.c
index c8723e7..77278c7 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3206,10 +3206,10 @@ CPUArchState *cpu_copy(CPUArchState *env)
/* Clone all break/watchpoints.
Note: Once we support ptrace with hw-debug register access, make sure
BP_CPU break/watchpoints are handled correctly on clone. */
- QTAILQ_INIT(&env->breakpoints);
+ QTAILQ_INIT(&cpu->breakpoints);
QTAILQ_INIT(&cpu->watchpoints);
#if defined(TARGET_HAS_ICE)
- QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
}
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 50b4339..7b2ae0d 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -3486,8 +3486,8 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
gen_tb_start();
do {
- if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
- QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == ctx.pc) {
gen_excp(&ctx, EXCP_DEBUG, 0);
break;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 4c6fe17..f9f6930 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -114,7 +114,7 @@ static void arm_cpu_reset(CPUState *s)
acc->parent_reset(s);
- memset(env, 0, offsetof(CPUARMState, breakpoints));
+ memset(env, 0, offsetof(CPUARMState, features));
g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 4f4a0a9..0eaec9f 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -10035,8 +10035,8 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
}
#endif
- if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
- QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == dc->pc) {
gen_exception_insn(dc, 0, EXCP_DEBUG);
/* Advance PC so that clearing the breakpoint will
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index 504d6a4..b229a10 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -69,7 +69,7 @@ static void cris_cpu_reset(CPUState *s)
ccc->parent_reset(s);
vr = env->pregs[PR_VR];
- memset(env, 0, offsetof(CPUCRISState, breakpoints));
+ memset(env, 0, offsetof(CPUCRISState, load_info));
env->pregs[PR_VR] = vr;
tlb_flush(env, 1);
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 9e9cb8c..df2a3f0 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -167,8 +167,8 @@ typedef struct CPUCRISState {
CPU_COMMON
- /* Members after CPU_COMMON are preserved across resets. */
- void *load_info;
+ /* Members from load_info on are preserved across resets. */
+ void *load_info;
} CPUCRISState;
#include "cpu-qom.h"
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 29e9f63..90a4394 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3110,10 +3110,11 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
static void check_breakpoint(CPUCRISState *env, DisasContext *dc)
{
+ CPUState *cs = CPU(cris_env_get_cpu(env));
CPUBreakpoint *bp;
- if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
- QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == dc->pc) {
cris_evaluate_flags(dc);
tcg_gen_movi_tl(env_pc, dc->pc);
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 89e3217..b8d0c15 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2328,7 +2328,7 @@ static void x86_cpu_reset(CPUState *s)
xcc->parent_reset(s);
- memset(env, 0, offsetof(CPUX86State, breakpoints));
+ memset(env, 0, offsetof(CPUX86State, pat));
tlb_flush(env, 1);
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 36e62b1..b9503d9 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -849,7 +849,7 @@ typedef struct CPUX86State {
target_ulong exception_next_eip;
target_ulong dr[8]; /* debug registers */
union {
- CPUBreakpoint *cpu_breakpoint[4];
+ struct CPUBreakpoint *cpu_breakpoint[4];
struct CPUWatchpoint *cpu_watchpoint[4];
}; /* break/watchpoints for dr[0..3] */
uint32_t smbase;
@@ -861,6 +861,7 @@ typedef struct CPUX86State {
CPU_COMMON
+ /* Fields from here on are preserved across CPU reset. */
uint64_t pat;
/* processor features (e.g. for CPUID insn) */
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 2a5ffc2..557c94f 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -1096,7 +1096,7 @@ void breakpoint_handler(CPUX86State *env)
}
}
} else {
- QTAILQ_FOREACH(bp, &env->breakpoints, entry)
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == env->eip) {
if (bp->flags & BP_CPU) {
check_hw_breakpoints(env, true);
@@ -1104,6 +1104,7 @@ void breakpoint_handler(CPUX86State *env)
}
break;
}
+ }
}
}
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 2e8e8d5..6e64551 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -8340,8 +8340,8 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
gen_tb_start();
for(;;) {
- if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
- QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == pc_ptr &&
!((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) {
gen_debug(dc, pc_ptr - dc->cs_base);
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
index 607e332..69bc6bb 100644
--- a/target-lm32/cpu.c
+++ b/target-lm32/cpu.c
@@ -54,7 +54,7 @@ static void lm32_cpu_reset(CPUState *s)
lcc->parent_reset(s);
/* reset cpu state */
- memset(env, 0, offsetof(CPULM32State, breakpoints));
+ memset(env, 0, offsetof(CPULM32State, eba));
tlb_flush(env, 1);
}
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index a94fd79..85c89e8 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -164,6 +164,7 @@ struct CPULM32State {
CPU_COMMON
+ /* Fields from here on are preserved across CPU reset. */
uint32_t eba; /* exception base address */
uint32_t deba; /* debug exception base address */
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 6ea0ecd..2e4951c 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -997,10 +997,11 @@ static inline void decode(DisasContext *dc, uint32_t ir)
static void check_breakpoint(CPULM32State *env, DisasContext *dc)
{
+ CPUState *cs = CPU(lm32_env_get_cpu(env));
CPUBreakpoint *bp;
- if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
- QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == dc->pc) {
tcg_gen_movi_tl(cpu_pc, dc->pc);
t_gen_raise_exception(dc, EXCP_DEBUG);
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index e46b647..b24120d 100644
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -69,7 +69,7 @@ static void m68k_cpu_reset(CPUState *s)
mcc->parent_reset(s);
- memset(env, 0, offsetof(CPUM68KState, breakpoints));
+ memset(env, 0, offsetof(CPUM68KState, features));
#if !defined(CONFIG_USER_ONLY)
env->sr = 0x2700;
#endif
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index b8ad269..9a49bfc 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -110,6 +110,7 @@ typedef struct CPUM68KState {
CPU_COMMON
+ /* Fields from here on are preserved across CPU reset. */
uint32_t features;
} CPUM68KState;
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index f3cdee0..c005e10 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -3016,8 +3016,8 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
do {
pc_offset = dc->pc - pc_start;
gen_throws_exception = NULL;
- if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
- QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == dc->pc) {
gen_exception(dc, dc->pc, EXCP_DEBUG);
dc->is_jmp = DISAS_JUMP;
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 8b248f4..d724b6e 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -73,7 +73,7 @@ static void mb_cpu_reset(CPUState *s)
mcc->parent_reset(s);
- memset(env, 0, offsetof(CPUMBState, breakpoints));
+ memset(env, 0, sizeof(CPUMBState));
env->res_addr = RES_ADDR_NONE;
tlb_flush(env, 1);
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index f4dbe11..31eef0f 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1724,10 +1724,11 @@ static inline void decode(DisasContext *dc, uint32_t ir)
static void check_breakpoint(CPUMBState *env, DisasContext *dc)
{
+ CPUState *cs = CPU(mb_env_get_cpu(env));
CPUBreakpoint *bp;
- if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
- QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == dc->pc) {
t_gen_raise_exception(dc, EXCP_DEBUG);
dc->is_jmp = DISAS_UPDATE;
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index 2fd5591..8f26d11 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -101,7 +101,7 @@ static void mips_cpu_reset(CPUState *s)
mcc->parent_reset(s);
- memset(env, 0, offsetof(CPUMIPSState, breakpoints));
+ memset(env, 0, offsetof(CPUMIPSState, mvp));
tlb_flush(env, 1);
cpu_state_reset(env);
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index b71a711..5320a05 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -469,6 +469,7 @@ struct CPUMIPSState {
CPU_COMMON
+ /* Fields from here on are preserved across CPU reset. */
CPUMIPSMVPContext *mvp;
#if !defined(CONFIG_USER_ONLY)
CPUMIPSTLBContext *tlb;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 453918d..f2e6625 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -15601,8 +15601,8 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
gen_tb_start();
while (ctx.bstate == BS_NONE) {
- if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
- QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == ctx.pc) {
save_cpu_state(&ctx, 1);
ctx.bstate = BS_BRANCH;
diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
index ab9d2cc..f7d1e6c 100644
--- a/target-moxie/cpu.c
+++ b/target-moxie/cpu.c
@@ -52,7 +52,7 @@ static void moxie_cpu_reset(CPUState *s)
mcc->parent_reset(s);
- memset(env, 0, offsetof(CPUMoxieState, breakpoints));
+ memset(env, 0, sizeof(CPUMoxieState));
env->pc = 0x1000;
tlb_flush(env, 1);
diff --git a/target-moxie/translate.c b/target-moxie/translate.c
index a93196f..63f889f 100644
--- a/target-moxie/translate.c
+++ b/target-moxie/translate.c
@@ -845,8 +845,8 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
gen_tb_start();
do {
- if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
- QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (ctx.pc == bp->pc) {
tcg_gen_movi_i32(cpu_pc, ctx.pc);
gen_helper_debug(cpu_env);
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index b7104e3..3eae4e9 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -62,7 +62,11 @@ static void openrisc_cpu_reset(CPUState *s)
occ->parent_reset(s);
- memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints));
+#ifndef CONFIG_USER_ONLY
+ memset(&cpu->env, 0, offsetof(CPUOpenRISCState, tlb));
+#else
+ memset(&cpu->env, 0, offsetof(CPUOpenRISCState, irq));
+#endif
tlb_flush(&cpu->env, 1);
/*tb_flush(&cpu->env); FIXME: Do we need it? */
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 8745072..441a0ef 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -304,6 +304,7 @@ typedef struct CPUOpenRISCState {
CPU_COMMON
+ /* Fields from here on are preserved across CPU reset. */
#ifndef CONFIG_USER_ONLY
CPUOpenRISCTLBContext * tlb;
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index ea242da..a0a633f 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -1645,10 +1645,11 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
static void check_breakpoint(OpenRISCCPU *cpu, DisasContext *dc)
{
+ CPUState *cs = CPU(cpu);
CPUBreakpoint *bp;
- if (unlikely(!QTAILQ_EMPTY(&cpu->env.breakpoints))) {
- QTAILQ_FOREACH(bp, &cpu->env.breakpoints, entry) {
+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == dc->pc) {
tcg_gen_movi_tl(cpu_pc, dc->pc);
gen_exception(dc, EXCP_DEBUG);
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 2da7bc7..ec12629 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9787,8 +9787,8 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
/* Set env in case of segfault during code fetch */
while (ctx.exception == POWERPC_EXCP_NONE
&& tcg_ctx.gen_opc_ptr < gen_opc_end) {
- if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
- QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == ctx.nip) {
gen_debug_exception(ctxp);
break;
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index ad0d5bc..d9b8470 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -131,7 +131,7 @@ static void s390_cpu_initial_reset(CPUState *s)
s390_cpu_reset(s);
/* initial reset does not touch regs,fregs and aregs */
- memset(&env->fpc, 0, offsetof(CPUS390XState, breakpoints) -
+ memset(&env->fpc, 0, offsetof(CPUS390XState, cpu_num) -
offsetof(CPUS390XState, fpc));
/* architectured initial values for CR 0 and 14 */
@@ -150,7 +150,7 @@ static void s390_cpu_full_reset(CPUState *s)
scc->parent_reset(s);
- memset(env, 0, offsetof(CPUS390XState, breakpoints));
+ memset(env, 0, offsetof(CPUS390XState, cpu_num));
/* architectured initial values for CR 0 and 14 */
env->cregs[0] = CR0_RESET;
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index afe90eb..d230f2c 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -4799,8 +4799,8 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu,
}
status = NO_EXIT;
- if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
- QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == dc.pc) {
status = EXIT_PC_STALE;
do_debug = true;
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index 1f1b8fd..fb176bf 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -76,7 +76,7 @@ static void superh_cpu_reset(CPUState *s)
scc->parent_reset(s);
- memset(env, 0, offsetof(CPUSH4State, breakpoints));
+ memset(env, 0, offsetof(CPUSH4State, id));
tlb_flush(env, 1);
env->pc = 0xA0000000;
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 8abd0cc..1df0842 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -178,6 +178,7 @@ typedef struct CPUSH4State {
CPU_COMMON
+ /* Fields from here on are preserved over CPU reset. */
int id; /* CPU model */
void *intc_handle;
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index c06b29f..3fe53b8 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1880,8 +1880,8 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb,
max_insns = CF_COUNT_MASK;
gen_tb_start();
while (ctx.bstate == BS_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end) {
- if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
- QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (ctx.pc == bp->pc) {
/* We have hit a breakpoint - make sure PC is up-to-date */
tcg_gen_movi_i32(cpu_pc, ctx.pc);
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index 9443713..6c1ff68 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -32,7 +32,7 @@ static void sparc_cpu_reset(CPUState *s)
scc->parent_reset(s);
- memset(env, 0, offsetof(CPUSPARCState, breakpoints));
+ memset(env, 0, offsetof(CPUSPARCState, version));
tlb_flush(env, 1);
env->cwp = 0;
#ifndef TARGET_SPARC64
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index cfa1e0d..69c6154 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -421,6 +421,7 @@ struct CPUSPARCState {
CPU_COMMON
+ /* Fields from here on are preserved across CPU reset. */
target_ulong version;
uint32_t nwindows;
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 73f8b9c..bc52c85 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -5254,8 +5254,8 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
max_insns = CF_COUNT_MASK;
gen_tb_start();
do {
- if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
- QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == dc->pc) {
if (dc->pc != pc_start)
save_state(dc);
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index 1246895..b4bee99 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -1925,8 +1925,8 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
gen_tb_start();
do {
- if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
- QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == dc->pc) {
gen_set_pc_im(dc->pc);
gen_exception(EXCP_DEBUG);
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 24343bd..55d4448 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -2871,10 +2871,11 @@ invalid_opcode:
static void check_breakpoint(CPUXtensaState *env, DisasContext *dc)
{
+ CPUState *cs = CPU(xtensa_env_get_cpu(env));
CPUBreakpoint *bp;
- if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
- QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
if (bp->pc == dc->pc) {
tcg_gen_movi_i32(cpu_pc, dc->pc);
gen_exception(dc, EXCP_DEBUG);
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 16/41] cpu: Move breakpoints field from CPU_COMMON to CPUState
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 16/41] cpu: Move breakpoints field " Andreas Färber
@ 2013-09-04 12:48 ` Jia Liu
0 siblings, 0 replies; 68+ messages in thread
From: Jia Liu @ 2013-09-04 12:48 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Anthony Green, Riku Voipio, qemu-devel@nongnu.org,
Alexander Graf, Blue Swirl, Max Filippov, Michael Walle,
open list:PowerPC, Paul Brook, Edgar E. Iglesias, Guan Xuetao,
Aurelien Jarno, Richard Henderson
On Wed, Sep 4, 2013 at 5:04 PM, Andreas Färber <afaerber@suse.de> wrote:
> Most targets were using offsetof(CPUFooState, breakpoints) to determine
> how much of CPUFooState to clear on reset. Use the next field after
> CPU_COMMON instead, if any, or sizeof(CPUFooState) otherwise.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
> exec.c | 21 +++++++++++++--------
> include/exec/cpu-defs.h | 10 ----------
> include/qom/cpu.h | 9 +++++++++
> linux-user/main.c | 4 ++--
> target-alpha/translate.c | 4 ++--
> target-arm/cpu.c | 2 +-
> target-arm/translate.c | 4 ++--
> target-cris/cpu.c | 2 +-
> target-cris/cpu.h | 4 ++--
> target-cris/translate.c | 5 +++--
> target-i386/cpu.c | 2 +-
> target-i386/cpu.h | 3 ++-
> target-i386/helper.c | 3 ++-
> target-i386/translate.c | 4 ++--
> target-lm32/cpu.c | 2 +-
> target-lm32/cpu.h | 1 +
> target-lm32/translate.c | 5 +++--
> target-m68k/cpu.c | 2 +-
> target-m68k/cpu.h | 1 +
> target-m68k/translate.c | 4 ++--
> target-microblaze/cpu.c | 2 +-
> target-microblaze/translate.c | 5 +++--
> target-mips/cpu.c | 2 +-
> target-mips/cpu.h | 1 +
> target-mips/translate.c | 4 ++--
> target-moxie/cpu.c | 2 +-
> target-moxie/translate.c | 4 ++--
> target-openrisc/cpu.c | 6 +++++-
> target-openrisc/cpu.h | 1 +
> target-openrisc/translate.c | 5 +++--
> target-ppc/translate.c | 4 ++--
> target-s390x/cpu.c | 4 ++--
> target-s390x/translate.c | 4 ++--
> target-sh4/cpu.c | 2 +-
> target-sh4/cpu.h | 1 +
> target-sh4/translate.c | 4 ++--
> target-sparc/cpu.c | 2 +-
> target-sparc/cpu.h | 1 +
> target-sparc/translate.c | 4 ++--
> target-unicore32/translate.c | 4 ++--
> target-xtensa/translate.c | 5 +++--
> 41 files changed, 90 insertions(+), 69 deletions(-)
>
> diff --git a/exec.c b/exec.c
> index 5b70bf8..6ae5a21 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -378,7 +378,7 @@ void cpu_exec_init(CPUArchState *env)
> }
> cpu->cpu_index = cpu_index;
> cpu->numa_node = 0;
> - QTAILQ_INIT(&env->breakpoints);
> + QTAILQ_INIT(&cpu->breakpoints);
> QTAILQ_INIT(&cpu->watchpoints);
> #ifndef CONFIG_USER_ONLY
> cpu->thread_id = qemu_get_thread_id();
> @@ -511,6 +511,7 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
> CPUBreakpoint **breakpoint)
> {
> #if defined(TARGET_HAS_ICE)
> + CPUState *cpu = ENV_GET_CPU(env);
> CPUBreakpoint *bp;
>
> bp = g_malloc(sizeof(*bp));
> @@ -520,12 +521,12 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
>
> /* keep all GDB-injected breakpoints in front */
> if (flags & BP_GDB) {
> - QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry);
> + QTAILQ_INSERT_HEAD(&cpu->breakpoints, bp, entry);
> } else {
> - QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry);
> + QTAILQ_INSERT_TAIL(&cpu->breakpoints, bp, entry);
> }
>
> - breakpoint_invalidate(ENV_GET_CPU(env), pc);
> + breakpoint_invalidate(cpu, pc);
>
> if (breakpoint) {
> *breakpoint = bp;
> @@ -540,9 +541,10 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
> int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags)
> {
> #if defined(TARGET_HAS_ICE)
> + CPUState *cpu = ENV_GET_CPU(env);
> CPUBreakpoint *bp;
>
> - QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
> if (bp->pc == pc && bp->flags == flags) {
> cpu_breakpoint_remove_by_ref(env, bp);
> return 0;
> @@ -558,9 +560,11 @@ int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags)
> void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint)
> {
> #if defined(TARGET_HAS_ICE)
> - QTAILQ_REMOVE(&env->breakpoints, breakpoint, entry);
> + CPUState *cpu = ENV_GET_CPU(env);
>
> - breakpoint_invalidate(ENV_GET_CPU(env), breakpoint->pc);
> + QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
> +
> + breakpoint_invalidate(cpu, breakpoint->pc);
>
> g_free(breakpoint);
> #endif
> @@ -570,9 +574,10 @@ void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint)
> void cpu_breakpoint_remove_all(CPUArchState *env, int mask)
> {
> #if defined(TARGET_HAS_ICE)
> + CPUState *cpu = ENV_GET_CPU(env);
> CPUBreakpoint *bp, *next;
>
> - QTAILQ_FOREACH_SAFE(bp, &env->breakpoints, entry, next) {
> + QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
> if (bp->flags & mask)
> cpu_breakpoint_remove_by_ref(env, bp);
> }
> diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
> index 338b8cb..d090594 100644
> --- a/include/exec/cpu-defs.h
> +++ b/include/exec/cpu-defs.h
> @@ -113,19 +113,9 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
> #endif
>
>
> -typedef struct CPUBreakpoint {
> - target_ulong pc;
> - int flags; /* BP_* */
> - QTAILQ_ENTRY(CPUBreakpoint) entry;
> -} CPUBreakpoint;
> -
> #define CPU_TEMP_BUF_NLONGS 128
> #define CPU_COMMON \
> /* soft mmu support */ \
> CPU_COMMON_TLB \
> - \
> - /* from this point: preserved by CPU reset */ \
> - /* ice debug support */ \
> - QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \
>
> #endif
> diff --git a/include/qom/cpu.h b/include/qom/cpu.h
> index ae6602a..fc3d345 100644
> --- a/include/qom/cpu.h
> +++ b/include/qom/cpu.h
> @@ -154,6 +154,12 @@ typedef struct icount_decr_u16 {
> } icount_decr_u16;
> #endif
>
> +typedef struct CPUBreakpoint {
> + vaddr pc;
> + int flags; /* BP_* */
> + QTAILQ_ENTRY(CPUBreakpoint) entry;
> +} CPUBreakpoint;
> +
> typedef struct CPUWatchpoint {
> vaddr vaddr;
> vaddr len_mask;
> @@ -238,6 +244,9 @@ struct CPUState {
> int gdb_num_g_regs;
> QTAILQ_ENTRY(CPUState) node;
>
> + /* ice debug support */
> + QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;
> +
> QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;
> CPUWatchpoint *watchpoint_hit;
>
> diff --git a/linux-user/main.c b/linux-user/main.c
> index c8723e7..77278c7 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -3206,10 +3206,10 @@ CPUArchState *cpu_copy(CPUArchState *env)
> /* Clone all break/watchpoints.
> Note: Once we support ptrace with hw-debug register access, make sure
> BP_CPU break/watchpoints are handled correctly on clone. */
> - QTAILQ_INIT(&env->breakpoints);
> + QTAILQ_INIT(&cpu->breakpoints);
> QTAILQ_INIT(&cpu->watchpoints);
> #if defined(TARGET_HAS_ICE)
> - QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> + QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
> cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
> }
> QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
> diff --git a/target-alpha/translate.c b/target-alpha/translate.c
> index 50b4339..7b2ae0d 100644
> --- a/target-alpha/translate.c
> +++ b/target-alpha/translate.c
> @@ -3486,8 +3486,8 @@ static inline void gen_intermediate_code_internal(AlphaCPU *cpu,
>
> gen_tb_start();
> do {
> - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
> - QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
> + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> if (bp->pc == ctx.pc) {
> gen_excp(&ctx, EXCP_DEBUG, 0);
> break;
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 4c6fe17..f9f6930 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -114,7 +114,7 @@ static void arm_cpu_reset(CPUState *s)
>
> acc->parent_reset(s);
>
> - memset(env, 0, offsetof(CPUARMState, breakpoints));
> + memset(env, 0, offsetof(CPUARMState, features));
> g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
> env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
> env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 4f4a0a9..0eaec9f 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -10035,8 +10035,8 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
> }
> #endif
>
> - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
> - QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
> + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> if (bp->pc == dc->pc) {
> gen_exception_insn(dc, 0, EXCP_DEBUG);
> /* Advance PC so that clearing the breakpoint will
> diff --git a/target-cris/cpu.c b/target-cris/cpu.c
> index 504d6a4..b229a10 100644
> --- a/target-cris/cpu.c
> +++ b/target-cris/cpu.c
> @@ -69,7 +69,7 @@ static void cris_cpu_reset(CPUState *s)
> ccc->parent_reset(s);
>
> vr = env->pregs[PR_VR];
> - memset(env, 0, offsetof(CPUCRISState, breakpoints));
> + memset(env, 0, offsetof(CPUCRISState, load_info));
> env->pregs[PR_VR] = vr;
> tlb_flush(env, 1);
>
> diff --git a/target-cris/cpu.h b/target-cris/cpu.h
> index 9e9cb8c..df2a3f0 100644
> --- a/target-cris/cpu.h
> +++ b/target-cris/cpu.h
> @@ -167,8 +167,8 @@ typedef struct CPUCRISState {
>
> CPU_COMMON
>
> - /* Members after CPU_COMMON are preserved across resets. */
> - void *load_info;
> + /* Members from load_info on are preserved across resets. */
> + void *load_info;
> } CPUCRISState;
>
> #include "cpu-qom.h"
> diff --git a/target-cris/translate.c b/target-cris/translate.c
> index 29e9f63..90a4394 100644
> --- a/target-cris/translate.c
> +++ b/target-cris/translate.c
> @@ -3110,10 +3110,11 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
>
> static void check_breakpoint(CPUCRISState *env, DisasContext *dc)
> {
> + CPUState *cs = CPU(cris_env_get_cpu(env));
> CPUBreakpoint *bp;
>
> - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
> - QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
> + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> if (bp->pc == dc->pc) {
> cris_evaluate_flags(dc);
> tcg_gen_movi_tl(env_pc, dc->pc);
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 89e3217..b8d0c15 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -2328,7 +2328,7 @@ static void x86_cpu_reset(CPUState *s)
> xcc->parent_reset(s);
>
>
> - memset(env, 0, offsetof(CPUX86State, breakpoints));
> + memset(env, 0, offsetof(CPUX86State, pat));
>
> tlb_flush(env, 1);
>
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index 36e62b1..b9503d9 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -849,7 +849,7 @@ typedef struct CPUX86State {
> target_ulong exception_next_eip;
> target_ulong dr[8]; /* debug registers */
> union {
> - CPUBreakpoint *cpu_breakpoint[4];
> + struct CPUBreakpoint *cpu_breakpoint[4];
> struct CPUWatchpoint *cpu_watchpoint[4];
> }; /* break/watchpoints for dr[0..3] */
> uint32_t smbase;
> @@ -861,6 +861,7 @@ typedef struct CPUX86State {
>
> CPU_COMMON
>
> + /* Fields from here on are preserved across CPU reset. */
> uint64_t pat;
>
> /* processor features (e.g. for CPUID insn) */
> diff --git a/target-i386/helper.c b/target-i386/helper.c
> index 2a5ffc2..557c94f 100644
> --- a/target-i386/helper.c
> +++ b/target-i386/helper.c
> @@ -1096,7 +1096,7 @@ void breakpoint_handler(CPUX86State *env)
> }
> }
> } else {
> - QTAILQ_FOREACH(bp, &env->breakpoints, entry)
> + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> if (bp->pc == env->eip) {
> if (bp->flags & BP_CPU) {
> check_hw_breakpoints(env, true);
> @@ -1104,6 +1104,7 @@ void breakpoint_handler(CPUX86State *env)
> }
> break;
> }
> + }
> }
> }
>
> diff --git a/target-i386/translate.c b/target-i386/translate.c
> index 2e8e8d5..6e64551 100644
> --- a/target-i386/translate.c
> +++ b/target-i386/translate.c
> @@ -8340,8 +8340,8 @@ static inline void gen_intermediate_code_internal(X86CPU *cpu,
>
> gen_tb_start();
> for(;;) {
> - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
> - QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
> + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> if (bp->pc == pc_ptr &&
> !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) {
> gen_debug(dc, pc_ptr - dc->cs_base);
> diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
> index 607e332..69bc6bb 100644
> --- a/target-lm32/cpu.c
> +++ b/target-lm32/cpu.c
> @@ -54,7 +54,7 @@ static void lm32_cpu_reset(CPUState *s)
> lcc->parent_reset(s);
>
> /* reset cpu state */
> - memset(env, 0, offsetof(CPULM32State, breakpoints));
> + memset(env, 0, offsetof(CPULM32State, eba));
>
> tlb_flush(env, 1);
> }
> diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
> index a94fd79..85c89e8 100644
> --- a/target-lm32/cpu.h
> +++ b/target-lm32/cpu.h
> @@ -164,6 +164,7 @@ struct CPULM32State {
>
> CPU_COMMON
>
> + /* Fields from here on are preserved across CPU reset. */
> uint32_t eba; /* exception base address */
> uint32_t deba; /* debug exception base address */
>
> diff --git a/target-lm32/translate.c b/target-lm32/translate.c
> index 6ea0ecd..2e4951c 100644
> --- a/target-lm32/translate.c
> +++ b/target-lm32/translate.c
> @@ -997,10 +997,11 @@ static inline void decode(DisasContext *dc, uint32_t ir)
>
> static void check_breakpoint(CPULM32State *env, DisasContext *dc)
> {
> + CPUState *cs = CPU(lm32_env_get_cpu(env));
> CPUBreakpoint *bp;
>
> - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
> - QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
> + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> if (bp->pc == dc->pc) {
> tcg_gen_movi_tl(cpu_pc, dc->pc);
> t_gen_raise_exception(dc, EXCP_DEBUG);
> diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
> index e46b647..b24120d 100644
> --- a/target-m68k/cpu.c
> +++ b/target-m68k/cpu.c
> @@ -69,7 +69,7 @@ static void m68k_cpu_reset(CPUState *s)
>
> mcc->parent_reset(s);
>
> - memset(env, 0, offsetof(CPUM68KState, breakpoints));
> + memset(env, 0, offsetof(CPUM68KState, features));
> #if !defined(CONFIG_USER_ONLY)
> env->sr = 0x2700;
> #endif
> diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
> index b8ad269..9a49bfc 100644
> --- a/target-m68k/cpu.h
> +++ b/target-m68k/cpu.h
> @@ -110,6 +110,7 @@ typedef struct CPUM68KState {
>
> CPU_COMMON
>
> + /* Fields from here on are preserved across CPU reset. */
> uint32_t features;
> } CPUM68KState;
>
> diff --git a/target-m68k/translate.c b/target-m68k/translate.c
> index f3cdee0..c005e10 100644
> --- a/target-m68k/translate.c
> +++ b/target-m68k/translate.c
> @@ -3016,8 +3016,8 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
> do {
> pc_offset = dc->pc - pc_start;
> gen_throws_exception = NULL;
> - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
> - QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
> + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> if (bp->pc == dc->pc) {
> gen_exception(dc, dc->pc, EXCP_DEBUG);
> dc->is_jmp = DISAS_JUMP;
> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
> index 8b248f4..d724b6e 100644
> --- a/target-microblaze/cpu.c
> +++ b/target-microblaze/cpu.c
> @@ -73,7 +73,7 @@ static void mb_cpu_reset(CPUState *s)
>
> mcc->parent_reset(s);
>
> - memset(env, 0, offsetof(CPUMBState, breakpoints));
> + memset(env, 0, sizeof(CPUMBState));
> env->res_addr = RES_ADDR_NONE;
> tlb_flush(env, 1);
>
> diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
> index f4dbe11..31eef0f 100644
> --- a/target-microblaze/translate.c
> +++ b/target-microblaze/translate.c
> @@ -1724,10 +1724,11 @@ static inline void decode(DisasContext *dc, uint32_t ir)
>
> static void check_breakpoint(CPUMBState *env, DisasContext *dc)
> {
> + CPUState *cs = CPU(mb_env_get_cpu(env));
> CPUBreakpoint *bp;
>
> - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
> - QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
> + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> if (bp->pc == dc->pc) {
> t_gen_raise_exception(dc, EXCP_DEBUG);
> dc->is_jmp = DISAS_UPDATE;
> diff --git a/target-mips/cpu.c b/target-mips/cpu.c
> index 2fd5591..8f26d11 100644
> --- a/target-mips/cpu.c
> +++ b/target-mips/cpu.c
> @@ -101,7 +101,7 @@ static void mips_cpu_reset(CPUState *s)
>
> mcc->parent_reset(s);
>
> - memset(env, 0, offsetof(CPUMIPSState, breakpoints));
> + memset(env, 0, offsetof(CPUMIPSState, mvp));
> tlb_flush(env, 1);
>
> cpu_state_reset(env);
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index b71a711..5320a05 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -469,6 +469,7 @@ struct CPUMIPSState {
>
> CPU_COMMON
>
> + /* Fields from here on are preserved across CPU reset. */
> CPUMIPSMVPContext *mvp;
> #if !defined(CONFIG_USER_ONLY)
> CPUMIPSTLBContext *tlb;
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 453918d..f2e6625 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -15601,8 +15601,8 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb,
> LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
> gen_tb_start();
> while (ctx.bstate == BS_NONE) {
> - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
> - QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
> + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> if (bp->pc == ctx.pc) {
> save_cpu_state(&ctx, 1);
> ctx.bstate = BS_BRANCH;
> diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
> index ab9d2cc..f7d1e6c 100644
> --- a/target-moxie/cpu.c
> +++ b/target-moxie/cpu.c
> @@ -52,7 +52,7 @@ static void moxie_cpu_reset(CPUState *s)
>
> mcc->parent_reset(s);
>
> - memset(env, 0, offsetof(CPUMoxieState, breakpoints));
> + memset(env, 0, sizeof(CPUMoxieState));
> env->pc = 0x1000;
>
> tlb_flush(env, 1);
> diff --git a/target-moxie/translate.c b/target-moxie/translate.c
> index a93196f..63f889f 100644
> --- a/target-moxie/translate.c
> +++ b/target-moxie/translate.c
> @@ -845,8 +845,8 @@ gen_intermediate_code_internal(MoxieCPU *cpu, TranslationBlock *tb,
>
> gen_tb_start();
> do {
> - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
> - QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
> + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> if (ctx.pc == bp->pc) {
> tcg_gen_movi_i32(cpu_pc, ctx.pc);
> gen_helper_debug(cpu_env);
> diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
> index b7104e3..3eae4e9 100644
> --- a/target-openrisc/cpu.c
> +++ b/target-openrisc/cpu.c
> @@ -62,7 +62,11 @@ static void openrisc_cpu_reset(CPUState *s)
>
> occ->parent_reset(s);
>
> - memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints));
> +#ifndef CONFIG_USER_ONLY
> + memset(&cpu->env, 0, offsetof(CPUOpenRISCState, tlb));
> +#else
> + memset(&cpu->env, 0, offsetof(CPUOpenRISCState, irq));
> +#endif
>
> tlb_flush(&cpu->env, 1);
> /*tb_flush(&cpu->env); FIXME: Do we need it? */
> diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
> index 8745072..441a0ef 100644
> --- a/target-openrisc/cpu.h
> +++ b/target-openrisc/cpu.h
> @@ -304,6 +304,7 @@ typedef struct CPUOpenRISCState {
>
> CPU_COMMON
>
> + /* Fields from here on are preserved across CPU reset. */
> #ifndef CONFIG_USER_ONLY
> CPUOpenRISCTLBContext * tlb;
>
> diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
> index ea242da..a0a633f 100644
> --- a/target-openrisc/translate.c
> +++ b/target-openrisc/translate.c
> @@ -1645,10 +1645,11 @@ static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
>
> static void check_breakpoint(OpenRISCCPU *cpu, DisasContext *dc)
> {
> + CPUState *cs = CPU(cpu);
> CPUBreakpoint *bp;
>
> - if (unlikely(!QTAILQ_EMPTY(&cpu->env.breakpoints))) {
> - QTAILQ_FOREACH(bp, &cpu->env.breakpoints, entry) {
> + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
> + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> if (bp->pc == dc->pc) {
> tcg_gen_movi_tl(cpu_pc, dc->pc);
> gen_exception(dc, EXCP_DEBUG);
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 2da7bc7..ec12629 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -9787,8 +9787,8 @@ static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
> /* Set env in case of segfault during code fetch */
> while (ctx.exception == POWERPC_EXCP_NONE
> && tcg_ctx.gen_opc_ptr < gen_opc_end) {
> - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
> - QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
> + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> if (bp->pc == ctx.nip) {
> gen_debug_exception(ctxp);
> break;
> diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
> index ad0d5bc..d9b8470 100644
> --- a/target-s390x/cpu.c
> +++ b/target-s390x/cpu.c
> @@ -131,7 +131,7 @@ static void s390_cpu_initial_reset(CPUState *s)
>
> s390_cpu_reset(s);
> /* initial reset does not touch regs,fregs and aregs */
> - memset(&env->fpc, 0, offsetof(CPUS390XState, breakpoints) -
> + memset(&env->fpc, 0, offsetof(CPUS390XState, cpu_num) -
> offsetof(CPUS390XState, fpc));
>
> /* architectured initial values for CR 0 and 14 */
> @@ -150,7 +150,7 @@ static void s390_cpu_full_reset(CPUState *s)
>
> scc->parent_reset(s);
>
> - memset(env, 0, offsetof(CPUS390XState, breakpoints));
> + memset(env, 0, offsetof(CPUS390XState, cpu_num));
>
> /* architectured initial values for CR 0 and 14 */
> env->cregs[0] = CR0_RESET;
> diff --git a/target-s390x/translate.c b/target-s390x/translate.c
> index afe90eb..d230f2c 100644
> --- a/target-s390x/translate.c
> +++ b/target-s390x/translate.c
> @@ -4799,8 +4799,8 @@ static inline void gen_intermediate_code_internal(S390CPU *cpu,
> }
>
> status = NO_EXIT;
> - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
> - QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
> + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> if (bp->pc == dc.pc) {
> status = EXIT_PC_STALE;
> do_debug = true;
> diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
> index 1f1b8fd..fb176bf 100644
> --- a/target-sh4/cpu.c
> +++ b/target-sh4/cpu.c
> @@ -76,7 +76,7 @@ static void superh_cpu_reset(CPUState *s)
>
> scc->parent_reset(s);
>
> - memset(env, 0, offsetof(CPUSH4State, breakpoints));
> + memset(env, 0, offsetof(CPUSH4State, id));
> tlb_flush(env, 1);
>
> env->pc = 0xA0000000;
> diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
> index 8abd0cc..1df0842 100644
> --- a/target-sh4/cpu.h
> +++ b/target-sh4/cpu.h
> @@ -178,6 +178,7 @@ typedef struct CPUSH4State {
>
> CPU_COMMON
>
> + /* Fields from here on are preserved over CPU reset. */
> int id; /* CPU model */
>
> void *intc_handle;
> diff --git a/target-sh4/translate.c b/target-sh4/translate.c
> index c06b29f..3fe53b8 100644
> --- a/target-sh4/translate.c
> +++ b/target-sh4/translate.c
> @@ -1880,8 +1880,8 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb,
> max_insns = CF_COUNT_MASK;
> gen_tb_start();
> while (ctx.bstate == BS_NONE && tcg_ctx.gen_opc_ptr < gen_opc_end) {
> - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
> - QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
> + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> if (ctx.pc == bp->pc) {
> /* We have hit a breakpoint - make sure PC is up-to-date */
> tcg_gen_movi_i32(cpu_pc, ctx.pc);
> diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
> index 9443713..6c1ff68 100644
> --- a/target-sparc/cpu.c
> +++ b/target-sparc/cpu.c
> @@ -32,7 +32,7 @@ static void sparc_cpu_reset(CPUState *s)
>
> scc->parent_reset(s);
>
> - memset(env, 0, offsetof(CPUSPARCState, breakpoints));
> + memset(env, 0, offsetof(CPUSPARCState, version));
> tlb_flush(env, 1);
> env->cwp = 0;
> #ifndef TARGET_SPARC64
> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
> index cfa1e0d..69c6154 100644
> --- a/target-sparc/cpu.h
> +++ b/target-sparc/cpu.h
> @@ -421,6 +421,7 @@ struct CPUSPARCState {
>
> CPU_COMMON
>
> + /* Fields from here on are preserved across CPU reset. */
> target_ulong version;
> uint32_t nwindows;
>
> diff --git a/target-sparc/translate.c b/target-sparc/translate.c
> index 73f8b9c..bc52c85 100644
> --- a/target-sparc/translate.c
> +++ b/target-sparc/translate.c
> @@ -5254,8 +5254,8 @@ static inline void gen_intermediate_code_internal(SPARCCPU *cpu,
> max_insns = CF_COUNT_MASK;
> gen_tb_start();
> do {
> - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
> - QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
> + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> if (bp->pc == dc->pc) {
> if (dc->pc != pc_start)
> save_state(dc);
> diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
> index 1246895..b4bee99 100644
> --- a/target-unicore32/translate.c
> +++ b/target-unicore32/translate.c
> @@ -1925,8 +1925,8 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
>
> gen_tb_start();
> do {
> - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
> - QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
> + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> if (bp->pc == dc->pc) {
> gen_set_pc_im(dc->pc);
> gen_exception(EXCP_DEBUG);
> diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
> index 24343bd..55d4448 100644
> --- a/target-xtensa/translate.c
> +++ b/target-xtensa/translate.c
> @@ -2871,10 +2871,11 @@ invalid_opcode:
>
> static void check_breakpoint(CPUXtensaState *env, DisasContext *dc)
> {
> + CPUState *cs = CPU(xtensa_env_get_cpu(env));
> CPUBreakpoint *bp;
>
> - if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
> - QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
> + if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
> + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
> if (bp->pc == dc->pc) {
> tcg_gen_movi_i32(cpu_pc, dc->pc);
> gen_exception(dc, EXCP_DEBUG);
target-openrisc: Tested-by: Jia Liu <proljc@gmail.com>
> --
> 1.8.1.4
>
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [RFC qom-cpu 17/41] cpu: Move tlb_flush_{addr, mask} fields from CPU_COMMON_TLB to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (15 preceding siblings ...)
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 16/41] cpu: Move breakpoints field " Andreas Färber
@ 2013-09-04 9:04 ` Andreas Färber
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 18/41] exec: Change tlb_fill() argument " Andreas Färber
` (26 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:04 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Change their type to vaddr but keep comparing target_ulongs for now.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cputlb.c | 27 ++++++++++++++-------------
include/exec/cpu-defs.h | 2 --
include/qom/cpu.h | 3 +++
3 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index e8131d8..e02663c 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -74,8 +74,8 @@ void tlb_flush(CPUArchState *env, int flush_global)
memset(cpu->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof(void *));
- env->tlb_flush_addr = -1;
- env->tlb_flush_mask = 0;
+ cpu->tlb_flush_addr = -1;
+ cpu->tlb_flush_mask = 0;
tlb_flush_count++;
}
@@ -101,11 +101,11 @@ void tlb_flush_page(CPUArchState *env, target_ulong addr)
printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr);
#endif
/* Check if we need to flush due to large pages. */
- if ((addr & env->tlb_flush_mask) == env->tlb_flush_addr) {
+ if ((addr & cpu->tlb_flush_mask) == cpu->tlb_flush_addr) {
#if defined(DEBUG_TLB)
- printf("tlb_flush_page: forced full flush ("
- TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
- env->tlb_flush_addr, env->tlb_flush_mask);
+ printf("tlb_flush_page: forced full flush (%"
+ VADDR_PRIx "/%" VADDR_PRIx ")\n",
+ cpu->tlb_flush_addr, cpu->tlb_flush_mask);
#endif
tlb_flush(env, 1);
return;
@@ -215,22 +215,23 @@ void tlb_set_dirty(CPUArchState *env, target_ulong vaddr)
static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
target_ulong size)
{
+ CPUState *cpu = ENV_GET_CPU(env);
target_ulong mask = ~(size - 1);
- if (env->tlb_flush_addr == (target_ulong)-1) {
- env->tlb_flush_addr = vaddr & mask;
- env->tlb_flush_mask = mask;
+ if ((target_ulong)cpu->tlb_flush_addr == (target_ulong)-1) {
+ cpu->tlb_flush_addr = vaddr & mask;
+ cpu->tlb_flush_mask = mask;
return;
}
/* Extend the existing region to include the new page.
This is a compromise between unnecessary flushes and the cost
of maintaining a full variable size TLB. */
- mask &= env->tlb_flush_mask;
- while (((env->tlb_flush_addr ^ vaddr) & mask) != 0) {
+ mask &= cpu->tlb_flush_mask;
+ while (((cpu->tlb_flush_addr ^ vaddr) & mask) != 0) {
mask <<= 1;
}
- env->tlb_flush_addr &= mask;
- env->tlb_flush_mask = mask;
+ cpu->tlb_flush_addr &= mask;
+ cpu->tlb_flush_mask = mask;
}
/* Add a new TLB entry. At most one entry for a given virtual address
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index d090594..460f7cf 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -103,8 +103,6 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
/* The meaning of the MMU modes is defined in the target code. */ \
CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
- target_ulong tlb_flush_addr; \
- target_ulong tlb_flush_mask;
#else
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index fc3d345..5349805 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -252,6 +252,9 @@ struct CPUState {
void *opaque;
+ vaddr tlb_flush_addr;
+ vaddr tlb_flush_mask;
+
/* In order to avoid passing too many arguments to the MMIO helpers,
* we store some rarely used information in the CPU context.
*/
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 18/41] exec: Change tlb_fill() argument to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (16 preceding siblings ...)
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 17/41] cpu: Move tlb_flush_{addr, mask} fields from CPU_COMMON_TLB " Andreas Färber
@ 2013-09-04 9:04 ` Andreas Färber
2013-09-04 12:49 ` Jia Liu
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 19/41] cpu-exec: Change cpu_loop_exit() " Andreas Färber
` (25 subsequent siblings)
43 siblings, 1 reply; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:04 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Anthony Green, Alexander Graf, Blue Swirl,
Max Filippov, Michael Walle, open list:PowerPC, Paul Brook,
Edgar E. Iglesias, Guan Xuetao, Andreas Färber,
Aurelien Jarno, Richard Henderson
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
include/exec/exec-all.h | 2 +-
include/exec/softmmu_template.h | 4 ++--
target-alpha/mem_helper.c | 8 +++++---
target-arm/op_helper.c | 12 +++++++-----
target-cris/op_helper.c | 7 ++++---
target-i386/mem_helper.c | 12 +++++++-----
target-lm32/op_helper.c | 13 ++++++++-----
target-m68k/op_helper.c | 8 +++++---
target-microblaze/op_helper.c | 13 ++++++++-----
target-mips/op_helper.c | 7 ++++---
target-moxie/helper.c | 7 ++++---
target-openrisc/mmu_helper.c | 8 +++++---
target-ppc/mmu_helper.c | 9 +++++----
target-s390x/mem_helper.c | 8 +++++---
target-sh4/op_helper.c | 8 +++++---
target-sparc/ldst_helper.c | 8 +++++---
target-unicore32/op_helper.c | 8 +++++---
target-xtensa/op_helper.c | 6 ++++--
18 files changed, 89 insertions(+), 59 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index e61b3f1..4429924 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -374,7 +374,7 @@ bool io_mem_read(struct MemoryRegion *mr, hwaddr addr,
bool io_mem_write(struct MemoryRegion *mr, hwaddr addr,
uint64_t value, unsigned size);
-void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr);
uint8_t helper_ldb_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h
index bbfda31..8dc0901 100644
--- a/include/exec/softmmu_template.h
+++ b/include/exec/softmmu_template.h
@@ -114,7 +114,7 @@ glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)(CPUArchState *env,
do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
}
#endif
- tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
+ tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
}
@@ -230,7 +230,7 @@ glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
}
#endif
- tlb_fill(env, addr, 1, mmu_idx, retaddr);
+ tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
}
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index 22fcbe1..c6c0182 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -144,14 +144,16 @@ void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr,
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUAlphaState *env, target_ulong addr, int is_write,
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
int mmu_idx, uintptr_t retaddr)
{
- AlphaCPU *cpu = alpha_env_get_cpu(env);
int ret;
- ret = alpha_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
+ ret = alpha_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret != 0)) {
+ AlphaCPU *cpu = ALPHA_CPU(cs);
+ CPUAlphaState *env = &cpu->env;
+
if (retaddr) {
cpu_restore_state(env, retaddr);
}
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 2c2b3b7..d05f522 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -72,17 +72,19 @@ uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
#include "exec/softmmu_template.h"
/* try to fill the TLB and return an exception if error. If retaddr is
- NULL, it means that the function was called in C code (i.e. not
- from generated code or from helper.c) */
-void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
+ * NULL, it means that the function was called in C code (i.e. not
+ * from generated code or from helper.c)
+ */
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
- ARMCPU *cpu = arm_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
int ret;
ret = arm_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret)) {
+ ARMCPU *cpu = ARM_CPU(cs);
+ CPUARMState *env = &cpu->env;
+
if (retaddr) {
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
index 9b20b94..68a5caa 100644
--- a/target-cris/op_helper.c
+++ b/target-cris/op_helper.c
@@ -54,15 +54,16 @@
/* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
-void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
- CRISCPU *cpu = cris_env_get_cpu(env);
+ CRISCPU *cpu = CRIS_CPU(cs);
+ CPUCRISState *env = &cpu->env;
int ret;
D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__,
env->pc, env->pregs[PR_EDA], (void *)retaddr);
- ret = cris_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
+ ret = cris_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */
diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c
index c0d3b45..2f0691b 100644
--- a/target-i386/mem_helper.c
+++ b/target-i386/mem_helper.c
@@ -129,18 +129,20 @@ void helper_boundl(CPUX86State *env, target_ulong a0, int v)
#if !defined(CONFIG_USER_ONLY)
/* try to fill the TLB and return an exception if error. If retaddr is
- NULL, it means that the function was called in C code (i.e. not
- from generated code or from helper.c) */
+ * NULL, it means that the function was called in C code (i.e. not
+ * from generated code or from helper.c)
+ */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUX86State *env, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
- X86CPU *cpu = x86_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
int ret;
ret = x86_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (ret) {
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
+
if (retaddr) {
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
index c7ad910..d4ee1ba 100644
--- a/target-lm32/op_helper.c
+++ b/target-lm32/op_helper.c
@@ -77,16 +77,19 @@ uint32_t HELPER(rcsr_jrx)(CPULM32State *env)
}
/* Try to fill the TLB and return an exception if error. If retaddr is
- NULL, it means that the function was called in C code (i.e. not
- from generated code or from helper.c) */
-void tlb_fill(CPULM32State *env, target_ulong addr, int is_write, int mmu_idx,
+ * NULL, it means that the function was called in C code (i.e. not
+ * from generated code or from helper.c)
+ */
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
- LM32CPU *cpu = lm32_env_get_cpu(env);
int ret;
- ret = lm32_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
+ ret = lm32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret)) {
+ LM32CPU *cpu = LM32_CPU(cs);
+ CPULM32State *env = &cpu->env;
+
if (retaddr) {
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
index 466ad0c..9ad3a9d 100644
--- a/target-m68k/op_helper.c
+++ b/target-m68k/op_helper.c
@@ -53,14 +53,16 @@ extern int semihosting_enabled;
/* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
-void tlb_fill(CPUM68KState *env, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
- M68kCPU *cpu = m68k_env_get_cpu(env);
int ret;
- ret = m68k_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
+ ret = m68k_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret)) {
+ M68kCPU *cpu = M68K_CPU(cs);
+ CPUM68KState *env = &cpu->env;
+
if (retaddr) {
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index 318185a..9e39411 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -39,16 +39,19 @@
#include "exec/softmmu_template.h"
/* Try to fill the TLB and return an exception if error. If retaddr is
- NULL, it means that the function was called in C code (i.e. not
- from generated code or from helper.c) */
-void tlb_fill(CPUMBState *env, target_ulong addr, int is_write, int mmu_idx,
+ * NULL, it means that the function was called in C code (i.e. not
+ * from generated code or from helper.c)
+ */
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
- MicroBlazeCPU *cpu = mb_env_get_cpu(env);
int ret;
- ret = mb_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
+ ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret)) {
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+ CPUMBState *env = &cpu->env;
+
if (retaddr) {
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index eeb98a6..7208659 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2133,15 +2133,16 @@ static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr);
}
-void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
- MIPSCPU *cpu = mips_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
int ret;
ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (ret) {
+ MIPSCPU *cpu = MIPS_CPU(cs);
+ CPUMIPSState *env = &cpu->env;
+
do_raise_exception_err(env, cs->exception_index,
env->error_code, retaddr);
}
diff --git a/target-moxie/helper.c b/target-moxie/helper.c
index 3b14f37..06a4c72 100644
--- a/target-moxie/helper.c
+++ b/target-moxie/helper.c
@@ -46,13 +46,14 @@
/* Try to fill the TLB and return an exception if error. If retaddr is
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
-void tlb_fill(CPUMoxieState *env, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
- MoxieCPU *cpu = moxie_env_get_cpu(env);
+ MoxieCPU *cpu = MOXIE_CPU(cs);
+ CPUMoxieState *env = &cpu->env;
int ret;
- ret = moxie_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
+ ret = moxie_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
cpu_restore_state(env, retaddr);
diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c
index b023a5f..e3fe6c7 100644
--- a/target-openrisc/mmu_helper.c
+++ b/target-openrisc/mmu_helper.c
@@ -36,15 +36,17 @@
#define SHIFT 3
#include "exec/softmmu_template.h"
-void tlb_fill(CPUOpenRISCState *env, target_ulong addr, int is_write,
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
int mmu_idx, uintptr_t retaddr)
{
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
int ret;
- ret = openrisc_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
+ ret = openrisc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (ret) {
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+ CPUOpenRISCState *env = &cpu->env;
+
if (retaddr) {
/* now we have a real cpu fault. */
cpu_restore_state(env, retaddr);
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 79a9134..cc31482 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -2892,11 +2892,12 @@ void helper_booke206_tlbflush(CPUPPCState *env, uint32_t type)
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
- CPUState *cpu = CPU(ppc_env_get_cpu(env));
- PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
+ CPUPPCState *env = &cpu->env;
int ret;
if (pcc->handle_mmu_fault) {
@@ -2909,6 +2910,6 @@ void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx,
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
}
- helper_raise_exception_err(env, cpu->exception_index, env->error_code);
+ helper_raise_exception_err(env, cs->exception_index, env->error_code);
}
}
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index e2748a7..8bd131b 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -44,14 +44,16 @@
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUS390XState *env, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
- S390CPU *cpu = s390_env_get_cpu(env);
int ret;
- ret = s390_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
+ ret = s390_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret != 0)) {
+ S390CPU *cpu = S390_CPU(cs);
+ CPUS390XState *env = &cpu->env;
+
if (likely(retaddr)) {
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 03633f0..6e527cf 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -38,15 +38,17 @@
#define SHIFT 3
#include "exec/softmmu_template.h"
-void tlb_fill(CPUSH4State *env, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
- SuperHCPU *cpu = sh_env_get_cpu(env);
int ret;
- ret = superh_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
+ ret = superh_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (ret) {
/* now we have a real cpu fault */
+ SuperHCPU *cpu = SUPERH_CPU(cs);
+ CPUSH4State *env = &cpu->env;
+
if (retaddr) {
cpu_restore_state(env, retaddr);
}
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index af7c289..973fcb6 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -2430,14 +2430,16 @@ static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env,
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(CPUSPARCState *env, target_ulong addr, int is_write, int mmu_idx,
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
- SPARCCPU *cpu = sparc_env_get_cpu(env);
int ret;
- ret = sparc_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
+ ret = sparc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (ret) {
+ SPARCCPU *cpu = SPARC_CPU(cs);
+ CPUSPARCState *env = &cpu->env;
+
if (retaddr) {
cpu_restore_state(env, retaddr);
}
diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
index cd2cbef..3efc6a8 100644
--- a/target-unicore32/op_helper.c
+++ b/target-unicore32/op_helper.c
@@ -257,14 +257,16 @@ uint32_t HELPER(ror_cc)(CPUUniCore32State *env, uint32_t x, uint32_t i)
#define SHIFT 3
#include "exec/softmmu_template.h"
-void tlb_fill(CPUUniCore32State *env, target_ulong addr, int is_write,
+void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
int mmu_idx, uintptr_t retaddr)
{
- UniCore32CPU *cpu = uc32_env_get_cpu(env);
int ret;
- ret = uc32_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
+ ret = uc32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret)) {
+ UniCore32CPU *cpu = UNICORE32_CPU(cs);
+ CPUUniCore32State *env = &cpu->env;
+
if (retaddr) {
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 2e006e4..cc1d5e2 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -59,9 +59,11 @@ static void do_unaligned_access(CPUXtensaState *env,
}
}
-void tlb_fill(CPUXtensaState *env,
- target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr)
+void tlb_fill(CPUState *cs,
+ target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr)
{
+ XtensaCPU *cpu = XTENSA_CPU(cs);
+ CPUXtensaState *env = &cpu->env;
uint32_t paddr;
uint32_t page_size;
unsigned access;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 18/41] exec: Change tlb_fill() argument to CPUState
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 18/41] exec: Change tlb_fill() argument " Andreas Färber
@ 2013-09-04 12:49 ` Jia Liu
0 siblings, 0 replies; 68+ messages in thread
From: Jia Liu @ 2013-09-04 12:49 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Anthony Green, qemu-devel@nongnu.org,
Alexander Graf, Blue Swirl, Max Filippov, Michael Walle,
open list:PowerPC, Paul Brook, Edgar E. Iglesias, Guan Xuetao,
Aurelien Jarno, Richard Henderson
On Wed, Sep 4, 2013 at 5:04 PM, Andreas Färber <afaerber@suse.de> wrote:
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
> include/exec/exec-all.h | 2 +-
> include/exec/softmmu_template.h | 4 ++--
> target-alpha/mem_helper.c | 8 +++++---
> target-arm/op_helper.c | 12 +++++++-----
> target-cris/op_helper.c | 7 ++++---
> target-i386/mem_helper.c | 12 +++++++-----
> target-lm32/op_helper.c | 13 ++++++++-----
> target-m68k/op_helper.c | 8 +++++---
> target-microblaze/op_helper.c | 13 ++++++++-----
> target-mips/op_helper.c | 7 ++++---
> target-moxie/helper.c | 7 ++++---
> target-openrisc/mmu_helper.c | 8 +++++---
> target-ppc/mmu_helper.c | 9 +++++----
> target-s390x/mem_helper.c | 8 +++++---
> target-sh4/op_helper.c | 8 +++++---
> target-sparc/ldst_helper.c | 8 +++++---
> target-unicore32/op_helper.c | 8 +++++---
> target-xtensa/op_helper.c | 6 ++++--
> 18 files changed, 89 insertions(+), 59 deletions(-)
>
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index e61b3f1..4429924 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -374,7 +374,7 @@ bool io_mem_read(struct MemoryRegion *mr, hwaddr addr,
> bool io_mem_write(struct MemoryRegion *mr, hwaddr addr,
> uint64_t value, unsigned size);
>
> -void tlb_fill(CPUArchState *env1, target_ulong addr, int is_write, int mmu_idx,
> +void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr);
>
> uint8_t helper_ldb_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
> diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h
> index bbfda31..8dc0901 100644
> --- a/include/exec/softmmu_template.h
> +++ b/include/exec/softmmu_template.h
> @@ -114,7 +114,7 @@ glue(glue(helper_ret_ld, USUFFIX), MMUSUFFIX)(CPUArchState *env,
> do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
> }
> #endif
> - tlb_fill(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
> + tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
> tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
> }
>
> @@ -230,7 +230,7 @@ glue(glue(helper_ret_st, SUFFIX), MMUSUFFIX)(CPUArchState *env,
> do_unaligned_access(env, addr, 1, mmu_idx, retaddr);
> }
> #endif
> - tlb_fill(env, addr, 1, mmu_idx, retaddr);
> + tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
> tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
> }
>
> diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
> index 22fcbe1..c6c0182 100644
> --- a/target-alpha/mem_helper.c
> +++ b/target-alpha/mem_helper.c
> @@ -144,14 +144,16 @@ void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr,
> NULL, it means that the function was called in C code (i.e. not
> from generated code or from helper.c) */
> /* XXX: fix it to restore all registers */
> -void tlb_fill(CPUAlphaState *env, target_ulong addr, int is_write,
> +void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
> int mmu_idx, uintptr_t retaddr)
> {
> - AlphaCPU *cpu = alpha_env_get_cpu(env);
> int ret;
>
> - ret = alpha_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> + ret = alpha_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (unlikely(ret != 0)) {
> + AlphaCPU *cpu = ALPHA_CPU(cs);
> + CPUAlphaState *env = &cpu->env;
> +
> if (retaddr) {
> cpu_restore_state(env, retaddr);
> }
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index 2c2b3b7..d05f522 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -72,17 +72,19 @@ uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
> #include "exec/softmmu_template.h"
>
> /* try to fill the TLB and return an exception if error. If retaddr is
> - NULL, it means that the function was called in C code (i.e. not
> - from generated code or from helper.c) */
> -void tlb_fill(CPUARMState *env, target_ulong addr, int is_write, int mmu_idx,
> + * NULL, it means that the function was called in C code (i.e. not
> + * from generated code or from helper.c)
> + */
> +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> - ARMCPU *cpu = arm_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> int ret;
>
> ret = arm_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> + ARMCPU *cpu = ARM_CPU(cs);
> + CPUARMState *env = &cpu->env;
> +
> if (retaddr) {
> /* now we have a real cpu fault */
> cpu_restore_state(env, retaddr);
> diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
> index 9b20b94..68a5caa 100644
> --- a/target-cris/op_helper.c
> +++ b/target-cris/op_helper.c
> @@ -54,15 +54,16 @@
> /* Try to fill the TLB and return an exception if error. If retaddr is
> NULL, it means that the function was called in C code (i.e. not
> from generated code or from helper.c) */
> -void tlb_fill(CPUCRISState *env, target_ulong addr, int is_write, int mmu_idx,
> +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> - CRISCPU *cpu = cris_env_get_cpu(env);
> + CRISCPU *cpu = CRIS_CPU(cs);
> + CPUCRISState *env = &cpu->env;
> int ret;
>
> D_LOG("%s pc=%x tpc=%x ra=%p\n", __func__,
> env->pc, env->pregs[PR_EDA], (void *)retaddr);
> - ret = cris_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> + ret = cris_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> if (retaddr) {
> /* now we have a real cpu fault */
> diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c
> index c0d3b45..2f0691b 100644
> --- a/target-i386/mem_helper.c
> +++ b/target-i386/mem_helper.c
> @@ -129,18 +129,20 @@ void helper_boundl(CPUX86State *env, target_ulong a0, int v)
>
> #if !defined(CONFIG_USER_ONLY)
> /* try to fill the TLB and return an exception if error. If retaddr is
> - NULL, it means that the function was called in C code (i.e. not
> - from generated code or from helper.c) */
> + * NULL, it means that the function was called in C code (i.e. not
> + * from generated code or from helper.c)
> + */
> /* XXX: fix it to restore all registers */
> -void tlb_fill(CPUX86State *env, target_ulong addr, int is_write, int mmu_idx,
> +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> - X86CPU *cpu = x86_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> int ret;
>
> ret = x86_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (ret) {
> + X86CPU *cpu = X86_CPU(cs);
> + CPUX86State *env = &cpu->env;
> +
> if (retaddr) {
> /* now we have a real cpu fault */
> cpu_restore_state(env, retaddr);
> diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
> index c7ad910..d4ee1ba 100644
> --- a/target-lm32/op_helper.c
> +++ b/target-lm32/op_helper.c
> @@ -77,16 +77,19 @@ uint32_t HELPER(rcsr_jrx)(CPULM32State *env)
> }
>
> /* Try to fill the TLB and return an exception if error. If retaddr is
> - NULL, it means that the function was called in C code (i.e. not
> - from generated code or from helper.c) */
> -void tlb_fill(CPULM32State *env, target_ulong addr, int is_write, int mmu_idx,
> + * NULL, it means that the function was called in C code (i.e. not
> + * from generated code or from helper.c)
> + */
> +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> - LM32CPU *cpu = lm32_env_get_cpu(env);
> int ret;
>
> - ret = lm32_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> + ret = lm32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> + LM32CPU *cpu = LM32_CPU(cs);
> + CPULM32State *env = &cpu->env;
> +
> if (retaddr) {
> /* now we have a real cpu fault */
> cpu_restore_state(env, retaddr);
> diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
> index 466ad0c..9ad3a9d 100644
> --- a/target-m68k/op_helper.c
> +++ b/target-m68k/op_helper.c
> @@ -53,14 +53,16 @@ extern int semihosting_enabled;
> /* Try to fill the TLB and return an exception if error. If retaddr is
> NULL, it means that the function was called in C code (i.e. not
> from generated code or from helper.c) */
> -void tlb_fill(CPUM68KState *env, target_ulong addr, int is_write, int mmu_idx,
> +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> - M68kCPU *cpu = m68k_env_get_cpu(env);
> int ret;
>
> - ret = m68k_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> + ret = m68k_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> + M68kCPU *cpu = M68K_CPU(cs);
> + CPUM68KState *env = &cpu->env;
> +
> if (retaddr) {
> /* now we have a real cpu fault */
> cpu_restore_state(env, retaddr);
> diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
> index 318185a..9e39411 100644
> --- a/target-microblaze/op_helper.c
> +++ b/target-microblaze/op_helper.c
> @@ -39,16 +39,19 @@
> #include "exec/softmmu_template.h"
>
> /* Try to fill the TLB and return an exception if error. If retaddr is
> - NULL, it means that the function was called in C code (i.e. not
> - from generated code or from helper.c) */
> -void tlb_fill(CPUMBState *env, target_ulong addr, int is_write, int mmu_idx,
> + * NULL, it means that the function was called in C code (i.e. not
> + * from generated code or from helper.c)
> + */
> +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> - MicroBlazeCPU *cpu = mb_env_get_cpu(env);
> int ret;
>
> - ret = mb_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> + ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
> + CPUMBState *env = &cpu->env;
> +
> if (retaddr) {
> /* now we have a real cpu fault */
> cpu_restore_state(env, retaddr);
> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
> index eeb98a6..7208659 100644
> --- a/target-mips/op_helper.c
> +++ b/target-mips/op_helper.c
> @@ -2133,15 +2133,16 @@ static void do_unaligned_access(CPUMIPSState *env, target_ulong addr,
> do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr);
> }
>
> -void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx,
> +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> - MIPSCPU *cpu = mips_env_get_cpu(env);
> - CPUState *cs = CPU(cpu);
> int ret;
>
> ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (ret) {
> + MIPSCPU *cpu = MIPS_CPU(cs);
> + CPUMIPSState *env = &cpu->env;
> +
> do_raise_exception_err(env, cs->exception_index,
> env->error_code, retaddr);
> }
> diff --git a/target-moxie/helper.c b/target-moxie/helper.c
> index 3b14f37..06a4c72 100644
> --- a/target-moxie/helper.c
> +++ b/target-moxie/helper.c
> @@ -46,13 +46,14 @@
> /* Try to fill the TLB and return an exception if error. If retaddr is
> NULL, it means that the function was called in C code (i.e. not
> from generated code or from helper.c) */
> -void tlb_fill(CPUMoxieState *env, target_ulong addr, int is_write, int mmu_idx,
> +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> - MoxieCPU *cpu = moxie_env_get_cpu(env);
> + MoxieCPU *cpu = MOXIE_CPU(cs);
> + CPUMoxieState *env = &cpu->env;
> int ret;
>
> - ret = moxie_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> + ret = moxie_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> if (retaddr) {
> cpu_restore_state(env, retaddr);
> diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c
> index b023a5f..e3fe6c7 100644
> --- a/target-openrisc/mmu_helper.c
> +++ b/target-openrisc/mmu_helper.c
> @@ -36,15 +36,17 @@
> #define SHIFT 3
> #include "exec/softmmu_template.h"
>
> -void tlb_fill(CPUOpenRISCState *env, target_ulong addr, int is_write,
> +void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
> int mmu_idx, uintptr_t retaddr)
> {
> - OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
> int ret;
>
> - ret = openrisc_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> + ret = openrisc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
>
> if (ret) {
> + OpenRISCCPU *cpu = OPENRISC_CPU(cs);
> + CPUOpenRISCState *env = &cpu->env;
> +
> if (retaddr) {
> /* now we have a real cpu fault. */
> cpu_restore_state(env, retaddr);
> diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
> index 79a9134..cc31482 100644
> --- a/target-ppc/mmu_helper.c
> +++ b/target-ppc/mmu_helper.c
> @@ -2892,11 +2892,12 @@ void helper_booke206_tlbflush(CPUPPCState *env, uint32_t type)
> NULL, it means that the function was called in C code (i.e. not
> from generated code or from helper.c) */
> /* XXX: fix it to restore all registers */
> -void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx,
> +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> - CPUState *cpu = CPU(ppc_env_get_cpu(env));
> - PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> + PowerPCCPU *cpu = POWERPC_CPU(cs);
> + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
> + CPUPPCState *env = &cpu->env;
> int ret;
>
> if (pcc->handle_mmu_fault) {
> @@ -2909,6 +2910,6 @@ void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx,
> /* now we have a real cpu fault */
> cpu_restore_state(env, retaddr);
> }
> - helper_raise_exception_err(env, cpu->exception_index, env->error_code);
> + helper_raise_exception_err(env, cs->exception_index, env->error_code);
> }
> }
> diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
> index e2748a7..8bd131b 100644
> --- a/target-s390x/mem_helper.c
> +++ b/target-s390x/mem_helper.c
> @@ -44,14 +44,16 @@
> NULL, it means that the function was called in C code (i.e. not
> from generated code or from helper.c) */
> /* XXX: fix it to restore all registers */
> -void tlb_fill(CPUS390XState *env, target_ulong addr, int is_write, int mmu_idx,
> +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> - S390CPU *cpu = s390_env_get_cpu(env);
> int ret;
>
> - ret = s390_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> + ret = s390_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (unlikely(ret != 0)) {
> + S390CPU *cpu = S390_CPU(cs);
> + CPUS390XState *env = &cpu->env;
> +
> if (likely(retaddr)) {
> /* now we have a real cpu fault */
> cpu_restore_state(env, retaddr);
> diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
> index 03633f0..6e527cf 100644
> --- a/target-sh4/op_helper.c
> +++ b/target-sh4/op_helper.c
> @@ -38,15 +38,17 @@
> #define SHIFT 3
> #include "exec/softmmu_template.h"
>
> -void tlb_fill(CPUSH4State *env, target_ulong addr, int is_write, int mmu_idx,
> +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> - SuperHCPU *cpu = sh_env_get_cpu(env);
> int ret;
>
> - ret = superh_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> + ret = superh_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (ret) {
> /* now we have a real cpu fault */
> + SuperHCPU *cpu = SUPERH_CPU(cs);
> + CPUSH4State *env = &cpu->env;
> +
> if (retaddr) {
> cpu_restore_state(env, retaddr);
> }
> diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
> index af7c289..973fcb6 100644
> --- a/target-sparc/ldst_helper.c
> +++ b/target-sparc/ldst_helper.c
> @@ -2430,14 +2430,16 @@ static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env,
> NULL, it means that the function was called in C code (i.e. not
> from generated code or from helper.c) */
> /* XXX: fix it to restore all registers */
> -void tlb_fill(CPUSPARCState *env, target_ulong addr, int is_write, int mmu_idx,
> +void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> - SPARCCPU *cpu = sparc_env_get_cpu(env);
> int ret;
>
> - ret = sparc_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> + ret = sparc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (ret) {
> + SPARCCPU *cpu = SPARC_CPU(cs);
> + CPUSPARCState *env = &cpu->env;
> +
> if (retaddr) {
> cpu_restore_state(env, retaddr);
> }
> diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
> index cd2cbef..3efc6a8 100644
> --- a/target-unicore32/op_helper.c
> +++ b/target-unicore32/op_helper.c
> @@ -257,14 +257,16 @@ uint32_t HELPER(ror_cc)(CPUUniCore32State *env, uint32_t x, uint32_t i)
> #define SHIFT 3
> #include "exec/softmmu_template.h"
>
> -void tlb_fill(CPUUniCore32State *env, target_ulong addr, int is_write,
> +void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
> int mmu_idx, uintptr_t retaddr)
> {
> - UniCore32CPU *cpu = uc32_env_get_cpu(env);
> int ret;
>
> - ret = uc32_cpu_handle_mmu_fault(CPU(cpu), addr, is_write, mmu_idx);
> + ret = uc32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> + UniCore32CPU *cpu = UNICORE32_CPU(cs);
> + CPUUniCore32State *env = &cpu->env;
> +
> if (retaddr) {
> /* now we have a real cpu fault */
> cpu_restore_state(env, retaddr);
> diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
> index 2e006e4..cc1d5e2 100644
> --- a/target-xtensa/op_helper.c
> +++ b/target-xtensa/op_helper.c
> @@ -59,9 +59,11 @@ static void do_unaligned_access(CPUXtensaState *env,
> }
> }
>
> -void tlb_fill(CPUXtensaState *env,
> - target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr)
> +void tlb_fill(CPUState *cs,
> + target_ulong vaddr, int is_write, int mmu_idx, uintptr_t retaddr)
> {
> + XtensaCPU *cpu = XTENSA_CPU(cs);
> + CPUXtensaState *env = &cpu->env;
> uint32_t paddr;
> uint32_t page_size;
> unsigned access;
target-openrisc: Tested-by: Jia Liu <proljc@gmail.com>
> --
> 1.8.1.4
>
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [RFC qom-cpu 19/41] cpu-exec: Change cpu_loop_exit() argument to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (17 preceding siblings ...)
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 18/41] exec: Change tlb_fill() argument " Andreas Färber
@ 2013-09-04 9:04 ` Andreas Färber
2013-09-04 12:49 ` Jia Liu
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 20/41] translate-all: Change cpu_restore_state() " Andreas Färber
` (24 subsequent siblings)
43 siblings, 1 reply; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:04 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Anthony Green, Alexander Graf, Blue Swirl,
Max Filippov, Michael Walle, open list:PowerPC, Paul Brook,
Edgar E. Iglesias, Guan Xuetao, Andreas Färber,
Aurelien Jarno, Richard Henderson
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cpu-exec.c | 14 ++++++--------
exec.c | 2 +-
include/exec/exec-all.h | 2 +-
target-alpha/helper.c | 4 ++--
target-alpha/mem_helper.c | 4 ++--
target-arm/op_helper.c | 6 +++---
target-cris/op_helper.c | 4 ++--
target-i386/excp_helper.c | 2 +-
target-i386/misc_helper.c | 4 ++--
target-i386/seg_helper.c | 2 +-
target-i386/svm_helper.c | 8 ++++----
target-lm32/op_helper.c | 6 +++---
target-m68k/op_helper.c | 6 +++---
target-microblaze/op_helper.c | 4 ++--
target-mips/op_helper.c | 4 ++--
target-moxie/helper.c | 6 +++---
target-openrisc/exception.c | 2 +-
target-openrisc/mmu_helper.c | 2 +-
target-ppc/excp_helper.c | 2 +-
target-s390x/cc_helper.c | 2 +-
target-s390x/mem_helper.c | 6 +++---
target-s390x/misc_helper.c | 10 +++++-----
target-sh4/op_helper.c | 4 ++--
target-sparc/helper.c | 6 +++---
target-sparc/ldst_helper.c | 2 +-
target-unicore32/op_helper.c | 4 ++--
target-xtensa/op_helper.c | 4 ++--
user-exec.c | 4 ++--
28 files changed, 62 insertions(+), 64 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 209380d..a1b8b96 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -23,10 +23,8 @@
#include "qemu/atomic.h"
#include "sysemu/qtest.h"
-void cpu_loop_exit(CPUArchState *env)
+void cpu_loop_exit(CPUState *cpu)
{
- CPUState *cpu = ENV_GET_CPU(env);
-
cpu->current_tb = NULL;
siglongjmp(cpu->jmp_env, 1);
}
@@ -305,7 +303,7 @@ int cpu_exec(CPUArchState *env)
if (interrupt_request & CPU_INTERRUPT_DEBUG) {
cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
cpu->exception_index = EXCP_DEBUG;
- cpu_loop_exit(env);
+ cpu_loop_exit(cpu);
}
#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
@@ -314,7 +312,7 @@ int cpu_exec(CPUArchState *env)
cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
cpu->halted = 1;
cpu->exception_index = EXCP_HLT;
- cpu_loop_exit(env);
+ cpu_loop_exit(cpu);
}
#endif
#if defined(TARGET_I386)
@@ -329,7 +327,7 @@ int cpu_exec(CPUArchState *env)
0);
do_cpu_init(x86_env_get_cpu(env));
cpu->exception_index = EXCP_HALTED;
- cpu_loop_exit(env);
+ cpu_loop_exit(cpu);
} else if (interrupt_request & CPU_INTERRUPT_SIPI) {
do_cpu_sipi(x86_env_get_cpu(env));
} else if (env->hflags2 & HF2_GIF_MASK) {
@@ -578,7 +576,7 @@ int cpu_exec(CPUArchState *env)
if (unlikely(cpu->exit_request)) {
cpu->exit_request = 0;
cpu->exception_index = EXCP_INTERRUPT;
- cpu_loop_exit(env);
+ cpu_loop_exit(cpu);
}
#if defined(DEBUG_DISAS)
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
@@ -665,7 +663,7 @@ int cpu_exec(CPUArchState *env)
}
cpu->exception_index = EXCP_INTERRUPT;
next_tb = 0;
- cpu_loop_exit(env);
+ cpu_loop_exit(cpu);
}
break;
}
diff --git a/exec.c b/exec.c
index 6ae5a21..06fb881 100644
--- a/exec.c
+++ b/exec.c
@@ -1483,7 +1483,7 @@ static void check_watchpoint(int offset, int len_mask, int flags)
tb_check_watchpoint(env);
if (wp->flags & BP_STOP_BEFORE_ACCESS) {
cpu->exception_index = EXCP_DEBUG;
- cpu_loop_exit(env);
+ cpu_loop_exit(cpu);
} else {
cc->get_tb_cpu_state(cpu, &pc, &cs_base, &cpu_flags);
tb_gen_code(env, pc, cs_base, cpu_flags, 1);
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 4429924..f6b9eac 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -88,7 +88,7 @@ TranslationBlock *tb_gen_code(CPUArchState *env,
target_ulong pc, target_ulong cs_base, int flags,
int cflags);
void cpu_exec_init(CPUArchState *env);
-void QEMU_NORETURN cpu_loop_exit(CPUArchState *env1);
+void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
int page_unprotect(target_ulong address, uintptr_t pc, void *puc);
void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
int is_cpu_write_access);
diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index 6f103ec..41a1394 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -512,7 +512,7 @@ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error)
cs->exception_index = excp;
env->error_code = error;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
/* This may be called from any of the helpers to set up EXCEPTION_INDEX. */
@@ -527,7 +527,7 @@ void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr,
if (retaddr) {
cpu_restore_state(env, retaddr);
}
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
void QEMU_NORETURN arith_excp(CPUAlphaState *env, uintptr_t retaddr,
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index c6c0182..c2bd64a 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -108,7 +108,7 @@ static void do_unaligned_access(CPUAlphaState *env, target_ulong addr,
env->trap_arg2 = (insn >> 21) & 31; /* dest regno */
cs->exception_index = EXCP_UNALIGN;
env->error_code = 0;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr,
@@ -158,7 +158,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
cpu_restore_state(env, retaddr);
}
/* Exception index and error code are already set */
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
}
#endif /* CONFIG_USER_ONLY */
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index d05f522..552ca3d 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -28,7 +28,7 @@ static void raise_exception(CPUARMState *env, int tt)
CPUState *cs = CPU(cpu);
cs->exception_index = tt;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
@@ -229,7 +229,7 @@ void HELPER(wfi)(CPUARMState *env)
cs->exception_index = EXCP_HLT;
cs->halted = 1;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
void HELPER(exception)(CPUARMState *env, uint32_t excp)
@@ -237,7 +237,7 @@ void HELPER(exception)(CPUARMState *env, uint32_t excp)
CPUState *cs = CPU(arm_env_get_cpu(env));
cs->exception_index = excp;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
uint32_t HELPER(cpsr_read)(CPUARMState *env)
diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
index 68a5caa..d80b6c9 100644
--- a/target-cris/op_helper.c
+++ b/target-cris/op_helper.c
@@ -72,7 +72,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
helper_top_evaluate_flags(env);
}
}
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
}
@@ -83,7 +83,7 @@ void helper_raise_exception(CPUCRISState *env, uint32_t index)
CPUState *cs = CPU(cris_env_get_cpu(env));
cs->exception_index = index;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
diff --git a/target-i386/excp_helper.c b/target-i386/excp_helper.c
index ec76eba..f337fd2 100644
--- a/target-i386/excp_helper.c
+++ b/target-i386/excp_helper.c
@@ -108,7 +108,7 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno,
env->error_code = error_code;
env->exception_is_int = is_int;
env->exception_next_eip = env->eip + next_eip_addend;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
/* shortcuts to generate exceptions */
diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c
index a058c43..4b7a142 100644
--- a/target-i386/misc_helper.c
+++ b/target-i386/misc_helper.c
@@ -574,7 +574,7 @@ static void do_hlt(X86CPU *cpu)
env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
cs->halted = 1;
cs->exception_index = EXCP_HLT;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
void helper_hlt(CPUX86State *env, int next_eip_addend)
@@ -623,5 +623,5 @@ void helper_debug(CPUX86State *env)
CPUState *cs = CPU(x86_env_get_cpu(env));
cs->exception_index = EXCP_DEBUG;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index b689e94..d030793 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -939,7 +939,7 @@ void helper_syscall(CPUX86State *env, int next_eip_addend)
cs->exception_index = EXCP_SYSCALL;
env->exception_next_eip = env->eip + next_eip_addend;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
#else
void helper_syscall(CPUX86State *env, int next_eip_addend)
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index 3c12cb8..fbf8359 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -305,7 +305,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
env->exception_is_int = 0;
env->exception_next_eip = env->eip;
qemu_log_mask(CPU_LOG_TB_IN_ASM, "NMI");
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
break;
case SVM_EVTINJ_TYPE_EXEPT:
cs->exception_index = vector;
@@ -313,7 +313,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
env->exception_is_int = 0;
env->exception_next_eip = -1;
qemu_log_mask(CPU_LOG_TB_IN_ASM, "EXEPT");
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
break;
case SVM_EVTINJ_TYPE_SOFT:
cs->exception_index = vector;
@@ -321,7 +321,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
env->exception_is_int = 1;
env->exception_next_eip = env->eip;
qemu_log_mask(CPU_LOG_TB_IN_ASM, "SOFT");
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
break;
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, " %#x %#x\n", cs->exception_index,
@@ -710,7 +710,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
env->error_code = 0;
env->old_exception = -1;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
index d4ee1ba..acf2412 100644
--- a/target-lm32/op_helper.c
+++ b/target-lm32/op_helper.c
@@ -24,7 +24,7 @@ void HELPER(raise_exception)(CPULM32State *env, uint32_t index)
CPUState *cs = CPU(lm32_env_get_cpu(env));
cs->exception_index = index;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
void HELPER(hlt)(CPULM32State *env)
@@ -33,7 +33,7 @@ void HELPER(hlt)(CPULM32State *env)
cs->halted = 1;
cs->exception_index = EXCP_HLT;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
void HELPER(wcsr_im)(CPULM32State *env, uint32_t im)
@@ -94,7 +94,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
}
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
}
#endif
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
index 9ad3a9d..6ab1927 100644
--- a/target-m68k/op_helper.c
+++ b/target-m68k/op_helper.c
@@ -67,7 +67,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
}
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
}
@@ -114,7 +114,7 @@ static void do_interrupt_all(CPUM68KState *env, int is_hw)
}
cs->halted = 1;
cs->exception_index = EXCP_HLT;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
return;
}
if (cs->exception_index >= EXCP_TRAP0
@@ -170,7 +170,7 @@ static void raise_exception(CPUM68KState *env, int tt)
CPUState *cs = CPU(m68k_env_get_cpu(env));
cs->exception_index = tt;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
void HELPER(raise_exception)(CPUM68KState *env, uint32_t tt)
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index 9e39411..f476132 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -56,7 +56,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
}
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
}
#endif
@@ -101,7 +101,7 @@ void helper_raise_exception(CPUMBState *env, uint32_t index)
CPUState *cs = CPU(mb_env_get_cpu(env));
cs->exception_index = index;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
void helper_debug(CPUMBState *env)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 7208659..0e0c540 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -51,7 +51,7 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
cpu_restore_state(env, pc);
}
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
@@ -280,7 +280,7 @@ static inline hwaddr do_translate_address(CPUMIPSState *env,
lladdr = cpu_mips_translate_address(env, address, rw);
if (lladdr == -1LL) {
- cpu_loop_exit(env);
+ cpu_loop_exit(CPU(mips_env_get_cpu(env)));
} else {
return lladdr;
}
diff --git a/target-moxie/helper.c b/target-moxie/helper.c
index 06a4c72..3994c09 100644
--- a/target-moxie/helper.c
+++ b/target-moxie/helper.c
@@ -59,7 +59,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
cpu_restore_state(env, retaddr);
}
}
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
void helper_raise_exception(CPUMoxieState *env, int ex)
@@ -74,7 +74,7 @@ void helper_raise_exception(CPUMoxieState *env, int ex)
env->sregs[5] = env->pc;
/* Jump the the exception handline routine. */
env->pc = env->sregs[1];
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
uint32_t helper_div(CPUMoxieState *env, uint32_t a, uint32_t b)
@@ -104,7 +104,7 @@ void helper_debug(CPUMoxieState *env)
CPUState *cs = CPU(moxie_env_get_cpu(env));
cs->exception_index = EXCP_DEBUG;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
#if defined(CONFIG_USER_ONLY)
diff --git a/target-openrisc/exception.c b/target-openrisc/exception.c
index b96f3f8..74652a5 100644
--- a/target-openrisc/exception.c
+++ b/target-openrisc/exception.c
@@ -25,5 +25,5 @@ void QEMU_NORETURN raise_exception(OpenRISCCPU *cpu, uint32_t excp)
CPUState *cs = CPU(cpu);
cs->exception_index = excp;
- cpu_loop_exit(&cpu->env);
+ cpu_loop_exit(cs);
}
diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c
index e3fe6c7..5f7f6f5 100644
--- a/target-openrisc/mmu_helper.c
+++ b/target-openrisc/mmu_helper.c
@@ -52,7 +52,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
cpu_restore_state(env, retaddr);
}
/* Raise Exception. */
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
}
#endif
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index 0ec2615..7ced42d 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -816,7 +816,7 @@ void helper_raise_exception_err(CPUPPCState *env, uint32_t exception,
#endif
cs->exception_index = exception;
env->error_code = error_code;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
void helper_raise_exception(CPUPPCState *env, uint32_t exception)
diff --git a/target-s390x/cc_helper.c b/target-s390x/cc_helper.c
index a6d60bf..d845f20 100644
--- a/target-s390x/cc_helper.c
+++ b/target-s390x/cc_helper.c
@@ -548,7 +548,7 @@ uint32_t HELPER(calc_cc)(CPUS390XState *env, uint32_t cc_op, uint64_t src,
void HELPER(load_psw)(CPUS390XState *env, uint64_t mask, uint64_t addr)
{
load_psw(env, mask, addr);
- cpu_loop_exit(env);
+ cpu_loop_exit(CPU(s390_env_get_cpu(env)));
}
void HELPER(sacf)(CPUS390XState *env, uint64_t a1)
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index 8bd131b..44a5557 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -58,7 +58,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
}
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
}
@@ -970,12 +970,12 @@ static uint32_t mvc_asc(CPUS390XState *env, int64_t l, uint64_t a1,
}
if (mmu_translate(env, a1 & TARGET_PAGE_MASK, 1, mode1, &dest, &flags)) {
- cpu_loop_exit(env);
+ cpu_loop_exit(CPU(s390_env_get_cpu(env)));
}
dest |= a1 & ~TARGET_PAGE_MASK;
if (mmu_translate(env, a2 & TARGET_PAGE_MASK, 0, mode2, &src, &flags)) {
- cpu_loop_exit(env);
+ cpu_loop_exit(CPU(s390_env_get_cpu(env)));
}
src |= a2 & ~TARGET_PAGE_MASK;
diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
index b6bd16f..2b1aa83 100644
--- a/target-s390x/misc_helper.c
+++ b/target-s390x/misc_helper.c
@@ -60,7 +60,7 @@ void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
env->int_pgm_ilen = t = get_ilen(t);
env->psw.addr += 2 * t;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
/* Raise an exception statically from a TB. */
@@ -70,7 +70,7 @@ void HELPER(exception)(CPUS390XState *env, uint32_t excp)
HELPER_LOG("%s: exception %d\n", __func__, excp);
cs->exception_index = excp;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
#ifndef CONFIG_USER_ONLY
@@ -172,7 +172,7 @@ void program_interrupt(CPUS390XState *env, uint32_t code, int ilen)
env->int_pgm_code = code;
env->int_pgm_ilen = ilen;
cs->exception_index = EXCP_PGM;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
}
@@ -509,11 +509,11 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
#if !defined(CONFIG_USER_ONLY)
case SIGP_RESTART:
qemu_system_reset_request();
- cpu_loop_exit(env);
+ cpu_loop_exit(CPU(s390_env_get_cpu(env)));
break;
case SIGP_STOP:
qemu_system_shutdown_request();
- cpu_loop_exit(env);
+ cpu_loop_exit(CPU(s390_env_get_cpu(env)));
break;
#endif
default:
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 6e527cf..271401f 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -52,7 +52,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
if (retaddr) {
cpu_restore_state(env, retaddr);
}
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
}
@@ -77,7 +77,7 @@ static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
if (retaddr) {
cpu_restore_state(env, retaddr);
}
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
void helper_raise_illegal_instruction(CPUSH4State *env)
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index a393ef0..fb5f6ec 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -27,7 +27,7 @@ void helper_raise_exception(CPUSPARCState *env, int tt)
CPUState *cs = CPU(sparc_env_get_cpu(env));
cs->exception_index = tt;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
void helper_debug(CPUSPARCState *env)
@@ -35,7 +35,7 @@ void helper_debug(CPUSPARCState *env)
CPUState *cs = CPU(sparc_env_get_cpu(env));
cs->exception_index = EXCP_DEBUG;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
#ifdef TARGET_SPARC64
@@ -239,6 +239,6 @@ void helper_power_down(CPUSPARCState *env)
cs->exception_index = EXCP_HLT;
env->pc = env->npc;
env->npc = env->pc + 4;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
#endif
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 973fcb6..65ce724 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -2443,7 +2443,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
if (retaddr) {
cpu_restore_state(env, retaddr);
}
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
}
#endif
diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
index 3efc6a8..c2bf834 100644
--- a/target-unicore32/op_helper.c
+++ b/target-unicore32/op_helper.c
@@ -19,7 +19,7 @@ void HELPER(exception)(CPUUniCore32State *env, uint32_t excp)
CPUState *cs = CPU(uc32_env_get_cpu(env));
cs->exception_index = excp;
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
static target_ulong asr_read(CPUUniCore32State *env)
@@ -271,7 +271,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
}
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
}
#endif
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index cc1d5e2..17d7f35 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -104,7 +104,7 @@ void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
if (excp == EXCP_DEBUG) {
env->exception_taken = 0;
}
- cpu_loop_exit(env);
+ cpu_loop_exit(cs);
}
void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
@@ -390,7 +390,7 @@ void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
(intlevel << PS_INTLEVEL_SHIFT);
check_interrupts(env);
if (env->pending_irq_level) {
- cpu_loop_exit(env);
+ cpu_loop_exit(CPU(xtensa_env_get_cpu(env)));
return;
}
diff --git a/user-exec.c b/user-exec.c
index dbb9c8d..e149c97 100644
--- a/user-exec.c
+++ b/user-exec.c
@@ -40,12 +40,12 @@
static void exception_action(CPUArchState *env1)
{
-#if defined(TARGET_I386)
CPUState *cpu = ENV_GET_CPU(env1);
+#if defined(TARGET_I386)
raise_exception_err(env1, cpu->exception_index, env1->error_code);
#else
- cpu_loop_exit(env1);
+ cpu_loop_exit(cpu);
#endif
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 19/41] cpu-exec: Change cpu_loop_exit() argument to CPUState
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 19/41] cpu-exec: Change cpu_loop_exit() " Andreas Färber
@ 2013-09-04 12:49 ` Jia Liu
0 siblings, 0 replies; 68+ messages in thread
From: Jia Liu @ 2013-09-04 12:49 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Anthony Green, qemu-devel@nongnu.org,
Alexander Graf, Blue Swirl, Max Filippov, Michael Walle,
open list:PowerPC, Paul Brook, Edgar E. Iglesias, Guan Xuetao,
Aurelien Jarno, Richard Henderson
On Wed, Sep 4, 2013 at 5:04 PM, Andreas Färber <afaerber@suse.de> wrote:
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
> cpu-exec.c | 14 ++++++--------
> exec.c | 2 +-
> include/exec/exec-all.h | 2 +-
> target-alpha/helper.c | 4 ++--
> target-alpha/mem_helper.c | 4 ++--
> target-arm/op_helper.c | 6 +++---
> target-cris/op_helper.c | 4 ++--
> target-i386/excp_helper.c | 2 +-
> target-i386/misc_helper.c | 4 ++--
> target-i386/seg_helper.c | 2 +-
> target-i386/svm_helper.c | 8 ++++----
> target-lm32/op_helper.c | 6 +++---
> target-m68k/op_helper.c | 6 +++---
> target-microblaze/op_helper.c | 4 ++--
> target-mips/op_helper.c | 4 ++--
> target-moxie/helper.c | 6 +++---
> target-openrisc/exception.c | 2 +-
> target-openrisc/mmu_helper.c | 2 +-
> target-ppc/excp_helper.c | 2 +-
> target-s390x/cc_helper.c | 2 +-
> target-s390x/mem_helper.c | 6 +++---
> target-s390x/misc_helper.c | 10 +++++-----
> target-sh4/op_helper.c | 4 ++--
> target-sparc/helper.c | 6 +++---
> target-sparc/ldst_helper.c | 2 +-
> target-unicore32/op_helper.c | 4 ++--
> target-xtensa/op_helper.c | 4 ++--
> user-exec.c | 4 ++--
> 28 files changed, 62 insertions(+), 64 deletions(-)
>
> diff --git a/cpu-exec.c b/cpu-exec.c
> index 209380d..a1b8b96 100644
> --- a/cpu-exec.c
> +++ b/cpu-exec.c
> @@ -23,10 +23,8 @@
> #include "qemu/atomic.h"
> #include "sysemu/qtest.h"
>
> -void cpu_loop_exit(CPUArchState *env)
> +void cpu_loop_exit(CPUState *cpu)
> {
> - CPUState *cpu = ENV_GET_CPU(env);
> -
> cpu->current_tb = NULL;
> siglongjmp(cpu->jmp_env, 1);
> }
> @@ -305,7 +303,7 @@ int cpu_exec(CPUArchState *env)
> if (interrupt_request & CPU_INTERRUPT_DEBUG) {
> cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
> cpu->exception_index = EXCP_DEBUG;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cpu);
> }
> #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
> defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
> @@ -314,7 +312,7 @@ int cpu_exec(CPUArchState *env)
> cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
> cpu->halted = 1;
> cpu->exception_index = EXCP_HLT;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cpu);
> }
> #endif
> #if defined(TARGET_I386)
> @@ -329,7 +327,7 @@ int cpu_exec(CPUArchState *env)
> 0);
> do_cpu_init(x86_env_get_cpu(env));
> cpu->exception_index = EXCP_HALTED;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cpu);
> } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
> do_cpu_sipi(x86_env_get_cpu(env));
> } else if (env->hflags2 & HF2_GIF_MASK) {
> @@ -578,7 +576,7 @@ int cpu_exec(CPUArchState *env)
> if (unlikely(cpu->exit_request)) {
> cpu->exit_request = 0;
> cpu->exception_index = EXCP_INTERRUPT;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cpu);
> }
> #if defined(DEBUG_DISAS)
> if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
> @@ -665,7 +663,7 @@ int cpu_exec(CPUArchState *env)
> }
> cpu->exception_index = EXCP_INTERRUPT;
> next_tb = 0;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cpu);
> }
> break;
> }
> diff --git a/exec.c b/exec.c
> index 6ae5a21..06fb881 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -1483,7 +1483,7 @@ static void check_watchpoint(int offset, int len_mask, int flags)
> tb_check_watchpoint(env);
> if (wp->flags & BP_STOP_BEFORE_ACCESS) {
> cpu->exception_index = EXCP_DEBUG;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cpu);
> } else {
> cc->get_tb_cpu_state(cpu, &pc, &cs_base, &cpu_flags);
> tb_gen_code(env, pc, cs_base, cpu_flags, 1);
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index 4429924..f6b9eac 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -88,7 +88,7 @@ TranslationBlock *tb_gen_code(CPUArchState *env,
> target_ulong pc, target_ulong cs_base, int flags,
> int cflags);
> void cpu_exec_init(CPUArchState *env);
> -void QEMU_NORETURN cpu_loop_exit(CPUArchState *env1);
> +void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
> int page_unprotect(target_ulong address, uintptr_t pc, void *puc);
> void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
> int is_cpu_write_access);
> diff --git a/target-alpha/helper.c b/target-alpha/helper.c
> index 6f103ec..41a1394 100644
> --- a/target-alpha/helper.c
> +++ b/target-alpha/helper.c
> @@ -512,7 +512,7 @@ void QEMU_NORETURN helper_excp(CPUAlphaState *env, int excp, int error)
>
> cs->exception_index = excp;
> env->error_code = error;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> /* This may be called from any of the helpers to set up EXCEPTION_INDEX. */
> @@ -527,7 +527,7 @@ void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr,
> if (retaddr) {
> cpu_restore_state(env, retaddr);
> }
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> void QEMU_NORETURN arith_excp(CPUAlphaState *env, uintptr_t retaddr,
> diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
> index c6c0182..c2bd64a 100644
> --- a/target-alpha/mem_helper.c
> +++ b/target-alpha/mem_helper.c
> @@ -108,7 +108,7 @@ static void do_unaligned_access(CPUAlphaState *env, target_ulong addr,
> env->trap_arg2 = (insn >> 21) & 31; /* dest regno */
> cs->exception_index = EXCP_UNALIGN;
> env->error_code = 0;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr,
> @@ -158,7 +158,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
> cpu_restore_state(env, retaddr);
> }
> /* Exception index and error code are already set */
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
> }
> #endif /* CONFIG_USER_ONLY */
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index d05f522..552ca3d 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -28,7 +28,7 @@ static void raise_exception(CPUARMState *env, int tt)
> CPUState *cs = CPU(cpu);
>
> cs->exception_index = tt;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
> @@ -229,7 +229,7 @@ void HELPER(wfi)(CPUARMState *env)
>
> cs->exception_index = EXCP_HLT;
> cs->halted = 1;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> void HELPER(exception)(CPUARMState *env, uint32_t excp)
> @@ -237,7 +237,7 @@ void HELPER(exception)(CPUARMState *env, uint32_t excp)
> CPUState *cs = CPU(arm_env_get_cpu(env));
>
> cs->exception_index = excp;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> uint32_t HELPER(cpsr_read)(CPUARMState *env)
> diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
> index 68a5caa..d80b6c9 100644
> --- a/target-cris/op_helper.c
> +++ b/target-cris/op_helper.c
> @@ -72,7 +72,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> helper_top_evaluate_flags(env);
> }
> }
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
> }
>
> @@ -83,7 +83,7 @@ void helper_raise_exception(CPUCRISState *env, uint32_t index)
> CPUState *cs = CPU(cris_env_get_cpu(env));
>
> cs->exception_index = index;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
> diff --git a/target-i386/excp_helper.c b/target-i386/excp_helper.c
> index ec76eba..f337fd2 100644
> --- a/target-i386/excp_helper.c
> +++ b/target-i386/excp_helper.c
> @@ -108,7 +108,7 @@ static void QEMU_NORETURN raise_interrupt2(CPUX86State *env, int intno,
> env->error_code = error_code;
> env->exception_is_int = is_int;
> env->exception_next_eip = env->eip + next_eip_addend;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> /* shortcuts to generate exceptions */
> diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c
> index a058c43..4b7a142 100644
> --- a/target-i386/misc_helper.c
> +++ b/target-i386/misc_helper.c
> @@ -574,7 +574,7 @@ static void do_hlt(X86CPU *cpu)
> env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
> cs->halted = 1;
> cs->exception_index = EXCP_HLT;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> void helper_hlt(CPUX86State *env, int next_eip_addend)
> @@ -623,5 +623,5 @@ void helper_debug(CPUX86State *env)
> CPUState *cs = CPU(x86_env_get_cpu(env));
>
> cs->exception_index = EXCP_DEBUG;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
> diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
> index b689e94..d030793 100644
> --- a/target-i386/seg_helper.c
> +++ b/target-i386/seg_helper.c
> @@ -939,7 +939,7 @@ void helper_syscall(CPUX86State *env, int next_eip_addend)
>
> cs->exception_index = EXCP_SYSCALL;
> env->exception_next_eip = env->eip + next_eip_addend;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
> #else
> void helper_syscall(CPUX86State *env, int next_eip_addend)
> diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
> index 3c12cb8..fbf8359 100644
> --- a/target-i386/svm_helper.c
> +++ b/target-i386/svm_helper.c
> @@ -305,7 +305,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
> env->exception_is_int = 0;
> env->exception_next_eip = env->eip;
> qemu_log_mask(CPU_LOG_TB_IN_ASM, "NMI");
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> break;
> case SVM_EVTINJ_TYPE_EXEPT:
> cs->exception_index = vector;
> @@ -313,7 +313,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
> env->exception_is_int = 0;
> env->exception_next_eip = -1;
> qemu_log_mask(CPU_LOG_TB_IN_ASM, "EXEPT");
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> break;
> case SVM_EVTINJ_TYPE_SOFT:
> cs->exception_index = vector;
> @@ -321,7 +321,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
> env->exception_is_int = 1;
> env->exception_next_eip = env->eip;
> qemu_log_mask(CPU_LOG_TB_IN_ASM, "SOFT");
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> break;
> }
> qemu_log_mask(CPU_LOG_TB_IN_ASM, " %#x %#x\n", cs->exception_index,
> @@ -710,7 +710,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
> env->error_code = 0;
> env->old_exception = -1;
>
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1)
> diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
> index d4ee1ba..acf2412 100644
> --- a/target-lm32/op_helper.c
> +++ b/target-lm32/op_helper.c
> @@ -24,7 +24,7 @@ void HELPER(raise_exception)(CPULM32State *env, uint32_t index)
> CPUState *cs = CPU(lm32_env_get_cpu(env));
>
> cs->exception_index = index;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> void HELPER(hlt)(CPULM32State *env)
> @@ -33,7 +33,7 @@ void HELPER(hlt)(CPULM32State *env)
>
> cs->halted = 1;
> cs->exception_index = EXCP_HLT;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> void HELPER(wcsr_im)(CPULM32State *env, uint32_t im)
> @@ -94,7 +94,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> /* now we have a real cpu fault */
> cpu_restore_state(env, retaddr);
> }
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
> }
> #endif
> diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
> index 9ad3a9d..6ab1927 100644
> --- a/target-m68k/op_helper.c
> +++ b/target-m68k/op_helper.c
> @@ -67,7 +67,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> /* now we have a real cpu fault */
> cpu_restore_state(env, retaddr);
> }
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
> }
>
> @@ -114,7 +114,7 @@ static void do_interrupt_all(CPUM68KState *env, int is_hw)
> }
> cs->halted = 1;
> cs->exception_index = EXCP_HLT;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> return;
> }
> if (cs->exception_index >= EXCP_TRAP0
> @@ -170,7 +170,7 @@ static void raise_exception(CPUM68KState *env, int tt)
> CPUState *cs = CPU(m68k_env_get_cpu(env));
>
> cs->exception_index = tt;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> void HELPER(raise_exception)(CPUM68KState *env, uint32_t tt)
> diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
> index 9e39411..f476132 100644
> --- a/target-microblaze/op_helper.c
> +++ b/target-microblaze/op_helper.c
> @@ -56,7 +56,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> /* now we have a real cpu fault */
> cpu_restore_state(env, retaddr);
> }
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
> }
> #endif
> @@ -101,7 +101,7 @@ void helper_raise_exception(CPUMBState *env, uint32_t index)
> CPUState *cs = CPU(mb_env_get_cpu(env));
>
> cs->exception_index = index;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> void helper_debug(CPUMBState *env)
> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
> index 7208659..0e0c540 100644
> --- a/target-mips/op_helper.c
> +++ b/target-mips/op_helper.c
> @@ -51,7 +51,7 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
> cpu_restore_state(env, pc);
> }
>
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
> @@ -280,7 +280,7 @@ static inline hwaddr do_translate_address(CPUMIPSState *env,
> lladdr = cpu_mips_translate_address(env, address, rw);
>
> if (lladdr == -1LL) {
> - cpu_loop_exit(env);
> + cpu_loop_exit(CPU(mips_env_get_cpu(env)));
> } else {
> return lladdr;
> }
> diff --git a/target-moxie/helper.c b/target-moxie/helper.c
> index 06a4c72..3994c09 100644
> --- a/target-moxie/helper.c
> +++ b/target-moxie/helper.c
> @@ -59,7 +59,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> cpu_restore_state(env, retaddr);
> }
> }
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> void helper_raise_exception(CPUMoxieState *env, int ex)
> @@ -74,7 +74,7 @@ void helper_raise_exception(CPUMoxieState *env, int ex)
> env->sregs[5] = env->pc;
> /* Jump the the exception handline routine. */
> env->pc = env->sregs[1];
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> uint32_t helper_div(CPUMoxieState *env, uint32_t a, uint32_t b)
> @@ -104,7 +104,7 @@ void helper_debug(CPUMoxieState *env)
> CPUState *cs = CPU(moxie_env_get_cpu(env));
>
> cs->exception_index = EXCP_DEBUG;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> #if defined(CONFIG_USER_ONLY)
> diff --git a/target-openrisc/exception.c b/target-openrisc/exception.c
> index b96f3f8..74652a5 100644
> --- a/target-openrisc/exception.c
> +++ b/target-openrisc/exception.c
> @@ -25,5 +25,5 @@ void QEMU_NORETURN raise_exception(OpenRISCCPU *cpu, uint32_t excp)
> CPUState *cs = CPU(cpu);
>
> cs->exception_index = excp;
> - cpu_loop_exit(&cpu->env);
> + cpu_loop_exit(cs);
> }
> diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c
> index e3fe6c7..5f7f6f5 100644
> --- a/target-openrisc/mmu_helper.c
> +++ b/target-openrisc/mmu_helper.c
> @@ -52,7 +52,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
> cpu_restore_state(env, retaddr);
> }
> /* Raise Exception. */
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
> }
> #endif
> diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
> index 0ec2615..7ced42d 100644
> --- a/target-ppc/excp_helper.c
> +++ b/target-ppc/excp_helper.c
> @@ -816,7 +816,7 @@ void helper_raise_exception_err(CPUPPCState *env, uint32_t exception,
> #endif
> cs->exception_index = exception;
> env->error_code = error_code;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> void helper_raise_exception(CPUPPCState *env, uint32_t exception)
> diff --git a/target-s390x/cc_helper.c b/target-s390x/cc_helper.c
> index a6d60bf..d845f20 100644
> --- a/target-s390x/cc_helper.c
> +++ b/target-s390x/cc_helper.c
> @@ -548,7 +548,7 @@ uint32_t HELPER(calc_cc)(CPUS390XState *env, uint32_t cc_op, uint64_t src,
> void HELPER(load_psw)(CPUS390XState *env, uint64_t mask, uint64_t addr)
> {
> load_psw(env, mask, addr);
> - cpu_loop_exit(env);
> + cpu_loop_exit(CPU(s390_env_get_cpu(env)));
> }
>
> void HELPER(sacf)(CPUS390XState *env, uint64_t a1)
> diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
> index 8bd131b..44a5557 100644
> --- a/target-s390x/mem_helper.c
> +++ b/target-s390x/mem_helper.c
> @@ -58,7 +58,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> /* now we have a real cpu fault */
> cpu_restore_state(env, retaddr);
> }
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
> }
>
> @@ -970,12 +970,12 @@ static uint32_t mvc_asc(CPUS390XState *env, int64_t l, uint64_t a1,
> }
>
> if (mmu_translate(env, a1 & TARGET_PAGE_MASK, 1, mode1, &dest, &flags)) {
> - cpu_loop_exit(env);
> + cpu_loop_exit(CPU(s390_env_get_cpu(env)));
> }
> dest |= a1 & ~TARGET_PAGE_MASK;
>
> if (mmu_translate(env, a2 & TARGET_PAGE_MASK, 0, mode2, &src, &flags)) {
> - cpu_loop_exit(env);
> + cpu_loop_exit(CPU(s390_env_get_cpu(env)));
> }
> src |= a2 & ~TARGET_PAGE_MASK;
>
> diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
> index b6bd16f..2b1aa83 100644
> --- a/target-s390x/misc_helper.c
> +++ b/target-s390x/misc_helper.c
> @@ -60,7 +60,7 @@ void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
> env->int_pgm_ilen = t = get_ilen(t);
> env->psw.addr += 2 * t;
>
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> /* Raise an exception statically from a TB. */
> @@ -70,7 +70,7 @@ void HELPER(exception)(CPUS390XState *env, uint32_t excp)
>
> HELPER_LOG("%s: exception %d\n", __func__, excp);
> cs->exception_index = excp;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> #ifndef CONFIG_USER_ONLY
> @@ -172,7 +172,7 @@ void program_interrupt(CPUS390XState *env, uint32_t code, int ilen)
> env->int_pgm_code = code;
> env->int_pgm_ilen = ilen;
> cs->exception_index = EXCP_PGM;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
> }
>
> @@ -509,11 +509,11 @@ uint32_t HELPER(sigp)(CPUS390XState *env, uint64_t order_code, uint32_t r1,
> #if !defined(CONFIG_USER_ONLY)
> case SIGP_RESTART:
> qemu_system_reset_request();
> - cpu_loop_exit(env);
> + cpu_loop_exit(CPU(s390_env_get_cpu(env)));
> break;
> case SIGP_STOP:
> qemu_system_shutdown_request();
> - cpu_loop_exit(env);
> + cpu_loop_exit(CPU(s390_env_get_cpu(env)));
> break;
> #endif
> default:
> diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
> index 6e527cf..271401f 100644
> --- a/target-sh4/op_helper.c
> +++ b/target-sh4/op_helper.c
> @@ -52,7 +52,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> if (retaddr) {
> cpu_restore_state(env, retaddr);
> }
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
> }
>
> @@ -77,7 +77,7 @@ static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
> if (retaddr) {
> cpu_restore_state(env, retaddr);
> }
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> void helper_raise_illegal_instruction(CPUSH4State *env)
> diff --git a/target-sparc/helper.c b/target-sparc/helper.c
> index a393ef0..fb5f6ec 100644
> --- a/target-sparc/helper.c
> +++ b/target-sparc/helper.c
> @@ -27,7 +27,7 @@ void helper_raise_exception(CPUSPARCState *env, int tt)
> CPUState *cs = CPU(sparc_env_get_cpu(env));
>
> cs->exception_index = tt;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> void helper_debug(CPUSPARCState *env)
> @@ -35,7 +35,7 @@ void helper_debug(CPUSPARCState *env)
> CPUState *cs = CPU(sparc_env_get_cpu(env));
>
> cs->exception_index = EXCP_DEBUG;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> #ifdef TARGET_SPARC64
> @@ -239,6 +239,6 @@ void helper_power_down(CPUSPARCState *env)
> cs->exception_index = EXCP_HLT;
> env->pc = env->npc;
> env->npc = env->pc + 4;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
> #endif
> diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
> index 973fcb6..65ce724 100644
> --- a/target-sparc/ldst_helper.c
> +++ b/target-sparc/ldst_helper.c
> @@ -2443,7 +2443,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> if (retaddr) {
> cpu_restore_state(env, retaddr);
> }
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
> }
> #endif
> diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
> index 3efc6a8..c2bf834 100644
> --- a/target-unicore32/op_helper.c
> +++ b/target-unicore32/op_helper.c
> @@ -19,7 +19,7 @@ void HELPER(exception)(CPUUniCore32State *env, uint32_t excp)
> CPUState *cs = CPU(uc32_env_get_cpu(env));
>
> cs->exception_index = excp;
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> static target_ulong asr_read(CPUUniCore32State *env)
> @@ -271,7 +271,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
> /* now we have a real cpu fault */
> cpu_restore_state(env, retaddr);
> }
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
> }
> #endif
> diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
> index cc1d5e2..17d7f35 100644
> --- a/target-xtensa/op_helper.c
> +++ b/target-xtensa/op_helper.c
> @@ -104,7 +104,7 @@ void HELPER(exception)(CPUXtensaState *env, uint32_t excp)
> if (excp == EXCP_DEBUG) {
> env->exception_taken = 0;
> }
> - cpu_loop_exit(env);
> + cpu_loop_exit(cs);
> }
>
> void HELPER(exception_cause)(CPUXtensaState *env, uint32_t pc, uint32_t cause)
> @@ -390,7 +390,7 @@ void HELPER(waiti)(CPUXtensaState *env, uint32_t pc, uint32_t intlevel)
> (intlevel << PS_INTLEVEL_SHIFT);
> check_interrupts(env);
> if (env->pending_irq_level) {
> - cpu_loop_exit(env);
> + cpu_loop_exit(CPU(xtensa_env_get_cpu(env)));
> return;
> }
>
> diff --git a/user-exec.c b/user-exec.c
> index dbb9c8d..e149c97 100644
> --- a/user-exec.c
> +++ b/user-exec.c
> @@ -40,12 +40,12 @@
>
> static void exception_action(CPUArchState *env1)
> {
> -#if defined(TARGET_I386)
> CPUState *cpu = ENV_GET_CPU(env1);
>
> +#if defined(TARGET_I386)
> raise_exception_err(env1, cpu->exception_index, env1->error_code);
> #else
> - cpu_loop_exit(env1);
> + cpu_loop_exit(cpu);
> #endif
> }
target-openrisc: Tested-by: Jia Liu <proljc@gmail.com>
>
> --
> 1.8.1.4
>
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [RFC qom-cpu 20/41] translate-all: Change cpu_restore_state() argument to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (18 preceding siblings ...)
2013-09-04 9:04 ` [Qemu-devel] [RFC qom-cpu 19/41] cpu-exec: Change cpu_loop_exit() " Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 12:49 ` Jia Liu
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 21/41] translate-all: Change cpu_restore_state_from_tb() " Andreas Färber
` (23 subsequent siblings)
43 siblings, 1 reply; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Anthony Green, Alexander Graf, Blue Swirl,
Max Filippov, Michael Walle, open list:PowerPC, Paul Brook,
Edgar E. Iglesias, Guan Xuetao, Andreas Färber,
Aurelien Jarno, Richard Henderson
This lets us drop some local variables in tlb_fill() functions.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
hw/i386/kvmvapic.c | 2 +-
include/exec/exec-all.h | 2 +-
target-alpha/helper.c | 2 +-
target-alpha/mem_helper.c | 7 ++-----
target-arm/op_helper.c | 2 +-
target-cris/op_helper.c | 2 +-
target-i386/helper.c | 2 +-
target-i386/mem_helper.c | 2 +-
target-lm32/op_helper.c | 5 +----
target-m68k/op_helper.c | 5 +----
target-microblaze/op_helper.c | 5 +----
target-mips/op_helper.c | 2 +-
target-moxie/helper.c | 6 ++----
target-openrisc/mmu_helper.c | 5 +----
target-ppc/mmu_helper.c | 2 +-
target-s390x/mem_helper.c | 5 +----
target-s390x/misc_helper.c | 2 +-
target-sh4/op_helper.c | 7 ++-----
target-sparc/helper.c | 12 ++++++------
target-sparc/ldst_helper.c | 7 ++-----
target-unicore32/op_helper.c | 5 +----
target-xtensa/op_helper.c | 4 ++--
translate-all.c | 3 ++-
user-exec.c | 2 +-
24 files changed, 35 insertions(+), 63 deletions(-)
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index 01e1117..5757a1b 100644
--- a/hw/i386/kvmvapic.c
+++ b/hw/i386/kvmvapic.c
@@ -408,7 +408,7 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
if (!kvm_enabled()) {
CPUClass *cc = CPU_GET_CLASS(cs);
- cpu_restore_state(env, cs->mem_io_pc);
+ cpu_restore_state(cs, cs->mem_io_pc);
cc->get_tb_cpu_state(cs, ¤t_pc, ¤t_cs_base,
¤t_flags);
}
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index f6b9eac..c25951c 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -80,7 +80,7 @@ void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
void cpu_gen_init(void);
int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb,
int *gen_code_size_ptr);
-bool cpu_restore_state(CPUArchState *env, uintptr_t searched_pc);
+bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc);
void QEMU_NORETURN cpu_io_recompile(CPUArchState *env, uintptr_t retaddr);
diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index 41a1394..f0ba5dd 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -525,7 +525,7 @@ void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr,
cs->exception_index = excp;
env->error_code = error;
if (retaddr) {
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(cs, retaddr);
}
cpu_loop_exit(cs);
}
diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
index c2bd64a..a807aa0 100644
--- a/target-alpha/mem_helper.c
+++ b/target-alpha/mem_helper.c
@@ -97,7 +97,7 @@ static void do_unaligned_access(CPUAlphaState *env, target_ulong addr,
uint32_t insn;
if (retaddr) {
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(cs, retaddr);
}
pc = env->pc;
@@ -151,11 +151,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
ret = alpha_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret != 0)) {
- AlphaCPU *cpu = ALPHA_CPU(cs);
- CPUAlphaState *env = &cpu->env;
-
if (retaddr) {
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(cs, retaddr);
}
/* Exception index and error code are already set */
cpu_loop_exit(cs);
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 552ca3d..7bd698c 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -87,7 +87,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
if (retaddr) {
/* now we have a real cpu fault */
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(cs, retaddr);
}
raise_exception(env, cs->exception_index);
}
diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
index d80b6c9..d28bd61 100644
--- a/target-cris/op_helper.c
+++ b/target-cris/op_helper.c
@@ -67,7 +67,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
if (unlikely(ret)) {
if (retaddr) {
/* now we have a real cpu fault */
- if (cpu_restore_state(env, retaddr)) {
+ if (cpu_restore_state(cs, retaddr)) {
/* Evaluate flags after retranslation. */
helper_top_evaluate_flags(env);
}
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 557c94f..c571589 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -1258,7 +1258,7 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access)
cpu_interrupt(cs, CPU_INTERRUPT_TPR);
} else {
- cpu_restore_state(env, cs->mem_io_pc);
+ cpu_restore_state(cs, cs->mem_io_pc);
apic_handle_tpr_access_report(env->apic_state, env->eip, access);
}
diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c
index 2f0691b..b3b811b 100644
--- a/target-i386/mem_helper.c
+++ b/target-i386/mem_helper.c
@@ -145,7 +145,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
if (retaddr) {
/* now we have a real cpu fault */
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(cs, retaddr);
}
raise_exception_err(env, cs->exception_index, env->error_code);
}
diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
index acf2412..59877ac 100644
--- a/target-lm32/op_helper.c
+++ b/target-lm32/op_helper.c
@@ -87,12 +87,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
ret = lm32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret)) {
- LM32CPU *cpu = LM32_CPU(cs);
- CPULM32State *env = &cpu->env;
-
if (retaddr) {
/* now we have a real cpu fault */
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(cs, retaddr);
}
cpu_loop_exit(cs);
}
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
index 6ab1927..59cb33d 100644
--- a/target-m68k/op_helper.c
+++ b/target-m68k/op_helper.c
@@ -60,12 +60,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
ret = m68k_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret)) {
- M68kCPU *cpu = M68K_CPU(cs);
- CPUM68KState *env = &cpu->env;
-
if (retaddr) {
/* now we have a real cpu fault */
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(cs, retaddr);
}
cpu_loop_exit(cs);
}
diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index f476132..f8fb7f9 100644
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -49,12 +49,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret)) {
- MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
- CPUMBState *env = &cpu->env;
-
if (retaddr) {
/* now we have a real cpu fault */
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(cs, retaddr);
}
cpu_loop_exit(cs);
}
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 0e0c540..dc0c1cc 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -48,7 +48,7 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
if (pc) {
/* now we have a real cpu fault */
- cpu_restore_state(env, pc);
+ cpu_restore_state(cs, pc);
}
cpu_loop_exit(cs);
diff --git a/target-moxie/helper.c b/target-moxie/helper.c
index 3994c09..04b36b7 100644
--- a/target-moxie/helper.c
+++ b/target-moxie/helper.c
@@ -49,14 +49,12 @@
void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
uintptr_t retaddr)
{
- MoxieCPU *cpu = MOXIE_CPU(cs);
- CPUMoxieState *env = &cpu->env;
int ret;
ret = moxie_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret)) {
if (retaddr) {
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(cs, retaddr);
}
}
cpu_loop_exit(cs);
@@ -70,7 +68,7 @@ void helper_raise_exception(CPUMoxieState *env, int ex)
/* Stash the exception type. */
env->sregs[2] = ex;
/* Stash the address where the exception occurred. */
- cpu_restore_state(env, GETPC());
+ cpu_restore_state(cs, GETPC());
env->sregs[5] = env->pc;
/* Jump the the exception handline routine. */
env->pc = env->sregs[1];
diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c
index 5f7f6f5..fb457c7 100644
--- a/target-openrisc/mmu_helper.c
+++ b/target-openrisc/mmu_helper.c
@@ -44,12 +44,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
ret = openrisc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (ret) {
- OpenRISCCPU *cpu = OPENRISC_CPU(cs);
- CPUOpenRISCState *env = &cpu->env;
-
if (retaddr) {
/* now we have a real cpu fault. */
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(cs, retaddr);
}
/* Raise Exception. */
cpu_loop_exit(cs);
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index cc31482..e214316 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -2908,7 +2908,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
if (unlikely(ret != 0)) {
if (likely(retaddr)) {
/* now we have a real cpu fault */
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(cs, retaddr);
}
helper_raise_exception_err(env, cs->exception_index, env->error_code);
}
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index 44a5557..6a79385 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -51,12 +51,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
ret = s390_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret != 0)) {
- S390CPU *cpu = S390_CPU(cs);
- CPUS390XState *env = &cpu->env;
-
if (likely(retaddr)) {
/* now we have a real cpu fault */
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(cs, retaddr);
}
cpu_loop_exit(cs);
}
diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
index 2b1aa83..54e6d36 100644
--- a/target-s390x/misc_helper.c
+++ b/target-s390x/misc_helper.c
@@ -53,7 +53,7 @@ void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
env->int_pgm_code = excp;
/* Use the (ultimate) callers address to find the insn that trapped. */
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(cs, retaddr);
/* Advance past the insn. */
t = cpu_ldub_code(env, env->psw.addr);
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index 271401f..b3ce7ba 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -46,11 +46,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
ret = superh_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (ret) {
/* now we have a real cpu fault */
- SuperHCPU *cpu = SUPERH_CPU(cs);
- CPUSH4State *env = &cpu->env;
-
if (retaddr) {
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(cs, retaddr);
}
cpu_loop_exit(cs);
}
@@ -75,7 +72,7 @@ static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
cs->exception_index = index;
if (retaddr) {
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(cs, retaddr);
}
cpu_loop_exit(cs);
}
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index fb5f6ec..8d1b72d 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -79,7 +79,7 @@ static target_ulong helper_udiv_common(CPUSPARCState *env, target_ulong a,
x1 = (b & 0xffffffff);
if (x1 == 0) {
- cpu_restore_state(env, GETPC());
+ cpu_restore_state(ENV_GET_CPU(env), GETPC());
helper_raise_exception(env, TT_DIV_ZERO);
}
@@ -118,7 +118,7 @@ static target_ulong helper_sdiv_common(CPUSPARCState *env, target_ulong a,
x1 = (b & 0xffffffff);
if (x1 == 0) {
- cpu_restore_state(env, GETPC());
+ cpu_restore_state(ENV_GET_CPU(env), GETPC());
helper_raise_exception(env, TT_DIV_ZERO);
}
@@ -151,7 +151,7 @@ int64_t helper_sdivx(CPUSPARCState *env, int64_t a, int64_t b)
{
if (b == 0) {
/* Raise divide by zero trap. */
- cpu_restore_state(env, GETPC());
+ cpu_restore_state(ENV_GET_CPU(env), GETPC());
helper_raise_exception(env, TT_DIV_ZERO);
} else if (b == -1) {
/* Avoid overflow trap with i386 divide insn. */
@@ -165,7 +165,7 @@ uint64_t helper_udivx(CPUSPARCState *env, uint64_t a, uint64_t b)
{
if (b == 0) {
/* Raise divide by zero trap. */
- cpu_restore_state(env, GETPC());
+ cpu_restore_state(ENV_GET_CPU(env), GETPC());
helper_raise_exception(env, TT_DIV_ZERO);
}
return a / b;
@@ -197,7 +197,7 @@ target_ulong helper_taddcctv(CPUSPARCState *env, target_ulong src1,
return dst;
tag_overflow:
- cpu_restore_state(env, GETPC());
+ cpu_restore_state(ENV_GET_CPU(env), GETPC());
helper_raise_exception(env, TT_TOVF);
}
@@ -226,7 +226,7 @@ target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1,
return dst;
tag_overflow:
- cpu_restore_state(env, GETPC());
+ cpu_restore_state(ENV_GET_CPU(env), GETPC());
helper_raise_exception(env, TT_TOVF);
}
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 65ce724..b222dff 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -2421,7 +2421,7 @@ static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env,
"\n", addr, env->pc);
#endif
if (retaddr) {
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(ENV_GET_CPU(env), retaddr);
}
helper_raise_exception(env, TT_UNALIGNED);
}
@@ -2437,11 +2437,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
ret = sparc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (ret) {
- SPARCCPU *cpu = SPARC_CPU(cs);
- CPUSPARCState *env = &cpu->env;
-
if (retaddr) {
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(cs, retaddr);
}
cpu_loop_exit(cs);
}
diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
index c2bf834..4c6950d 100644
--- a/target-unicore32/op_helper.c
+++ b/target-unicore32/op_helper.c
@@ -264,12 +264,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
ret = uc32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
if (unlikely(ret)) {
- UniCore32CPU *cpu = UNICORE32_CPU(cs);
- CPUUniCore32State *env = &cpu->env;
-
if (retaddr) {
/* now we have a real cpu fault */
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(cs, retaddr);
}
cpu_loop_exit(cs);
}
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 17d7f35..24f7579 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -53,7 +53,7 @@ static void do_unaligned_access(CPUXtensaState *env,
{
if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) &&
!xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) {
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(ENV_GET_CPU(env), retaddr);
HELPER(exception_cause_vaddr)(env,
env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
}
@@ -79,7 +79,7 @@ void tlb_fill(CPUState *cs,
paddr & TARGET_PAGE_MASK,
access, mmu_idx, page_size);
} else {
- cpu_restore_state(env, retaddr);
+ cpu_restore_state(cs, retaddr);
HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr);
}
}
diff --git a/translate-all.c b/translate-all.c
index ef34936..5673420 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -249,8 +249,9 @@ static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env,
return 0;
}
-bool cpu_restore_state(CPUArchState *env, uintptr_t retaddr)
+bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr)
{
+ CPUArchState *env = cpu->env_ptr;
TranslationBlock *tb;
tb = tb_find_pc(retaddr);
diff --git a/user-exec.c b/user-exec.c
index e149c97..75c6d54 100644
--- a/user-exec.c
+++ b/user-exec.c
@@ -117,7 +117,7 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
return 1; /* the MMU fault was handled without causing real CPU fault */
}
/* now we have a real cpu fault */
- cpu_restore_state(env, pc);
+ cpu_restore_state(cpu, pc);
/* we restore the process signal mask as the sigreturn should
do it (XXX: use sigsetjmp) */
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 20/41] translate-all: Change cpu_restore_state() argument to CPUState
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 20/41] translate-all: Change cpu_restore_state() " Andreas Färber
@ 2013-09-04 12:49 ` Jia Liu
0 siblings, 0 replies; 68+ messages in thread
From: Jia Liu @ 2013-09-04 12:49 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Anthony Green, qemu-devel@nongnu.org,
Alexander Graf, Blue Swirl, Max Filippov, Michael Walle,
open list:PowerPC, Paul Brook, Edgar E. Iglesias, Guan Xuetao,
Aurelien Jarno, Richard Henderson
On Wed, Sep 4, 2013 at 5:05 PM, Andreas Färber <afaerber@suse.de> wrote:
> This lets us drop some local variables in tlb_fill() functions.
>
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
> hw/i386/kvmvapic.c | 2 +-
> include/exec/exec-all.h | 2 +-
> target-alpha/helper.c | 2 +-
> target-alpha/mem_helper.c | 7 ++-----
> target-arm/op_helper.c | 2 +-
> target-cris/op_helper.c | 2 +-
> target-i386/helper.c | 2 +-
> target-i386/mem_helper.c | 2 +-
> target-lm32/op_helper.c | 5 +----
> target-m68k/op_helper.c | 5 +----
> target-microblaze/op_helper.c | 5 +----
> target-mips/op_helper.c | 2 +-
> target-moxie/helper.c | 6 ++----
> target-openrisc/mmu_helper.c | 5 +----
> target-ppc/mmu_helper.c | 2 +-
> target-s390x/mem_helper.c | 5 +----
> target-s390x/misc_helper.c | 2 +-
> target-sh4/op_helper.c | 7 ++-----
> target-sparc/helper.c | 12 ++++++------
> target-sparc/ldst_helper.c | 7 ++-----
> target-unicore32/op_helper.c | 5 +----
> target-xtensa/op_helper.c | 4 ++--
> translate-all.c | 3 ++-
> user-exec.c | 2 +-
> 24 files changed, 35 insertions(+), 63 deletions(-)
>
> diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
> index 01e1117..5757a1b 100644
> --- a/hw/i386/kvmvapic.c
> +++ b/hw/i386/kvmvapic.c
> @@ -408,7 +408,7 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
> if (!kvm_enabled()) {
> CPUClass *cc = CPU_GET_CLASS(cs);
>
> - cpu_restore_state(env, cs->mem_io_pc);
> + cpu_restore_state(cs, cs->mem_io_pc);
> cc->get_tb_cpu_state(cs, ¤t_pc, ¤t_cs_base,
> ¤t_flags);
> }
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index f6b9eac..c25951c 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -80,7 +80,7 @@ void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
> void cpu_gen_init(void);
> int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb,
> int *gen_code_size_ptr);
> -bool cpu_restore_state(CPUArchState *env, uintptr_t searched_pc);
> +bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
>
> void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc);
> void QEMU_NORETURN cpu_io_recompile(CPUArchState *env, uintptr_t retaddr);
> diff --git a/target-alpha/helper.c b/target-alpha/helper.c
> index 41a1394..f0ba5dd 100644
> --- a/target-alpha/helper.c
> +++ b/target-alpha/helper.c
> @@ -525,7 +525,7 @@ void QEMU_NORETURN dynamic_excp(CPUAlphaState *env, uintptr_t retaddr,
> cs->exception_index = excp;
> env->error_code = error;
> if (retaddr) {
> - cpu_restore_state(env, retaddr);
> + cpu_restore_state(cs, retaddr);
> }
> cpu_loop_exit(cs);
> }
> diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c
> index c2bd64a..a807aa0 100644
> --- a/target-alpha/mem_helper.c
> +++ b/target-alpha/mem_helper.c
> @@ -97,7 +97,7 @@ static void do_unaligned_access(CPUAlphaState *env, target_ulong addr,
> uint32_t insn;
>
> if (retaddr) {
> - cpu_restore_state(env, retaddr);
> + cpu_restore_state(cs, retaddr);
> }
>
> pc = env->pc;
> @@ -151,11 +151,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
>
> ret = alpha_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (unlikely(ret != 0)) {
> - AlphaCPU *cpu = ALPHA_CPU(cs);
> - CPUAlphaState *env = &cpu->env;
> -
> if (retaddr) {
> - cpu_restore_state(env, retaddr);
> + cpu_restore_state(cs, retaddr);
> }
> /* Exception index and error code are already set */
> cpu_loop_exit(cs);
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index 552ca3d..7bd698c 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -87,7 +87,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
>
> if (retaddr) {
> /* now we have a real cpu fault */
> - cpu_restore_state(env, retaddr);
> + cpu_restore_state(cs, retaddr);
> }
> raise_exception(env, cs->exception_index);
> }
> diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
> index d80b6c9..d28bd61 100644
> --- a/target-cris/op_helper.c
> +++ b/target-cris/op_helper.c
> @@ -67,7 +67,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> if (unlikely(ret)) {
> if (retaddr) {
> /* now we have a real cpu fault */
> - if (cpu_restore_state(env, retaddr)) {
> + if (cpu_restore_state(cs, retaddr)) {
> /* Evaluate flags after retranslation. */
> helper_top_evaluate_flags(env);
> }
> diff --git a/target-i386/helper.c b/target-i386/helper.c
> index 557c94f..c571589 100644
> --- a/target-i386/helper.c
> +++ b/target-i386/helper.c
> @@ -1258,7 +1258,7 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access)
>
> cpu_interrupt(cs, CPU_INTERRUPT_TPR);
> } else {
> - cpu_restore_state(env, cs->mem_io_pc);
> + cpu_restore_state(cs, cs->mem_io_pc);
>
> apic_handle_tpr_access_report(env->apic_state, env->eip, access);
> }
> diff --git a/target-i386/mem_helper.c b/target-i386/mem_helper.c
> index 2f0691b..b3b811b 100644
> --- a/target-i386/mem_helper.c
> +++ b/target-i386/mem_helper.c
> @@ -145,7 +145,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
>
> if (retaddr) {
> /* now we have a real cpu fault */
> - cpu_restore_state(env, retaddr);
> + cpu_restore_state(cs, retaddr);
> }
> raise_exception_err(env, cs->exception_index, env->error_code);
> }
> diff --git a/target-lm32/op_helper.c b/target-lm32/op_helper.c
> index acf2412..59877ac 100644
> --- a/target-lm32/op_helper.c
> +++ b/target-lm32/op_helper.c
> @@ -87,12 +87,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
>
> ret = lm32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> - LM32CPU *cpu = LM32_CPU(cs);
> - CPULM32State *env = &cpu->env;
> -
> if (retaddr) {
> /* now we have a real cpu fault */
> - cpu_restore_state(env, retaddr);
> + cpu_restore_state(cs, retaddr);
> }
> cpu_loop_exit(cs);
> }
> diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
> index 6ab1927..59cb33d 100644
> --- a/target-m68k/op_helper.c
> +++ b/target-m68k/op_helper.c
> @@ -60,12 +60,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
>
> ret = m68k_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> - M68kCPU *cpu = M68K_CPU(cs);
> - CPUM68KState *env = &cpu->env;
> -
> if (retaddr) {
> /* now we have a real cpu fault */
> - cpu_restore_state(env, retaddr);
> + cpu_restore_state(cs, retaddr);
> }
> cpu_loop_exit(cs);
> }
> diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
> index f476132..f8fb7f9 100644
> --- a/target-microblaze/op_helper.c
> +++ b/target-microblaze/op_helper.c
> @@ -49,12 +49,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
>
> ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> - MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
> - CPUMBState *env = &cpu->env;
> -
> if (retaddr) {
> /* now we have a real cpu fault */
> - cpu_restore_state(env, retaddr);
> + cpu_restore_state(cs, retaddr);
> }
> cpu_loop_exit(cs);
> }
> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
> index 0e0c540..dc0c1cc 100644
> --- a/target-mips/op_helper.c
> +++ b/target-mips/op_helper.c
> @@ -48,7 +48,7 @@ static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
>
> if (pc) {
> /* now we have a real cpu fault */
> - cpu_restore_state(env, pc);
> + cpu_restore_state(cs, pc);
> }
>
> cpu_loop_exit(cs);
> diff --git a/target-moxie/helper.c b/target-moxie/helper.c
> index 3994c09..04b36b7 100644
> --- a/target-moxie/helper.c
> +++ b/target-moxie/helper.c
> @@ -49,14 +49,12 @@
> void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> uintptr_t retaddr)
> {
> - MoxieCPU *cpu = MOXIE_CPU(cs);
> - CPUMoxieState *env = &cpu->env;
> int ret;
>
> ret = moxie_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> if (retaddr) {
> - cpu_restore_state(env, retaddr);
> + cpu_restore_state(cs, retaddr);
> }
> }
> cpu_loop_exit(cs);
> @@ -70,7 +68,7 @@ void helper_raise_exception(CPUMoxieState *env, int ex)
> /* Stash the exception type. */
> env->sregs[2] = ex;
> /* Stash the address where the exception occurred. */
> - cpu_restore_state(env, GETPC());
> + cpu_restore_state(cs, GETPC());
> env->sregs[5] = env->pc;
> /* Jump the the exception handline routine. */
> env->pc = env->sregs[1];
> diff --git a/target-openrisc/mmu_helper.c b/target-openrisc/mmu_helper.c
> index 5f7f6f5..fb457c7 100644
> --- a/target-openrisc/mmu_helper.c
> +++ b/target-openrisc/mmu_helper.c
> @@ -44,12 +44,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
> ret = openrisc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
>
> if (ret) {
> - OpenRISCCPU *cpu = OPENRISC_CPU(cs);
> - CPUOpenRISCState *env = &cpu->env;
> -
> if (retaddr) {
> /* now we have a real cpu fault. */
> - cpu_restore_state(env, retaddr);
> + cpu_restore_state(cs, retaddr);
> }
> /* Raise Exception. */
> cpu_loop_exit(cs);
> diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
> index cc31482..e214316 100644
> --- a/target-ppc/mmu_helper.c
> +++ b/target-ppc/mmu_helper.c
> @@ -2908,7 +2908,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> if (unlikely(ret != 0)) {
> if (likely(retaddr)) {
> /* now we have a real cpu fault */
> - cpu_restore_state(env, retaddr);
> + cpu_restore_state(cs, retaddr);
> }
> helper_raise_exception_err(env, cs->exception_index, env->error_code);
> }
> diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
> index 44a5557..6a79385 100644
> --- a/target-s390x/mem_helper.c
> +++ b/target-s390x/mem_helper.c
> @@ -51,12 +51,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
>
> ret = s390_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (unlikely(ret != 0)) {
> - S390CPU *cpu = S390_CPU(cs);
> - CPUS390XState *env = &cpu->env;
> -
> if (likely(retaddr)) {
> /* now we have a real cpu fault */
> - cpu_restore_state(env, retaddr);
> + cpu_restore_state(cs, retaddr);
> }
> cpu_loop_exit(cs);
> }
> diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
> index 2b1aa83..54e6d36 100644
> --- a/target-s390x/misc_helper.c
> +++ b/target-s390x/misc_helper.c
> @@ -53,7 +53,7 @@ void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
> env->int_pgm_code = excp;
>
> /* Use the (ultimate) callers address to find the insn that trapped. */
> - cpu_restore_state(env, retaddr);
> + cpu_restore_state(cs, retaddr);
>
> /* Advance past the insn. */
> t = cpu_ldub_code(env, env->psw.addr);
> diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
> index 271401f..b3ce7ba 100644
> --- a/target-sh4/op_helper.c
> +++ b/target-sh4/op_helper.c
> @@ -46,11 +46,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> ret = superh_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (ret) {
> /* now we have a real cpu fault */
> - SuperHCPU *cpu = SUPERH_CPU(cs);
> - CPUSH4State *env = &cpu->env;
> -
> if (retaddr) {
> - cpu_restore_state(env, retaddr);
> + cpu_restore_state(cs, retaddr);
> }
> cpu_loop_exit(cs);
> }
> @@ -75,7 +72,7 @@ static inline void QEMU_NORETURN raise_exception(CPUSH4State *env, int index,
>
> cs->exception_index = index;
> if (retaddr) {
> - cpu_restore_state(env, retaddr);
> + cpu_restore_state(cs, retaddr);
> }
> cpu_loop_exit(cs);
> }
> diff --git a/target-sparc/helper.c b/target-sparc/helper.c
> index fb5f6ec..8d1b72d 100644
> --- a/target-sparc/helper.c
> +++ b/target-sparc/helper.c
> @@ -79,7 +79,7 @@ static target_ulong helper_udiv_common(CPUSPARCState *env, target_ulong a,
> x1 = (b & 0xffffffff);
>
> if (x1 == 0) {
> - cpu_restore_state(env, GETPC());
> + cpu_restore_state(ENV_GET_CPU(env), GETPC());
> helper_raise_exception(env, TT_DIV_ZERO);
> }
>
> @@ -118,7 +118,7 @@ static target_ulong helper_sdiv_common(CPUSPARCState *env, target_ulong a,
> x1 = (b & 0xffffffff);
>
> if (x1 == 0) {
> - cpu_restore_state(env, GETPC());
> + cpu_restore_state(ENV_GET_CPU(env), GETPC());
> helper_raise_exception(env, TT_DIV_ZERO);
> }
>
> @@ -151,7 +151,7 @@ int64_t helper_sdivx(CPUSPARCState *env, int64_t a, int64_t b)
> {
> if (b == 0) {
> /* Raise divide by zero trap. */
> - cpu_restore_state(env, GETPC());
> + cpu_restore_state(ENV_GET_CPU(env), GETPC());
> helper_raise_exception(env, TT_DIV_ZERO);
> } else if (b == -1) {
> /* Avoid overflow trap with i386 divide insn. */
> @@ -165,7 +165,7 @@ uint64_t helper_udivx(CPUSPARCState *env, uint64_t a, uint64_t b)
> {
> if (b == 0) {
> /* Raise divide by zero trap. */
> - cpu_restore_state(env, GETPC());
> + cpu_restore_state(ENV_GET_CPU(env), GETPC());
> helper_raise_exception(env, TT_DIV_ZERO);
> }
> return a / b;
> @@ -197,7 +197,7 @@ target_ulong helper_taddcctv(CPUSPARCState *env, target_ulong src1,
> return dst;
>
> tag_overflow:
> - cpu_restore_state(env, GETPC());
> + cpu_restore_state(ENV_GET_CPU(env), GETPC());
> helper_raise_exception(env, TT_TOVF);
> }
>
> @@ -226,7 +226,7 @@ target_ulong helper_tsubcctv(CPUSPARCState *env, target_ulong src1,
> return dst;
>
> tag_overflow:
> - cpu_restore_state(env, GETPC());
> + cpu_restore_state(ENV_GET_CPU(env), GETPC());
> helper_raise_exception(env, TT_TOVF);
> }
>
> diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
> index 65ce724..b222dff 100644
> --- a/target-sparc/ldst_helper.c
> +++ b/target-sparc/ldst_helper.c
> @@ -2421,7 +2421,7 @@ static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env,
> "\n", addr, env->pc);
> #endif
> if (retaddr) {
> - cpu_restore_state(env, retaddr);
> + cpu_restore_state(ENV_GET_CPU(env), retaddr);
> }
> helper_raise_exception(env, TT_UNALIGNED);
> }
> @@ -2437,11 +2437,8 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
>
> ret = sparc_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (ret) {
> - SPARCCPU *cpu = SPARC_CPU(cs);
> - CPUSPARCState *env = &cpu->env;
> -
> if (retaddr) {
> - cpu_restore_state(env, retaddr);
> + cpu_restore_state(cs, retaddr);
> }
> cpu_loop_exit(cs);
> }
> diff --git a/target-unicore32/op_helper.c b/target-unicore32/op_helper.c
> index c2bf834..4c6950d 100644
> --- a/target-unicore32/op_helper.c
> +++ b/target-unicore32/op_helper.c
> @@ -264,12 +264,9 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write,
>
> ret = uc32_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
> if (unlikely(ret)) {
> - UniCore32CPU *cpu = UNICORE32_CPU(cs);
> - CPUUniCore32State *env = &cpu->env;
> -
> if (retaddr) {
> /* now we have a real cpu fault */
> - cpu_restore_state(env, retaddr);
> + cpu_restore_state(cs, retaddr);
> }
> cpu_loop_exit(cs);
> }
> diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
> index 17d7f35..24f7579 100644
> --- a/target-xtensa/op_helper.c
> +++ b/target-xtensa/op_helper.c
> @@ -53,7 +53,7 @@ static void do_unaligned_access(CPUXtensaState *env,
> {
> if (xtensa_option_enabled(env->config, XTENSA_OPTION_UNALIGNED_EXCEPTION) &&
> !xtensa_option_enabled(env->config, XTENSA_OPTION_HW_ALIGNMENT)) {
> - cpu_restore_state(env, retaddr);
> + cpu_restore_state(ENV_GET_CPU(env), retaddr);
> HELPER(exception_cause_vaddr)(env,
> env->pc, LOAD_STORE_ALIGNMENT_CAUSE, addr);
> }
> @@ -79,7 +79,7 @@ void tlb_fill(CPUState *cs,
> paddr & TARGET_PAGE_MASK,
> access, mmu_idx, page_size);
> } else {
> - cpu_restore_state(env, retaddr);
> + cpu_restore_state(cs, retaddr);
> HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr);
> }
> }
> diff --git a/translate-all.c b/translate-all.c
> index ef34936..5673420 100644
> --- a/translate-all.c
> +++ b/translate-all.c
> @@ -249,8 +249,9 @@ static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env,
> return 0;
> }
>
> -bool cpu_restore_state(CPUArchState *env, uintptr_t retaddr)
> +bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr)
> {
> + CPUArchState *env = cpu->env_ptr;
> TranslationBlock *tb;
>
> tb = tb_find_pc(retaddr);
> diff --git a/user-exec.c b/user-exec.c
> index e149c97..75c6d54 100644
> --- a/user-exec.c
> +++ b/user-exec.c
> @@ -117,7 +117,7 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
> return 1; /* the MMU fault was handled without causing real CPU fault */
> }
> /* now we have a real cpu fault */
> - cpu_restore_state(env, pc);
> + cpu_restore_state(cpu, pc);
>
> /* we restore the process signal mask as the sigreturn should
> do it (XXX: use sigsetjmp) */
target-openrisc: Tested-by: Jia Liu <proljc@gmail.com>
> --
> 1.8.1.4
>
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [RFC qom-cpu 21/41] translate-all: Change cpu_restore_state_from_tb() argument to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (19 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 20/41] translate-all: Change cpu_restore_state() " Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 22/41] translate-all: Change tb_check_watchpoint() " Andreas Färber
` (22 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
And normalize the argument order.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
translate-all.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/translate-all.c b/translate-all.c
index 5673420..0dd6a60 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -193,10 +193,10 @@ int cpu_gen_code(CPUArchState *env, TranslationBlock *tb, int *gen_code_size_ptr
/* The cpu state corresponding to 'searched_pc' is restored.
*/
-static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env,
+static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
uintptr_t searched_pc)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUArchState *env = cpu->env_ptr;
TCGContext *s = &tcg_ctx;
int j;
uintptr_t tc_ptr;
@@ -251,12 +251,11 @@ static int cpu_restore_state_from_tb(TranslationBlock *tb, CPUArchState *env,
bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr)
{
- CPUArchState *env = cpu->env_ptr;
TranslationBlock *tb;
tb = tb_find_pc(retaddr);
if (tb) {
- cpu_restore_state_from_tb(tb, env, retaddr);
+ cpu_restore_state_from_tb(cpu, tb, retaddr);
return true;
}
return false;
@@ -1074,7 +1073,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
restore the CPU state */
current_tb_modified = 1;
- cpu_restore_state_from_tb(current_tb, env, cpu->mem_io_pc);
+ cpu_restore_state_from_tb(cpu, current_tb, cpu->mem_io_pc);
cc->get_tb_cpu_state(cpu, ¤t_pc, ¤t_cs_base,
¤t_flags);
}
@@ -1195,7 +1194,7 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr,
restore the CPU state */
current_tb_modified = 1;
- cpu_restore_state_from_tb(current_tb, env, pc);
+ cpu_restore_state_from_tb(cpu, current_tb, pc);
cc->get_tb_cpu_state(cpu, ¤t_pc, ¤t_cs_base,
¤t_flags);
}
@@ -1395,7 +1394,7 @@ void tb_check_watchpoint(CPUArchState *env)
cpu_abort(env, "check_watchpoint: could not find TB for pc=%p",
(void *)cpu->mem_io_pc);
}
- cpu_restore_state_from_tb(tb, env, cpu->mem_io_pc);
+ cpu_restore_state_from_tb(cpu, tb, cpu->mem_io_pc);
tb_phys_invalidate(tb, -1);
}
@@ -1447,7 +1446,7 @@ void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr)
(void *)retaddr);
}
n = cpu->icount_decr.u16.low + tb->icount;
- cpu_restore_state_from_tb(tb, env, retaddr);
+ cpu_restore_state_from_tb(cpu, tb, retaddr);
/* Calculate how many instructions had been executed before the fault
occurred. */
n = n - cpu->icount_decr.u16.low;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 22/41] translate-all: Change tb_check_watchpoint() argument to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (20 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 21/41] translate-all: Change cpu_restore_state_from_tb() " Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 23/41] translate-all: Change cpu_io_recompile() " Andreas Färber
` (21 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
exec.c | 2 +-
translate-all.c | 4 ++--
translate-all.h | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/exec.c b/exec.c
index 06fb881..0a81967 100644
--- a/exec.c
+++ b/exec.c
@@ -1480,7 +1480,7 @@ static void check_watchpoint(int offset, int len_mask, int flags)
wp->flags |= BP_WATCHPOINT_HIT;
if (!cpu->watchpoint_hit) {
cpu->watchpoint_hit = wp;
- tb_check_watchpoint(env);
+ tb_check_watchpoint(cpu);
if (wp->flags & BP_STOP_BEFORE_ACCESS) {
cpu->exception_index = EXCP_DEBUG;
cpu_loop_exit(cpu);
diff --git a/translate-all.c b/translate-all.c
index 0dd6a60..22a5b80 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1384,9 +1384,9 @@ void tb_invalidate_phys_addr(hwaddr addr)
}
#endif /* TARGET_HAS_ICE && !defined(CONFIG_USER_ONLY) */
-void tb_check_watchpoint(CPUArchState *env)
+void tb_check_watchpoint(CPUState *cpu)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUArchState *env = cpu->env_ptr;
TranslationBlock *tb;
tb = tb_find_pc(cpu->mem_io_pc);
diff --git a/translate-all.h b/translate-all.h
index 5c38819..78e88d3 100644
--- a/translate-all.h
+++ b/translate-all.h
@@ -29,6 +29,6 @@
/* translate-all.c */
void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len);
void cpu_unlink_tb(CPUState *cpu);
-void tb_check_watchpoint(CPUArchState *env);
+void tb_check_watchpoint(CPUState *cpu);
#endif /* TRANSLATE_ALL_H */
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 23/41] translate-all: Change cpu_io_recompile() argument to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (21 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 22/41] translate-all: Change tb_check_watchpoint() " Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 24/41] translate-all: Change tb_gen_code() " Andreas Färber
` (20 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
include/exec/exec-all.h | 2 +-
include/exec/softmmu_template.h | 4 ++--
translate-all.c | 4 ++--
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index c25951c..40d5931 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -83,7 +83,7 @@ int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb,
bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc);
-void QEMU_NORETURN cpu_io_recompile(CPUArchState *env, uintptr_t retaddr);
+void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
TranslationBlock *tb_gen_code(CPUArchState *env,
target_ulong pc, target_ulong cs_base, int flags,
int cflags);
diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h
index 8dc0901..e424d7e 100644
--- a/include/exec/softmmu_template.h
+++ b/include/exec/softmmu_template.h
@@ -82,7 +82,7 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(CPUArchState *env,
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
cpu->mem_io_pc = retaddr;
if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
- cpu_io_recompile(env, retaddr);
+ cpu_io_recompile(cpu, retaddr);
}
cpu->mem_io_vaddr = addr;
@@ -202,7 +202,7 @@ static inline void glue(io_write, SUFFIX)(CPUArchState *env,
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
if (mr != &io_mem_rom && mr != &io_mem_notdirty && !cpu_can_do_io(cpu)) {
- cpu_io_recompile(env, retaddr);
+ cpu_io_recompile(cpu, retaddr);
}
cpu->mem_io_vaddr = addr;
diff --git a/translate-all.c b/translate-all.c
index 22a5b80..1158681 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1432,9 +1432,9 @@ CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt;
/* in deterministic execution mode, instructions doing device I/Os
must be at the end of the TB */
-void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr)
+void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUArchState *env = cpu->env_ptr;
TranslationBlock *tb;
uint32_t n, cflags;
target_ulong pc, cs_base;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 24/41] translate-all: Change tb_gen_code() argument to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (22 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 23/41] translate-all: Change cpu_io_recompile() " Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 25/41] translate-all: Change tb_flush_jmp_cache() " Andreas Färber
` (19 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cpu-exec.c | 4 ++--
exec.c | 2 +-
hw/i386/kvmvapic.c | 2 +-
include/exec/exec-all.h | 2 +-
translate-all.c | 9 +++++----
5 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index a1b8b96..a984b7c 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -85,7 +85,7 @@ static void cpu_exec_nocache(CPUArchState *env, int max_cycles,
if (max_cycles > CF_COUNT_MASK)
max_cycles = CF_COUNT_MASK;
- tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
+ tb = tb_gen_code(cpu, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
max_cycles);
cpu->current_tb = tb;
/* execute the generated code */
@@ -138,7 +138,7 @@ static TranslationBlock *tb_find_slow(CPUArchState *env,
}
not_found:
/* if no translated code available, then translate it now */
- tb = tb_gen_code(env, pc, cs_base, flags, 0);
+ tb = tb_gen_code(cpu, pc, cs_base, flags, 0);
found:
/* Move the last found TB to the head of the list */
diff --git a/exec.c b/exec.c
index 0a81967..1b5a0cd 100644
--- a/exec.c
+++ b/exec.c
@@ -1486,7 +1486,7 @@ static void check_watchpoint(int offset, int len_mask, int flags)
cpu_loop_exit(cpu);
} else {
cc->get_tb_cpu_state(cpu, &pc, &cs_base, &cpu_flags);
- tb_gen_code(env, pc, cs_base, cpu_flags, 1);
+ tb_gen_code(cpu, pc, cs_base, cpu_flags, 1);
cpu_resume_from_signal(env, NULL);
}
}
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index 5757a1b..bcf8d9d 100644
--- a/hw/i386/kvmvapic.c
+++ b/hw/i386/kvmvapic.c
@@ -450,7 +450,7 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
if (!kvm_enabled()) {
cs->current_tb = NULL;
- tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
+ tb_gen_code(cs, current_pc, current_cs_base, current_flags, 1);
cpu_resume_from_signal(env, NULL);
}
}
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 40d5931..73abf9e 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -84,7 +84,7 @@ bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc);
void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
-TranslationBlock *tb_gen_code(CPUArchState *env,
+TranslationBlock *tb_gen_code(CPUState *cpu,
target_ulong pc, target_ulong cs_base, int flags,
int cflags);
void cpu_exec_init(CPUArchState *env);
diff --git a/translate-all.c b/translate-all.c
index 1158681..6e5bfee 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -933,10 +933,11 @@ static void build_page_bitmap(PageDesc *p)
}
}
-TranslationBlock *tb_gen_code(CPUArchState *env,
+TranslationBlock *tb_gen_code(CPUState *cpu,
target_ulong pc, target_ulong cs_base,
int flags, int cflags)
{
+ CPUArchState *env = cpu->env_ptr;
TranslationBlock *tb;
uint8_t *tc_ptr;
tb_page_addr_t phys_pc, phys_page2;
@@ -1110,7 +1111,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
modifying the memory. It will ensure that it cannot modify
itself */
cpu->current_tb = NULL;
- tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
+ tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1);
cpu_resume_from_signal(env, NULL);
}
#endif
@@ -1209,7 +1210,7 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr,
modifying the memory. It will ensure that it cannot modify
itself */
cpu->current_tb = NULL;
- tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
+ tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1);
if (locked) {
mmap_unlock();
}
@@ -1482,7 +1483,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
tb_phys_invalidate(tb, -1);
/* FIXME: In theory this could raise an exception. In practice
we have already translated the block once so it's probably ok. */
- tb_gen_code(env, pc, cs_base, flags, cflags);
+ tb_gen_code(cpu, pc, cs_base, flags, cflags);
/* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not
the first in the TB) then we end up generating a whole new TB and
repeating the fault, which is horribly inefficient.
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 25/41] translate-all: Change tb_flush_jmp_cache() argument to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (23 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 24/41] translate-all: Change tb_gen_code() " Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 26/41] target-ppc: Use PowerPCCPU in PowerPCCPUClass::handle_mmu_fault hook Andreas Färber
` (18 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cputlb.c | 2 +-
include/exec/cputlb.h | 2 +-
translate-all.c | 3 +--
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index e02663c..3721bfc 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -120,7 +120,7 @@ void tlb_flush_page(CPUArchState *env, target_ulong addr)
tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
}
- tb_flush_jmp_cache(env, addr);
+ tb_flush_jmp_cache(cpu, addr);
}
/* update the TLBs so that writes to code in the virtual page 'addr'
diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h
index e21cb60..e1eb4d9 100644
--- a/include/exec/cputlb.h
+++ b/include/exec/cputlb.h
@@ -31,7 +31,7 @@ void tlb_set_dirty(CPUArchState *env, target_ulong vaddr);
extern int tlb_flush_count;
/* exec.c */
-void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr);
+void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr);
MemoryRegionSection *
address_space_translate_for_iotlb(AddressSpace *as, hwaddr addr, hwaddr *xlat,
diff --git a/translate-all.c b/translate-all.c
index 6e5bfee..2254b9f 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1492,9 +1492,8 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
cpu_resume_from_signal(env, NULL);
}
-void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr)
+void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr)
{
- CPUState *cpu = ENV_GET_CPU(env);
unsigned int i;
/* Discard jump cache entries for any tb which might potentially
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 26/41] target-ppc: Use PowerPCCPU in PowerPCCPUClass::handle_mmu_fault hook
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (24 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 25/41] translate-all: Change tb_flush_jmp_cache() " Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 27/41] exec: Change cpu_watchpoint_{insert, remove{, _by_ref, _all}} argument Andreas Färber
` (17 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel; +Cc: open list:PowerPC, Andreas Färber, Alexander Graf
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-ppc/cpu-qom.h | 8 +++++---
target-ppc/mmu-hash32.c | 5 +++--
target-ppc/mmu-hash32.h | 2 +-
target-ppc/mmu-hash64.c | 5 +++--
target-ppc/mmu-hash64.h | 2 +-
target-ppc/mmu_helper.c | 2 +-
6 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
index f3c710a..c213589 100644
--- a/target-ppc/cpu-qom.h
+++ b/target-ppc/cpu-qom.h
@@ -38,6 +38,8 @@
#define POWERPC_CPU_GET_CLASS(obj) \
OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU)
+typedef struct PowerPCCPU PowerPCCPU;
+
/**
* PowerPCCPUClass:
* @parent_realize: The parent class' realize handler.
@@ -70,7 +72,7 @@ typedef struct PowerPCCPUClass {
void (*init_proc)(CPUPPCState *env);
int (*check_pow)(CPUPPCState *env);
#if defined(CONFIG_SOFTMMU)
- int (*handle_mmu_fault)(CPUPPCState *env, target_ulong eaddr, int rwx,
+ int (*handle_mmu_fault)(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
int mmu_idx);
#endif
} PowerPCCPUClass;
@@ -81,13 +83,13 @@ typedef struct PowerPCCPUClass {
*
* A PowerPC CPU.
*/
-typedef struct PowerPCCPU {
+struct PowerPCCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUPPCState env;
-} PowerPCCPU;
+};
static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
{
diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
index aa87084..6a4d6a8 100644
--- a/target-ppc/mmu-hash32.c
+++ b/target-ppc/mmu-hash32.c
@@ -381,10 +381,11 @@ static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,
return (rpn & ~mask) | (eaddr & mask);
}
-int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx,
+int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
int mmu_idx)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = CPU(cpu);
+ CPUPPCState *env = &cpu->env;
target_ulong sr;
hwaddr pte_offset;
ppc_hash_pte32_t pte;
diff --git a/target-ppc/mmu-hash32.h b/target-ppc/mmu-hash32.h
index 884786b..4a49ceb 100644
--- a/target-ppc/mmu-hash32.h
+++ b/target-ppc/mmu-hash32.h
@@ -5,7 +5,7 @@
hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash);
hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong addr);
-int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
+int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong address, int rw,
int mmu_idx);
/*
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 04dcfb3..82bfa7c 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -396,10 +396,11 @@ static hwaddr ppc_hash64_pte_raddr(ppc_slb_t *slb, ppc_hash_pte64_t pte,
return (rpn & ~mask) | (eaddr & mask);
}
-int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr,
+int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
int rwx, int mmu_idx)
{
- CPUState *cs = CPU(ppc_env_get_cpu(env));
+ CPUState *cs = CPU(cpu);
+ CPUPPCState *env = &cpu->env;
ppc_slb_t *slb;
hwaddr pte_offset;
ppc_hash_pte64_t pte;
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
index 55f5a23..41b0ac4 100644
--- a/target-ppc/mmu-hash64.h
+++ b/target-ppc/mmu-hash64.h
@@ -7,7 +7,7 @@
void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr);
-int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
+int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong address, int rw,
int mmu_idx);
#endif
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index e214316..5a237ce 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -2901,7 +2901,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
int ret;
if (pcc->handle_mmu_fault) {
- ret = pcc->handle_mmu_fault(env, addr, is_write, mmu_idx);
+ ret = pcc->handle_mmu_fault(cpu, addr, is_write, mmu_idx);
} else {
ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, mmu_idx);
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 27/41] exec: Change cpu_watchpoint_{insert, remove{, _by_ref, _all}} argument
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (25 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 26/41] target-ppc: Use PowerPCCPU in PowerPCCPUClass::handle_mmu_fault hook Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 28/41] exec: Change cpu_breakpoint_{insert, " Andreas Färber
` (16 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Max Filippov, Riku Voipio, Andreas Färber
Use CPUState. This lets us drop a few local env usages.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
exec.c | 34 +++++++++++++++++-----------------
gdbstub.c | 17 +++++++++--------
include/exec/cpu-all.h | 6 ------
include/qom/cpu.h | 7 +++++++
linux-user/main.c | 5 +++--
target-i386/cpu.c | 2 +-
target-i386/helper.c | 11 ++++++++---
target-i386/machine.c | 3 ++-
target-xtensa/op_helper.c | 9 ++++++---
9 files changed, 53 insertions(+), 41 deletions(-)
diff --git a/exec.c b/exec.c
index 1b5a0cd..cfd0ecb 100644
--- a/exec.c
+++ b/exec.c
@@ -35,6 +35,7 @@
#include "hw/xen/xen.h"
#include "qemu/timer.h"
#include "qemu/config-file.h"
+#include "qemu/error-report.h"
#include "exec/memory.h"
#include "sysemu/dma.h"
#include "exec/address-spaces.h"
@@ -417,30 +418,30 @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
#endif /* TARGET_HAS_ICE */
#if defined(CONFIG_USER_ONLY)
-void cpu_watchpoint_remove_all(CPUArchState *env, int mask)
+void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
{
}
-int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
+int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
int flags, CPUWatchpoint **watchpoint)
{
return -ENOSYS;
}
#else
/* Add a watchpoint. */
-int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
+int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
int flags, CPUWatchpoint **watchpoint)
{
- CPUState *cpu = ENV_GET_CPU(env);
- target_ulong len_mask = ~(len - 1);
+ CPUArchState *env = cpu->env_ptr;
+ vaddr len_mask = ~(len - 1);
CPUWatchpoint *wp;
/* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */
if ((len & (len - 1)) || (addr & ~len_mask) ||
len == 0 || len > TARGET_PAGE_SIZE) {
- fprintf(stderr, "qemu: tried to set invalid watchpoint at "
- TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len);
+ error_report("tried to set invalid watchpoint at %"
+ VADDR_PRIx ", len=%" VADDR_PRIu, addr, len);
return -EINVAL;
}
wp = g_malloc(sizeof(*wp));
@@ -464,17 +465,16 @@ int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len
}
/* Remove a specific watchpoint. */
-int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len,
+int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
int flags)
{
- CPUState *cpu = ENV_GET_CPU(env);
- target_ulong len_mask = ~(len - 1);
+ vaddr len_mask = ~(len - 1);
CPUWatchpoint *wp;
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
if (addr == wp->vaddr && len_mask == wp->len_mask
&& flags == (wp->flags & ~BP_WATCHPOINT_HIT)) {
- cpu_watchpoint_remove_by_ref(env, wp);
+ cpu_watchpoint_remove_by_ref(cpu, wp);
return 0;
}
}
@@ -482,9 +482,9 @@ int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr, target_ulong len
}
/* Remove a specific watchpoint by reference. */
-void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint)
+void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUArchState *env = cpu->env_ptr;
QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
@@ -494,14 +494,14 @@ void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint)
}
/* Remove all matching watchpoints. */
-void cpu_watchpoint_remove_all(CPUArchState *env, int mask)
+void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
{
- CPUState *cpu = ENV_GET_CPU(env);
CPUWatchpoint *wp, *next;
QTAILQ_FOREACH_SAFE(wp, &cpu->watchpoints, entry, next) {
- if (wp->flags & mask)
- cpu_watchpoint_remove_by_ref(env, wp);
+ if (wp->flags & mask) {
+ cpu_watchpoint_remove_by_ref(cpu, wp);
+ }
}
}
#endif
diff --git a/gdbstub.c b/gdbstub.c
index 05b76e0..1e0dea4 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -660,8 +660,7 @@ static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
case GDB_WATCHPOINT_READ:
case GDB_WATCHPOINT_ACCESS:
CPU_FOREACH(cpu) {
- env = cpu->env_ptr;
- err = cpu_watchpoint_insert(env, addr, len, xlat_gdb_type[type],
+ err = cpu_watchpoint_insert(cpu, addr, len, xlat_gdb_type[type],
NULL);
if (err)
break;
@@ -698,8 +697,7 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
case GDB_WATCHPOINT_READ:
case GDB_WATCHPOINT_ACCESS:
CPU_FOREACH(cpu) {
- env = cpu->env_ptr;
- err = cpu_watchpoint_remove(env, addr, len, xlat_gdb_type[type]);
+ err = cpu_watchpoint_remove(cpu, addr, len, xlat_gdb_type[type]);
if (err)
break;
}
@@ -724,7 +722,7 @@ static void gdb_breakpoint_remove_all(void)
env = cpu->env_ptr;
cpu_breakpoint_remove_all(env, BP_GDB);
#ifndef CONFIG_USER_ONLY
- cpu_watchpoint_remove_all(env, BP_GDB);
+ cpu_watchpoint_remove_all(cpu, BP_GDB);
#endif
}
}
@@ -1598,13 +1596,16 @@ int gdbserver_start(int port)
/* Disable gdb stub for child processes. */
void gdbserver_fork(CPUArchState *env)
{
+ CPUState *cpu = ENV_GET_CPU(env);
GDBState *s = gdbserver_state;
- if (gdbserver_fd < 0 || s->fd < 0)
- return;
+
+ if (gdbserver_fd < 0 || s->fd < 0) {
+ return;
+ }
close(s->fd);
s->fd = -1;
cpu_breakpoint_remove_all(env, BP_GDB);
- cpu_watchpoint_remove_all(env, BP_GDB);
+ cpu_watchpoint_remove_all(cpu, BP_GDB);
}
#else
static int gdb_chr_can_receive(void *opaque)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index a407b50..c3ff709 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -426,12 +426,6 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags);
void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint);
void cpu_breakpoint_remove_all(CPUArchState *env, int mask);
-int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
- int flags, CPUWatchpoint **watchpoint);
-int cpu_watchpoint_remove(CPUArchState *env, target_ulong addr,
- target_ulong len, int flags);
-void cpu_watchpoint_remove_by_ref(CPUArchState *env, CPUWatchpoint *watchpoint);
-void cpu_watchpoint_remove_all(CPUArchState *env, int mask);
#if !defined(CONFIG_USER_ONLY)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 5349805..9ef30d3 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -600,6 +600,13 @@ void qemu_init_vcpu(CPUState *cpu);
*/
void cpu_single_step(CPUState *cpu, int enabled);
+int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
+ int flags, CPUWatchpoint **watchpoint);
+int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
+ vaddr len, int flags);
+void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
+void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
+
#ifdef CONFIG_SOFTMMU
extern const struct VMStateDescription vmstate_cpu_common;
#else
diff --git a/linux-user/main.c b/linux-user/main.c
index 77278c7..6feaa50 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3193,13 +3193,14 @@ CPUArchState *cpu_copy(CPUArchState *env)
{
CPUState *cpu = ENV_GET_CPU(env);
CPUArchState *new_env = cpu_init(cpu_model);
+ CPUState *new_cpu = ENV_GET_CPU(new_env);
#if defined(TARGET_HAS_ICE)
CPUBreakpoint *bp;
CPUWatchpoint *wp;
#endif
/* Reset non arch specific state */
- cpu_reset(ENV_GET_CPU(new_env));
+ cpu_reset(new_cpu);
memcpy(new_env, env, sizeof(CPUArchState));
@@ -3213,7 +3214,7 @@ CPUArchState *cpu_copy(CPUArchState *env)
cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
}
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
- cpu_watchpoint_insert(new_env, wp->vaddr, (~wp->len_mask) + 1,
+ cpu_watchpoint_insert(new_cpu, wp->vaddr, (~wp->len_mask) + 1,
wp->flags, NULL);
}
#endif
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index b8d0c15..b80f75b 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2391,7 +2391,7 @@ static void x86_cpu_reset(CPUState *s)
env->dr[6] = DR6_FIXED_1;
env->dr[7] = DR7_FIXED_1;
cpu_breakpoint_remove_all(env, BP_CPU);
- cpu_watchpoint_remove_all(env, BP_CPU);
+ cpu_watchpoint_remove_all(s, BP_CPU);
#if !defined(CONFIG_USER_ONLY)
/* We hard-wire the BSP to the first CPU. */
diff --git a/target-i386/helper.c b/target-i386/helper.c
index c571589..69cc374 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -988,6 +988,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
void hw_breakpoint_insert(CPUX86State *env, int index)
{
+ CPUState *cs = CPU(x86_env_get_cpu(env));
int type = 0, err = 0;
switch (hw_breakpoint_type(env->dr[7], index)) {
@@ -1009,7 +1010,7 @@ void hw_breakpoint_insert(CPUX86State *env, int index)
}
if (type != 0) {
- err = cpu_watchpoint_insert(env, env->dr[index],
+ err = cpu_watchpoint_insert(cs, env->dr[index],
hw_breakpoint_len(env->dr[7], index),
type, &env->cpu_watchpoint[index]);
}
@@ -1021,8 +1022,12 @@ void hw_breakpoint_insert(CPUX86State *env, int index)
void hw_breakpoint_remove(CPUX86State *env, int index)
{
- if (!env->cpu_breakpoint[index])
+ CPUState *cs;
+
+ if (!env->cpu_breakpoint[index]) {
return;
+ }
+ cs = CPU(x86_env_get_cpu(env));
switch (hw_breakpoint_type(env->dr[7], index)) {
case DR7_TYPE_BP_INST:
if (hw_breakpoint_enabled(env->dr[7], index)) {
@@ -1031,7 +1036,7 @@ void hw_breakpoint_remove(CPUX86State *env, int index)
break;
case DR7_TYPE_DATA_WR:
case DR7_TYPE_DATA_RW:
- cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[index]);
+ cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[index]);
break;
case DR7_TYPE_IO_RW:
/* No support for I/O watchpoints yet */
diff --git a/target-i386/machine.c b/target-i386/machine.c
index dc81cde..7f05c3b 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -275,6 +275,7 @@ static void cpu_pre_save(void *opaque)
static int cpu_post_load(void *opaque, int version_id)
{
X86CPU *cpu = opaque;
+ CPUState *cs = CPU(cpu);
CPUX86State *env = &cpu->env;
int i;
@@ -305,7 +306,7 @@ static int cpu_post_load(void *opaque, int version_id)
}
cpu_breakpoint_remove_all(env, BP_CPU);
- cpu_watchpoint_remove_all(env, BP_CPU);
+ cpu_watchpoint_remove_all(cs, BP_CPU);
for (i = 0; i < DR7_MAX_BP; i++) {
hw_breakpoint_insert(env, i);
}
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 24f7579..164b34b 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -782,11 +782,12 @@ void HELPER(wsr_ibreaka)(CPUXtensaState *env, uint32_t i, uint32_t v)
static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
uint32_t dbreakc)
{
+ CPUState *cs = CPU(xtensa_env_get_cpu(env));
int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
uint32_t mask = dbreakc | ~DBREAKC_MASK;
if (env->cpu_watchpoint[i]) {
- cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]);
+ cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
}
if (dbreakc & DBREAKC_SB) {
flags |= BP_MEM_WRITE;
@@ -800,7 +801,7 @@ static void set_dbreak(CPUXtensaState *env, unsigned i, uint32_t dbreaka,
/* cut mask after the first zero bit */
mask = 0xffffffff << (32 - clo32(mask));
}
- if (cpu_watchpoint_insert(env, dbreaka & mask, ~mask + 1,
+ if (cpu_watchpoint_insert(cs, dbreaka & mask, ~mask + 1,
flags, &env->cpu_watchpoint[i])) {
env->cpu_watchpoint[i] = NULL;
qemu_log("Failed to set data breakpoint at 0x%08x/%d\n",
@@ -826,7 +827,9 @@ void HELPER(wsr_dbreakc)(CPUXtensaState *env, uint32_t i, uint32_t v)
set_dbreak(env, i, env->sregs[DBREAKA + i], v);
} else {
if (env->cpu_watchpoint[i]) {
- cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[i]);
+ CPUState *cs = CPU(xtensa_env_get_cpu(env));
+
+ cpu_watchpoint_remove_by_ref(cs, env->cpu_watchpoint[i]);
env->cpu_watchpoint[i] = NULL;
}
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 28/41] exec: Change cpu_breakpoint_{insert, remove{, _by_ref, _all}} argument
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (26 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 27/41] exec: Change cpu_watchpoint_{insert, remove{, _by_ref, _all}} argument Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 29/41] cpu-exec: Change cpu_resume_from_signal() argument to CPUState Andreas Färber
` (15 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Riku Voipio, Andreas Färber
Use CPUState. Allows to clean up CPUArchState in gdbstub.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
exec.c | 20 ++++++++------------
gdbstub.c | 20 ++++++++------------
include/exec/cpu-all.h | 15 ---------------
include/qom/cpu.h | 15 +++++++++++++++
linux-user/main.c | 2 +-
target-i386/cpu.c | 2 +-
target-i386/helper.c | 4 ++--
target-i386/machine.c | 2 +-
8 files changed, 36 insertions(+), 44 deletions(-)
diff --git a/exec.c b/exec.c
index cfd0ecb..7ea864a 100644
--- a/exec.c
+++ b/exec.c
@@ -507,11 +507,10 @@ void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
#endif
/* Add a breakpoint. */
-int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
+int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
CPUBreakpoint **breakpoint)
{
#if defined(TARGET_HAS_ICE)
- CPUState *cpu = ENV_GET_CPU(env);
CPUBreakpoint *bp;
bp = g_malloc(sizeof(*bp));
@@ -538,15 +537,14 @@ int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
}
/* Remove a specific breakpoint. */
-int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags)
+int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags)
{
#if defined(TARGET_HAS_ICE)
- CPUState *cpu = ENV_GET_CPU(env);
CPUBreakpoint *bp;
QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
if (bp->pc == pc && bp->flags == flags) {
- cpu_breakpoint_remove_by_ref(env, bp);
+ cpu_breakpoint_remove_by_ref(cpu, bp);
return 0;
}
}
@@ -557,11 +555,9 @@ int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags)
}
/* Remove a specific breakpoint by reference. */
-void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint)
+void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint)
{
#if defined(TARGET_HAS_ICE)
- CPUState *cpu = ENV_GET_CPU(env);
-
QTAILQ_REMOVE(&cpu->breakpoints, breakpoint, entry);
breakpoint_invalidate(cpu, breakpoint->pc);
@@ -571,15 +567,15 @@ void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint)
}
/* Remove all matching breakpoints. */
-void cpu_breakpoint_remove_all(CPUArchState *env, int mask)
+void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
{
#if defined(TARGET_HAS_ICE)
- CPUState *cpu = ENV_GET_CPU(env);
CPUBreakpoint *bp, *next;
QTAILQ_FOREACH_SAFE(bp, &cpu->breakpoints, entry, next) {
- if (bp->flags & mask)
- cpu_breakpoint_remove_by_ref(env, bp);
+ if (bp->flags & mask) {
+ cpu_breakpoint_remove_by_ref(cpu, bp);
+ }
}
#endif
}
diff --git a/gdbstub.c b/gdbstub.c
index 1e0dea4..8bdefe2 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -638,7 +638,6 @@ static const int xlat_gdb_type[] = {
static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
{
CPUState *cpu;
- CPUArchState *env;
int err = 0;
if (kvm_enabled()) {
@@ -649,10 +648,10 @@ static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
case GDB_BREAKPOINT_SW:
case GDB_BREAKPOINT_HW:
CPU_FOREACH(cpu) {
- env = cpu->env_ptr;
- err = cpu_breakpoint_insert(env, addr, BP_GDB, NULL);
- if (err)
+ err = cpu_breakpoint_insert(cpu, addr, BP_GDB, NULL);
+ if (err) {
break;
+ }
}
return err;
#ifndef CONFIG_USER_ONLY
@@ -675,7 +674,6 @@ static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
{
CPUState *cpu;
- CPUArchState *env;
int err = 0;
if (kvm_enabled()) {
@@ -686,10 +684,10 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
case GDB_BREAKPOINT_SW:
case GDB_BREAKPOINT_HW:
CPU_FOREACH(cpu) {
- env = cpu->env_ptr;
- err = cpu_breakpoint_remove(env, addr, BP_GDB);
- if (err)
+ err = cpu_breakpoint_remove(cpu, addr, BP_GDB);
+ if (err) {
break;
+ }
}
return err;
#ifndef CONFIG_USER_ONLY
@@ -711,7 +709,6 @@ static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
static void gdb_breakpoint_remove_all(void)
{
CPUState *cpu;
- CPUArchState *env;
if (kvm_enabled()) {
kvm_remove_all_breakpoints(gdbserver_state->c_cpu);
@@ -719,8 +716,7 @@ static void gdb_breakpoint_remove_all(void)
}
CPU_FOREACH(cpu) {
- env = cpu->env_ptr;
- cpu_breakpoint_remove_all(env, BP_GDB);
+ cpu_breakpoint_remove_all(cpu, BP_GDB);
#ifndef CONFIG_USER_ONLY
cpu_watchpoint_remove_all(cpu, BP_GDB);
#endif
@@ -1604,7 +1600,7 @@ void gdbserver_fork(CPUArchState *env)
}
close(s->fd);
s->fd = -1;
- cpu_breakpoint_remove_all(env, BP_GDB);
+ cpu_breakpoint_remove_all(cpu, BP_GDB);
cpu_watchpoint_remove_all(cpu, BP_GDB);
}
#else
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index c3ff709..a26d653 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -412,21 +412,6 @@ void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...)
| CPU_INTERRUPT_TGT_EXT_3 \
| CPU_INTERRUPT_TGT_EXT_4)
-/* Breakpoint/watchpoint flags */
-#define BP_MEM_READ 0x01
-#define BP_MEM_WRITE 0x02
-#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
-#define BP_STOP_BEFORE_ACCESS 0x04
-#define BP_WATCHPOINT_HIT 0x08
-#define BP_GDB 0x10
-#define BP_CPU 0x20
-
-int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
- CPUBreakpoint **breakpoint);
-int cpu_breakpoint_remove(CPUArchState *env, target_ulong pc, int flags);
-void cpu_breakpoint_remove_by_ref(CPUArchState *env, CPUBreakpoint *breakpoint);
-void cpu_breakpoint_remove_all(CPUArchState *env, int mask);
-
#if !defined(CONFIG_USER_ONLY)
/* memory API */
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 9ef30d3..85ba419 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -600,6 +600,21 @@ void qemu_init_vcpu(CPUState *cpu);
*/
void cpu_single_step(CPUState *cpu, int enabled);
+/* Breakpoint/watchpoint flags */
+#define BP_MEM_READ 0x01
+#define BP_MEM_WRITE 0x02
+#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
+#define BP_STOP_BEFORE_ACCESS 0x04
+#define BP_WATCHPOINT_HIT 0x08
+#define BP_GDB 0x10
+#define BP_CPU 0x20
+
+int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
+ CPUBreakpoint **breakpoint);
+int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
+void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
+void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
+
int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
int flags, CPUWatchpoint **watchpoint);
int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
diff --git a/linux-user/main.c b/linux-user/main.c
index 6feaa50..cadefbe 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3211,7 +3211,7 @@ CPUArchState *cpu_copy(CPUArchState *env)
QTAILQ_INIT(&cpu->watchpoints);
#if defined(TARGET_HAS_ICE)
QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
- cpu_breakpoint_insert(new_env, bp->pc, bp->flags, NULL);
+ cpu_breakpoint_insert(new_cpu, bp->pc, bp->flags, NULL);
}
QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
cpu_watchpoint_insert(new_cpu, wp->vaddr, (~wp->len_mask) + 1,
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index b80f75b..944c3d7 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2390,7 +2390,7 @@ static void x86_cpu_reset(CPUState *s)
memset(env->dr, 0, sizeof(env->dr));
env->dr[6] = DR6_FIXED_1;
env->dr[7] = DR7_FIXED_1;
- cpu_breakpoint_remove_all(env, BP_CPU);
+ cpu_breakpoint_remove_all(s, BP_CPU);
cpu_watchpoint_remove_all(s, BP_CPU);
#if !defined(CONFIG_USER_ONLY)
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 69cc374..1cd7688 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -994,7 +994,7 @@ void hw_breakpoint_insert(CPUX86State *env, int index)
switch (hw_breakpoint_type(env->dr[7], index)) {
case DR7_TYPE_BP_INST:
if (hw_breakpoint_enabled(env->dr[7], index)) {
- err = cpu_breakpoint_insert(env, env->dr[index], BP_CPU,
+ err = cpu_breakpoint_insert(cs, env->dr[index], BP_CPU,
&env->cpu_breakpoint[index]);
}
break;
@@ -1031,7 +1031,7 @@ void hw_breakpoint_remove(CPUX86State *env, int index)
switch (hw_breakpoint_type(env->dr[7], index)) {
case DR7_TYPE_BP_INST:
if (hw_breakpoint_enabled(env->dr[7], index)) {
- cpu_breakpoint_remove_by_ref(env, env->cpu_breakpoint[index]);
+ cpu_breakpoint_remove_by_ref(cs, env->cpu_breakpoint[index]);
}
break;
case DR7_TYPE_DATA_WR:
diff --git a/target-i386/machine.c b/target-i386/machine.c
index 7f05c3b..54dd2ab 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -305,7 +305,7 @@ static int cpu_post_load(void *opaque, int version_id)
env->fptags[i] = (env->fptag_vmstate >> i) & 1;
}
- cpu_breakpoint_remove_all(env, BP_CPU);
+ cpu_breakpoint_remove_all(cs, BP_CPU);
cpu_watchpoint_remove_all(cs, BP_CPU);
for (i = 0; i < DR7_MAX_BP; i++) {
hw_breakpoint_insert(env, i);
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 29/41] cpu-exec: Change cpu_resume_from_signal() argument to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (27 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 28/41] exec: Change cpu_breakpoint_{insert, " Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 30/41] cputlb: Change tlb_update_dirty() " Andreas Färber
` (14 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Max Filippov, Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cpu-exec.c | 4 +---
exec.c | 3 +--
hw/i386/kvmvapic.c | 3 +--
include/exec/exec-all.h | 2 +-
target-i386/helper.c | 2 +-
target-xtensa/helper.c | 2 +-
translate-all.c | 12 ++++++------
user-exec.c | 3 +--
8 files changed, 13 insertions(+), 18 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index a984b7c..6016a10 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -33,10 +33,8 @@ void cpu_loop_exit(CPUState *cpu)
restored in a state compatible with the CPU emulator
*/
#if defined(CONFIG_SOFTMMU)
-void cpu_resume_from_signal(CPUArchState *env, void *puc)
+void cpu_resume_from_signal(CPUState *cpu, void *puc)
{
- CPUState *cpu = ENV_GET_CPU(env);
-
/* XXX: restore cpu registers saved in host registers */
cpu->exception_index = -1;
diff --git a/exec.c b/exec.c
index 7ea864a..5f133e4 100644
--- a/exec.c
+++ b/exec.c
@@ -1455,7 +1455,6 @@ static const MemoryRegionOps notdirty_mem_ops = {
static void check_watchpoint(int offset, int len_mask, int flags)
{
CPUState *cpu = current_cpu;
- CPUArchState *env = cpu->env_ptr;
CPUClass *cc = CPU_GET_CLASS(cpu);
vaddr pc, cs_base;
target_ulong vaddr;
@@ -1483,7 +1482,7 @@ static void check_watchpoint(int offset, int len_mask, int flags)
} else {
cc->get_tb_cpu_state(cpu, &pc, &cs_base, &cpu_flags);
tb_gen_code(cpu, pc, cs_base, cpu_flags, 1);
- cpu_resume_from_signal(env, NULL);
+ cpu_resume_from_signal(cpu, NULL);
}
}
} else {
diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c
index bcf8d9d..95449f7 100644
--- a/hw/i386/kvmvapic.c
+++ b/hw/i386/kvmvapic.c
@@ -391,7 +391,6 @@ static void patch_call(VAPICROMState *s, X86CPU *cpu, target_ulong ip,
static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
{
CPUState *cs = CPU(cpu);
- CPUX86State *env = &cpu->env;
VAPICHandlers *handlers;
uint8_t opcode[2];
uint32_t imm32;
@@ -451,7 +450,7 @@ static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulong ip)
if (!kvm_enabled()) {
cs->current_tb = NULL;
tb_gen_code(cs, current_pc, current_cs_base, current_flags, 1);
- cpu_resume_from_signal(env, NULL);
+ cpu_resume_from_signal(cs, NULL);
}
}
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 73abf9e..1838ae1 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -82,7 +82,7 @@ int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb,
int *gen_code_size_ptr);
bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
-void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc);
+void QEMU_NORETURN cpu_resume_from_signal(CPUState *cpu, void *puc);
void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
TranslationBlock *tb_gen_code(CPUState *cpu,
target_ulong pc, target_ulong cs_base, int flags,
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 1cd7688..a6d64a6 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -1097,7 +1097,7 @@ void breakpoint_handler(CPUX86State *env)
if (check_hw_breakpoints(env, false)) {
raise_exception(env, EXCP01_DB);
} else {
- cpu_resume_from_signal(env, NULL);
+ cpu_resume_from_signal(cs, NULL);
}
}
} else {
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index c44cf71..9e5af25 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -92,7 +92,7 @@ void xtensa_breakpoint_handler(CPUXtensaState *env)
if (cause) {
debug_exception_env(env, cause);
}
- cpu_resume_from_signal(env, NULL);
+ cpu_resume_from_signal(cs, NULL);
}
}
}
diff --git a/translate-all.c b/translate-all.c
index 2254b9f..9b62b07 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1002,7 +1002,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
{
TranslationBlock *tb, *tb_next, *saved_tb;
CPUState *cpu = current_cpu;
-#if defined(TARGET_HAS_PRECISE_SMC) || !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
CPUArchState *env = NULL;
#endif
tb_page_addr_t tb_start, tb_end;
@@ -1030,7 +1030,9 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
}
#if defined(TARGET_HAS_PRECISE_SMC) || !defined(CONFIG_USER_ONLY)
if (cpu != NULL) {
+#ifndef CONFIG_USER_ONLY
env = cpu->env_ptr;
+#endif
#ifdef TARGET_HAS_PRECISE_SMC
cc = CPU_GET_CLASS(cpu);
#endif
@@ -1112,7 +1114,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
itself */
cpu->current_tb = NULL;
tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1);
- cpu_resume_from_signal(env, NULL);
+ cpu_resume_from_signal(cpu, NULL);
}
#endif
}
@@ -1160,7 +1162,6 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr,
TranslationBlock *current_tb = NULL;
CPUState *cpu = current_cpu;
CPUClass *cc = NULL;
- CPUArchState *env = NULL;
int current_tb_modified = 0;
vaddr current_pc = 0;
vaddr current_cs_base = 0;
@@ -1178,7 +1179,6 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr,
current_tb = tb_find_pc(pc);
}
if (cpu != NULL) {
- env = cpu->env_ptr;
cc = CPU_GET_CLASS(cpu);
}
#endif
@@ -1214,7 +1214,7 @@ static void tb_invalidate_phys_page(tb_page_addr_t addr,
if (locked) {
mmap_unlock();
}
- cpu_resume_from_signal(env, puc);
+ cpu_resume_from_signal(cpu, puc);
}
#endif
}
@@ -1489,7 +1489,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
repeating the fault, which is horribly inefficient.
Better would be to execute just this insn uncached, or generate a
second new TB. */
- cpu_resume_from_signal(env, NULL);
+ cpu_resume_from_signal(cpu, NULL);
}
void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr)
diff --git a/user-exec.c b/user-exec.c
index 75c6d54..3b795c1 100644
--- a/user-exec.c
+++ b/user-exec.c
@@ -52,9 +52,8 @@ static void exception_action(CPUArchState *env1)
/* exit the current TB from a signal handler. The host registers are
restored in a state compatible with the CPU emulator
*/
-void cpu_resume_from_signal(CPUArchState *env1, void *puc)
+void cpu_resume_from_signal(CPUState *cpu, void *puc)
{
- CPUState *cpu = ENV_GET_CPU(env1);
#ifdef __linux__
struct ucontext *uc = puc;
#elif defined(__OpenBSD__)
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 30/41] cputlb: Change tlb_update_dirty() argument to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (28 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 29/41] cpu-exec: Change cpu_resume_from_signal() argument to CPUState Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 31/41] exec: Change memory_region_section_get_iotlb() " Andreas Färber
` (13 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
This allows to drop env in tb_invalidate_phys_page_range().
Note that the argument is unused.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cputlb.c | 2 +-
include/exec/cputlb.h | 2 +-
translate-all.c | 12 ++----------
3 files changed, 4 insertions(+), 12 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index 3721bfc..bd5cf0e 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -134,7 +134,7 @@ void tlb_protect_code(ram_addr_t ram_addr)
/* update the TLB so that writes in physical page 'phys_addr' are no longer
tested for self modifying code */
-void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
+void tlb_unprotect_code_phys(CPUState *cpu, ram_addr_t ram_addr,
target_ulong vaddr)
{
cpu_physical_memory_set_dirty_flags(ram_addr, CODE_DIRTY_FLAG);
diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h
index e1eb4d9..31df03c 100644
--- a/include/exec/cputlb.h
+++ b/include/exec/cputlb.h
@@ -22,7 +22,7 @@
#if !defined(CONFIG_USER_ONLY)
/* cputlb.c */
void tlb_protect_code(ram_addr_t ram_addr);
-void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
+void tlb_unprotect_code_phys(CPUState *cpu, ram_addr_t ram_addr,
target_ulong vaddr);
void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
uintptr_t length);
diff --git a/translate-all.c b/translate-all.c
index 9b62b07..37b573b 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1002,9 +1002,6 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
{
TranslationBlock *tb, *tb_next, *saved_tb;
CPUState *cpu = current_cpu;
-#if !defined(CONFIG_USER_ONLY)
- CPUArchState *env = NULL;
-#endif
tb_page_addr_t tb_start, tb_end;
PageDesc *p;
int n;
@@ -1028,14 +1025,9 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
/* build code bitmap */
build_page_bitmap(p);
}
-#if defined(TARGET_HAS_PRECISE_SMC) || !defined(CONFIG_USER_ONLY)
+#if defined(TARGET_HAS_PRECISE_SMC)
if (cpu != NULL) {
-#ifndef CONFIG_USER_ONLY
- env = cpu->env_ptr;
-#endif
-#ifdef TARGET_HAS_PRECISE_SMC
cc = CPU_GET_CLASS(cpu);
-#endif
}
#endif
@@ -1103,7 +1095,7 @@ void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
if (!p->first_tb) {
invalidate_page_bitmap(p);
if (is_cpu_write_access) {
- tlb_unprotect_code_phys(env, start, cpu->mem_io_vaddr);
+ tlb_unprotect_code_phys(cpu, start, cpu->mem_io_vaddr);
}
}
#endif
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 31/41] exec: Change memory_region_section_get_iotlb() argument to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (29 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 30/41] cputlb: Change tlb_update_dirty() " Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 32/41] cputlb: Change tlb_set_page() " Andreas Färber
` (12 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
It no longer needs CPUArchState since moving watchpoints to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cputlb.c | 3 ++-
exec.c | 3 +--
include/exec/cputlb.h | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index bd5cf0e..e5b6145 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -241,6 +241,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size)
{
+ CPUState *cpu = ENV_GET_CPU(env);
MemoryRegionSection *section;
unsigned int index;
target_ulong address;
@@ -276,7 +277,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
}
code_address = address;
- iotlb = memory_region_section_get_iotlb(env, section, vaddr, paddr, xlat,
+ iotlb = memory_region_section_get_iotlb(cpu, section, vaddr, paddr, xlat,
prot, &address);
index = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
diff --git a/exec.c b/exec.c
index 5f133e4..ffbf4c3 100644
--- a/exec.c
+++ b/exec.c
@@ -677,14 +677,13 @@ static int cpu_physical_memory_set_dirty_tracking(int enable)
return ret;
}
-hwaddr memory_region_section_get_iotlb(CPUArchState *env,
+hwaddr memory_region_section_get_iotlb(CPUState *cpu,
MemoryRegionSection *section,
target_ulong vaddr,
hwaddr paddr, hwaddr xlat,
int prot,
target_ulong *address)
{
- CPUState *cpu = ENV_GET_CPU(env);
hwaddr iotlb;
CPUWatchpoint *wp;
diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h
index 31df03c..b8ecd6f 100644
--- a/include/exec/cputlb.h
+++ b/include/exec/cputlb.h
@@ -36,7 +36,7 @@ void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr);
MemoryRegionSection *
address_space_translate_for_iotlb(AddressSpace *as, hwaddr addr, hwaddr *xlat,
hwaddr *plen);
-hwaddr memory_region_section_get_iotlb(CPUArchState *env,
+hwaddr memory_region_section_get_iotlb(CPUState *cpu,
MemoryRegionSection *section,
target_ulong vaddr,
hwaddr paddr, hwaddr xlat,
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 32/41] cputlb: Change tlb_set_page() argument to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (30 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 31/41] exec: Change memory_region_section_get_iotlb() " Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 33/41] " Andreas Färber
` (11 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
It no longer needs CPUArchState since moving tlb_flush_* to CPUState.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cputlb.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index e5b6145..ddcd2cd 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -212,10 +212,9 @@ void tlb_set_dirty(CPUArchState *env, target_ulong vaddr)
/* Our TLB does not support large pages, so remember the area covered by
large pages and trigger a full TLB flush if these are invalidated. */
-static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
+static void tlb_add_large_page(CPUState *cpu, target_ulong vaddr,
target_ulong size)
{
- CPUState *cpu = ENV_GET_CPU(env);
target_ulong mask = ~(size - 1);
if ((target_ulong)cpu->tlb_flush_addr == (target_ulong)-1) {
@@ -252,7 +251,7 @@ void tlb_set_page(CPUArchState *env, target_ulong vaddr,
assert(size >= TARGET_PAGE_SIZE);
if (size != TARGET_PAGE_SIZE) {
- tlb_add_large_page(env, vaddr, size);
+ tlb_add_large_page(cpu, vaddr, size);
}
sz = size;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 33/41] cputlb: Change tlb_set_page() argument to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (31 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 32/41] cputlb: Change tlb_set_page() " Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 12:51 ` Jia Liu
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 34/41] exec: Change cpu_abort() " Andreas Färber
` (10 subsequent siblings)
43 siblings, 1 reply; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Anthony Green, Alexander Graf, Blue Swirl,
Max Filippov, Michael Walle, open list:PowerPC, Paul Brook,
Edgar E. Iglesias, Guan Xuetao, Andreas Färber,
Aurelien Jarno, Richard Henderson
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cputlb.c | 4 ++--
include/exec/exec-all.h | 2 +-
target-alpha/helper.c | 2 +-
target-arm/helper.c | 2 +-
target-cris/helper.c | 2 +-
target-i386/helper.c | 2 +-
target-lm32/helper.c | 6 +++---
target-m68k/helper.c | 3 +--
target-microblaze/helper.c | 4 ++--
target-mips/helper.c | 2 +-
target-moxie/helper.c | 2 +-
target-openrisc/mmu.c | 2 +-
target-ppc/mmu-hash32.c | 8 ++++----
target-ppc/mmu-hash64.c | 4 ++--
target-ppc/mmu_helper.c | 2 +-
target-s390x/helper.c | 2 +-
target-sh4/helper.c | 2 +-
target-sparc/mmu_helper.c | 6 +++---
target-unicore32/softmmu.c | 2 +-
target-xtensa/op_helper.c | 8 ++++----
20 files changed, 33 insertions(+), 34 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index ddcd2cd..f8b9566 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -236,11 +236,11 @@ static void tlb_add_large_page(CPUState *cpu, target_ulong vaddr,
/* Add a new TLB entry. At most one entry for a given virtual address
is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
supplied size is only used by tlb_flush_page. */
-void tlb_set_page(CPUArchState *env, target_ulong vaddr,
+void tlb_set_page(CPUState *cpu, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUArchState *env = cpu->env_ptr;
MemoryRegionSection *section;
unsigned int index;
target_ulong address;
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 1838ae1..847ed84 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -98,7 +98,7 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
/* cputlb.c */
void tlb_flush_page(CPUArchState *env, target_ulong addr);
void tlb_flush(CPUArchState *env, int flush_global);
-void tlb_set_page(CPUArchState *env, target_ulong vaddr,
+void tlb_set_page(CPUState *cpu, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size);
void tb_invalidate_phys_addr(hwaddr addr);
diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index f0ba5dd..fd4a70c 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -344,7 +344,7 @@ int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int rw,
return 1;
}
- tlb_set_page(env, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
+ tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
}
diff --git a/target-arm/helper.c b/target-arm/helper.c
index bc00858..06dd57c 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3040,7 +3040,7 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
/* Map a single [sub]page. */
phys_addr &= ~(hwaddr)0x3ff;
address &= ~(uint32_t)0x3ff;
- tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
+ tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
return 0;
}
diff --git a/target-cris/helper.c b/target-cris/helper.c
index 3c4501c..08b3864 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -106,7 +106,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
*/
phy = res.phy & ~0x80000000;
prot = res.prot;
- tlb_set_page(env, address & TARGET_PAGE_MASK, phy,
+ tlb_set_page(cs, address & TARGET_PAGE_MASK, phy,
prot, mmu_idx, TARGET_PAGE_SIZE);
r = 0;
}
diff --git a/target-i386/helper.c b/target-i386/helper.c
index a6d64a6..e0df092 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -864,7 +864,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
paddr = (pte & TARGET_PAGE_MASK) + page_offset;
vaddr = virt_addr + page_offset;
- tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
+ tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
return 0;
do_fault_protect:
error_code = PG_ERROR_P_MASK;
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index b2093a8..daf0f2f 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -30,10 +30,10 @@ int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
address &= TARGET_PAGE_MASK;
prot = PAGE_BITS;
if (env->flags & LM32_FLAG_IGNORE_MSB) {
- tlb_set_page(env, address, address & 0x7fffffff, prot, mmu_idx,
- TARGET_PAGE_SIZE);
+ tlb_set_page(cs, address, address & 0x7fffffff, prot, mmu_idx,
+ TARGET_PAGE_SIZE);
} else {
- tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
}
return 0;
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index e38065c..219e8b3 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -300,12 +300,11 @@ hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int mmu_idx)
{
- M68kCPU *cpu = M68K_CPU(cs);
int prot;
address &= TARGET_PAGE_MASK;
prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
- tlb_set_page(&cpu->env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
}
diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
index 4825415..50aa55a 100644
--- a/target-microblaze/helper.c
+++ b/target-microblaze/helper.c
@@ -77,7 +77,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n",
mmu_idx, vaddr, paddr, lu.prot));
- tlb_set_page(env, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
r = 0;
} else {
env->sregs[SR_EAR] = address;
@@ -108,7 +108,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
/* MMU disabled or not available. */
address &= TARGET_PAGE_MASK;
prot = PAGE_BITS;
- tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
r = 0;
}
return r;
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 698c3d1..ca2f0e7 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -300,7 +300,7 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
" prot %d\n",
__func__, address, ret, physical, prot);
if (ret == TLBRET_MATCH) {
- tlb_set_page(env, address & TARGET_PAGE_MASK,
+ tlb_set_page(cs, address & TARGET_PAGE_MASK,
physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
mmu_idx, TARGET_PAGE_SIZE);
ret = 0;
diff --git a/target-moxie/helper.c b/target-moxie/helper.c
index 04b36b7..3d0c34d 100644
--- a/target-moxie/helper.c
+++ b/target-moxie/helper.c
@@ -148,7 +148,7 @@ int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
phy = res.phy;
r = 0;
}
- tlb_set_page(env, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE);
return r;
}
diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c
index b1830da..cc026a7 100644
--- a/target-openrisc/mmu.c
+++ b/target-openrisc/mmu.c
@@ -194,7 +194,7 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs,
address, rw);
if (ret == TLBRET_MATCH) {
- tlb_set_page(&cpu->env, address & TARGET_PAGE_MASK,
+ tlb_set_page(cs, address & TARGET_PAGE_MASK,
physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
mmu_idx, TARGET_PAGE_SIZE);
ret = 0;
diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
index 6a4d6a8..1cc1916 100644
--- a/target-ppc/mmu-hash32.c
+++ b/target-ppc/mmu-hash32.c
@@ -400,7 +400,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
/* Translation is off */
raddr = eaddr;
- tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
+ tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
TARGET_PAGE_SIZE);
return 0;
@@ -427,7 +427,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
return 1;
}
- tlb_set_page(env, eaddr & TARGET_PAGE_MASK,
+ tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
raddr & TARGET_PAGE_MASK, prot, mmu_idx,
TARGET_PAGE_SIZE);
return 0;
@@ -441,7 +441,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
if (sr & SR32_T) {
if (ppc_hash32_direct_store(env, sr, eaddr, rwx,
&raddr, &prot) == 0) {
- tlb_set_page(env, eaddr & TARGET_PAGE_MASK,
+ tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
raddr & TARGET_PAGE_MASK, prot, mmu_idx,
TARGET_PAGE_SIZE);
return 0;
@@ -522,7 +522,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
raddr = ppc_hash32_pte_raddr(sr, pte, eaddr);
- tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
+ tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 82bfa7c..b060e69 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -416,7 +416,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
/* Translation is off */
/* In real mode the top 4 effective address bits are ignored */
raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
- tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
+ tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
TARGET_PAGE_SIZE);
return 0;
@@ -517,7 +517,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
raddr = ppc_hash64_pte_raddr(slb, pte, eaddr);
- tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
+ tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 5a237ce..ff70b38 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -1506,7 +1506,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
}
ret = get_physical_address(env, &ctx, address, rw, access_type);
if (ret == 0) {
- tlb_set_page(env, address & TARGET_PAGE_MASK,
+ tlb_set_page(cs, address & TARGET_PAGE_MASK,
ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
mmu_idx, TARGET_PAGE_SIZE);
ret = 0;
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index e1ed6c0..207af52 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -411,7 +411,7 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr,
DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__,
(uint64_t)vaddr, (uint64_t)raddr, prot);
- tlb_set_page(env, orig_vaddr, raddr, prot,
+ tlb_set_page(cs, orig_vaddr, raddr, prot,
mmu_idx, TARGET_PAGE_SIZE);
return 0;
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 0357ceb..b444da1 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -506,7 +506,7 @@ int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
address &= TARGET_PAGE_MASK;
physical &= TARGET_PAGE_MASK;
- tlb_set_page(env, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
}
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index ea72657..ad070de 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -216,7 +216,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
printf("Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr "
TARGET_FMT_lx "\n", address, paddr, vaddr);
#endif
- tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
+ tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
return 0;
}
@@ -232,7 +232,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
neverland. Fake/overridden mappings will be flushed when
switching to normal mode. */
prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
- tlb_set_page(env, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
+ tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
return 0;
} else {
if (rw & 2) {
@@ -727,7 +727,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
env->dmmu.mmu_primary_context,
env->dmmu.mmu_secondary_context);
- tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
+ tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
return 0;
}
/* XXX */
diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
index 2e26fd1..d0527e5 100644
--- a/target-unicore32/softmmu.c
+++ b/target-unicore32/softmmu.c
@@ -249,7 +249,7 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
/* Map a single page. */
phys_addr &= TARGET_PAGE_MASK;
address &= TARGET_PAGE_MASK;
- tlb_set_page(env, address, phys_addr, prot, mmu_idx, page_size);
+ tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
return 0;
}
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 164b34b..5952ed8 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -74,10 +74,10 @@ void tlb_fill(CPUState *cs,
vaddr, is_write, mmu_idx, paddr, ret);
if (ret == 0) {
- tlb_set_page(env,
- vaddr & TARGET_PAGE_MASK,
- paddr & TARGET_PAGE_MASK,
- access, mmu_idx, page_size);
+ tlb_set_page(cs,
+ vaddr & TARGET_PAGE_MASK,
+ paddr & TARGET_PAGE_MASK,
+ access, mmu_idx, page_size);
} else {
cpu_restore_state(cs, retaddr);
HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr);
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 33/41] cputlb: Change tlb_set_page() argument to CPUState
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 33/41] " Andreas Färber
@ 2013-09-04 12:51 ` Jia Liu
0 siblings, 0 replies; 68+ messages in thread
From: Jia Liu @ 2013-09-04 12:51 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Anthony Green, qemu-devel@nongnu.org,
Alexander Graf, Blue Swirl, Max Filippov, Michael Walle,
open list:PowerPC, Paul Brook, Edgar E. Iglesias, Guan Xuetao,
Aurelien Jarno, Richard Henderson
On Wed, Sep 4, 2013 at 5:05 PM, Andreas Färber <afaerber@suse.de> wrote:
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
> cputlb.c | 4 ++--
> include/exec/exec-all.h | 2 +-
> target-alpha/helper.c | 2 +-
> target-arm/helper.c | 2 +-
> target-cris/helper.c | 2 +-
> target-i386/helper.c | 2 +-
> target-lm32/helper.c | 6 +++---
> target-m68k/helper.c | 3 +--
> target-microblaze/helper.c | 4 ++--
> target-mips/helper.c | 2 +-
> target-moxie/helper.c | 2 +-
> target-openrisc/mmu.c | 2 +-
> target-ppc/mmu-hash32.c | 8 ++++----
> target-ppc/mmu-hash64.c | 4 ++--
> target-ppc/mmu_helper.c | 2 +-
> target-s390x/helper.c | 2 +-
> target-sh4/helper.c | 2 +-
> target-sparc/mmu_helper.c | 6 +++---
> target-unicore32/softmmu.c | 2 +-
> target-xtensa/op_helper.c | 8 ++++----
> 20 files changed, 33 insertions(+), 34 deletions(-)
>
> diff --git a/cputlb.c b/cputlb.c
> index ddcd2cd..f8b9566 100644
> --- a/cputlb.c
> +++ b/cputlb.c
> @@ -236,11 +236,11 @@ static void tlb_add_large_page(CPUState *cpu, target_ulong vaddr,
> /* Add a new TLB entry. At most one entry for a given virtual address
> is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
> supplied size is only used by tlb_flush_page. */
> -void tlb_set_page(CPUArchState *env, target_ulong vaddr,
> +void tlb_set_page(CPUState *cpu, target_ulong vaddr,
> hwaddr paddr, int prot,
> int mmu_idx, target_ulong size)
> {
> - CPUState *cpu = ENV_GET_CPU(env);
> + CPUArchState *env = cpu->env_ptr;
> MemoryRegionSection *section;
> unsigned int index;
> target_ulong address;
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index 1838ae1..847ed84 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -98,7 +98,7 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
> /* cputlb.c */
> void tlb_flush_page(CPUArchState *env, target_ulong addr);
> void tlb_flush(CPUArchState *env, int flush_global);
> -void tlb_set_page(CPUArchState *env, target_ulong vaddr,
> +void tlb_set_page(CPUState *cpu, target_ulong vaddr,
> hwaddr paddr, int prot,
> int mmu_idx, target_ulong size);
> void tb_invalidate_phys_addr(hwaddr addr);
> diff --git a/target-alpha/helper.c b/target-alpha/helper.c
> index f0ba5dd..fd4a70c 100644
> --- a/target-alpha/helper.c
> +++ b/target-alpha/helper.c
> @@ -344,7 +344,7 @@ int alpha_cpu_handle_mmu_fault(CPUState *cs, vaddr addr, int rw,
> return 1;
> }
>
> - tlb_set_page(env, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
> + tlb_set_page(cs, addr & TARGET_PAGE_MASK, phys & TARGET_PAGE_MASK,
> prot, mmu_idx, TARGET_PAGE_SIZE);
> return 0;
> }
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index bc00858..06dd57c 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -3040,7 +3040,7 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> /* Map a single [sub]page. */
> phys_addr &= ~(hwaddr)0x3ff;
> address &= ~(uint32_t)0x3ff;
> - tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
> + tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
> return 0;
> }
>
> diff --git a/target-cris/helper.c b/target-cris/helper.c
> index 3c4501c..08b3864 100644
> --- a/target-cris/helper.c
> +++ b/target-cris/helper.c
> @@ -106,7 +106,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> */
> phy = res.phy & ~0x80000000;
> prot = res.prot;
> - tlb_set_page(env, address & TARGET_PAGE_MASK, phy,
> + tlb_set_page(cs, address & TARGET_PAGE_MASK, phy,
> prot, mmu_idx, TARGET_PAGE_SIZE);
> r = 0;
> }
> diff --git a/target-i386/helper.c b/target-i386/helper.c
> index a6d64a6..e0df092 100644
> --- a/target-i386/helper.c
> +++ b/target-i386/helper.c
> @@ -864,7 +864,7 @@ int x86_cpu_handle_mmu_fault(CPUState *cs, vaddr addr,
> paddr = (pte & TARGET_PAGE_MASK) + page_offset;
> vaddr = virt_addr + page_offset;
>
> - tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
> + tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
> return 0;
> do_fault_protect:
> error_code = PG_ERROR_P_MASK;
> diff --git a/target-lm32/helper.c b/target-lm32/helper.c
> index b2093a8..daf0f2f 100644
> --- a/target-lm32/helper.c
> +++ b/target-lm32/helper.c
> @@ -30,10 +30,10 @@ int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> address &= TARGET_PAGE_MASK;
> prot = PAGE_BITS;
> if (env->flags & LM32_FLAG_IGNORE_MSB) {
> - tlb_set_page(env, address, address & 0x7fffffff, prot, mmu_idx,
> - TARGET_PAGE_SIZE);
> + tlb_set_page(cs, address, address & 0x7fffffff, prot, mmu_idx,
> + TARGET_PAGE_SIZE);
> } else {
> - tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
> + tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
> }
>
> return 0;
> diff --git a/target-m68k/helper.c b/target-m68k/helper.c
> index e38065c..219e8b3 100644
> --- a/target-m68k/helper.c
> +++ b/target-m68k/helper.c
> @@ -300,12 +300,11 @@ hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
> int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> int mmu_idx)
> {
> - M68kCPU *cpu = M68K_CPU(cs);
> int prot;
>
> address &= TARGET_PAGE_MASK;
> prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
> - tlb_set_page(&cpu->env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
> + tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
> return 0;
> }
>
> diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
> index 4825415..50aa55a 100644
> --- a/target-microblaze/helper.c
> +++ b/target-microblaze/helper.c
> @@ -77,7 +77,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
>
> DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n",
> mmu_idx, vaddr, paddr, lu.prot));
> - tlb_set_page(env, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
> + tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
> r = 0;
> } else {
> env->sregs[SR_EAR] = address;
> @@ -108,7 +108,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> /* MMU disabled or not available. */
> address &= TARGET_PAGE_MASK;
> prot = PAGE_BITS;
> - tlb_set_page(env, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
> + tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
> r = 0;
> }
> return r;
> diff --git a/target-mips/helper.c b/target-mips/helper.c
> index 698c3d1..ca2f0e7 100644
> --- a/target-mips/helper.c
> +++ b/target-mips/helper.c
> @@ -300,7 +300,7 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> " prot %d\n",
> __func__, address, ret, physical, prot);
> if (ret == TLBRET_MATCH) {
> - tlb_set_page(env, address & TARGET_PAGE_MASK,
> + tlb_set_page(cs, address & TARGET_PAGE_MASK,
> physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
> mmu_idx, TARGET_PAGE_SIZE);
> ret = 0;
> diff --git a/target-moxie/helper.c b/target-moxie/helper.c
> index 04b36b7..3d0c34d 100644
> --- a/target-moxie/helper.c
> +++ b/target-moxie/helper.c
> @@ -148,7 +148,7 @@ int moxie_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> phy = res.phy;
> r = 0;
> }
> - tlb_set_page(env, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE);
> + tlb_set_page(cs, address, phy, prot, mmu_idx, TARGET_PAGE_SIZE);
> return r;
> }
>
> diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c
> index b1830da..cc026a7 100644
> --- a/target-openrisc/mmu.c
> +++ b/target-openrisc/mmu.c
> @@ -194,7 +194,7 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs,
> address, rw);
>
> if (ret == TLBRET_MATCH) {
> - tlb_set_page(&cpu->env, address & TARGET_PAGE_MASK,
> + tlb_set_page(cs, address & TARGET_PAGE_MASK,
> physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
> mmu_idx, TARGET_PAGE_SIZE);
> ret = 0;
> diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
> index 6a4d6a8..1cc1916 100644
> --- a/target-ppc/mmu-hash32.c
> +++ b/target-ppc/mmu-hash32.c
> @@ -400,7 +400,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
> if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
> /* Translation is off */
> raddr = eaddr;
> - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
> + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
> PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
> TARGET_PAGE_SIZE);
> return 0;
> @@ -427,7 +427,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
> return 1;
> }
>
> - tlb_set_page(env, eaddr & TARGET_PAGE_MASK,
> + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
> raddr & TARGET_PAGE_MASK, prot, mmu_idx,
> TARGET_PAGE_SIZE);
> return 0;
> @@ -441,7 +441,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
> if (sr & SR32_T) {
> if (ppc_hash32_direct_store(env, sr, eaddr, rwx,
> &raddr, &prot) == 0) {
> - tlb_set_page(env, eaddr & TARGET_PAGE_MASK,
> + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK,
> raddr & TARGET_PAGE_MASK, prot, mmu_idx,
> TARGET_PAGE_SIZE);
> return 0;
> @@ -522,7 +522,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
>
> raddr = ppc_hash32_pte_raddr(sr, pte, eaddr);
>
> - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
> + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
> prot, mmu_idx, TARGET_PAGE_SIZE);
>
> return 0;
> diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
> index 82bfa7c..b060e69 100644
> --- a/target-ppc/mmu-hash64.c
> +++ b/target-ppc/mmu-hash64.c
> @@ -416,7 +416,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
> /* Translation is off */
> /* In real mode the top 4 effective address bits are ignored */
> raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
> - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
> + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
> PAGE_READ | PAGE_WRITE | PAGE_EXEC, mmu_idx,
> TARGET_PAGE_SIZE);
> return 0;
> @@ -517,7 +517,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
>
> raddr = ppc_hash64_pte_raddr(slb, pte, eaddr);
>
> - tlb_set_page(env, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
> + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MASK,
> prot, mmu_idx, TARGET_PAGE_SIZE);
>
> return 0;
> diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
> index 5a237ce..ff70b38 100644
> --- a/target-ppc/mmu_helper.c
> +++ b/target-ppc/mmu_helper.c
> @@ -1506,7 +1506,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> }
> ret = get_physical_address(env, &ctx, address, rw, access_type);
> if (ret == 0) {
> - tlb_set_page(env, address & TARGET_PAGE_MASK,
> + tlb_set_page(cs, address & TARGET_PAGE_MASK,
> ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
> mmu_idx, TARGET_PAGE_SIZE);
> ret = 0;
> diff --git a/target-s390x/helper.c b/target-s390x/helper.c
> index e1ed6c0..207af52 100644
> --- a/target-s390x/helper.c
> +++ b/target-s390x/helper.c
> @@ -411,7 +411,7 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr,
> DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__,
> (uint64_t)vaddr, (uint64_t)raddr, prot);
>
> - tlb_set_page(env, orig_vaddr, raddr, prot,
> + tlb_set_page(cs, orig_vaddr, raddr, prot,
> mmu_idx, TARGET_PAGE_SIZE);
>
> return 0;
> diff --git a/target-sh4/helper.c b/target-sh4/helper.c
> index 0357ceb..b444da1 100644
> --- a/target-sh4/helper.c
> +++ b/target-sh4/helper.c
> @@ -506,7 +506,7 @@ int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> address &= TARGET_PAGE_MASK;
> physical &= TARGET_PAGE_MASK;
>
> - tlb_set_page(env, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
> + tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
> return 0;
> }
>
> diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
> index ea72657..ad070de 100644
> --- a/target-sparc/mmu_helper.c
> +++ b/target-sparc/mmu_helper.c
> @@ -216,7 +216,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> printf("Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr "
> TARGET_FMT_lx "\n", address, paddr, vaddr);
> #endif
> - tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
> + tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
> return 0;
> }
>
> @@ -232,7 +232,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> neverland. Fake/overridden mappings will be flushed when
> switching to normal mode. */
> prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
> - tlb_set_page(env, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
> + tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
> return 0;
> } else {
> if (rw & 2) {
> @@ -727,7 +727,7 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> env->dmmu.mmu_primary_context,
> env->dmmu.mmu_secondary_context);
>
> - tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
> + tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
> return 0;
> }
> /* XXX */
> diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
> index 2e26fd1..d0527e5 100644
> --- a/target-unicore32/softmmu.c
> +++ b/target-unicore32/softmmu.c
> @@ -249,7 +249,7 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> /* Map a single page. */
> phys_addr &= TARGET_PAGE_MASK;
> address &= TARGET_PAGE_MASK;
> - tlb_set_page(env, address, phys_addr, prot, mmu_idx, page_size);
> + tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
> return 0;
> }
>
> diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
> index 164b34b..5952ed8 100644
> --- a/target-xtensa/op_helper.c
> +++ b/target-xtensa/op_helper.c
> @@ -74,10 +74,10 @@ void tlb_fill(CPUState *cs,
> vaddr, is_write, mmu_idx, paddr, ret);
>
> if (ret == 0) {
> - tlb_set_page(env,
> - vaddr & TARGET_PAGE_MASK,
> - paddr & TARGET_PAGE_MASK,
> - access, mmu_idx, page_size);
> + tlb_set_page(cs,
> + vaddr & TARGET_PAGE_MASK,
> + paddr & TARGET_PAGE_MASK,
> + access, mmu_idx, page_size);
> } else {
> cpu_restore_state(cs, retaddr);
> HELPER(exception_cause_vaddr)(env, env->pc, ret, vaddr);
target-openrisc: Tested-by: Jia Liu <proljc@gmail.com>
> --
> 1.8.1.4
>
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [RFC qom-cpu 34/41] exec: Change cpu_abort() argument to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (32 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 33/41] " Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 12:49 ` Jia Liu
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 35/41] target-cris: Replace DisasContext::env field with CRISCPU Andreas Färber
` (9 subsequent siblings)
43 siblings, 1 reply; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Riku Voipio, Alexander Graf, Blue Swirl,
Michael Walle, open list:PowerPC, Paul Brook, Edgar E. Iglesias,
Guan Xuetao, Andreas Färber, Aurelien Jarno,
Richard Henderson
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cputlb.c | 2 +-
exec.c | 3 +-
include/exec/cpu-all.h | 3 --
include/qom/cpu.h | 3 ++
linux-user/m68k-sim.c | 3 +-
linux-user/main.c | 80 ++++++++++++++++++++---------------------
target-alpha/helper.c | 2 +-
target-arm/helper.c | 35 ++++++++++++------
target-arm/translate.c | 2 +-
target-cris/helper.c | 4 +--
target-cris/translate.c | 4 +--
target-cris/translate_v10.c | 12 +++----
target-i386/seg_helper.c | 8 +++--
target-lm32/helper.c | 2 +-
target-lm32/translate.c | 38 ++++++++++----------
target-m68k/helper.c | 7 ++--
target-m68k/m68k-semi.c | 2 +-
target-m68k/translate.c | 4 ++-
target-microblaze/helper.c | 4 +--
target-microblaze/translate.c | 51 +++++++++++++++-----------
target-mips/op_helper.c | 11 ++++--
target-mips/translate_init.c | 4 ++-
target-openrisc/interrupt.c | 2 +-
target-ppc/cpu.h | 2 +-
target-ppc/excp_helper.c | 48 ++++++++++++-------------
target-ppc/mmu_helper.c | 54 ++++++++++++++++------------
target-ppc/translate_init.c | 5 +--
target-s390x/cc_helper.c | 3 +-
target-s390x/fpu_helper.c | 4 ++-
target-s390x/helper.c | 23 +++++++-----
target-s390x/mem_helper.c | 11 +++---
target-sh4/helper.c | 21 +++++++----
target-sh4/op_helper.c | 4 ++-
target-sparc/int32_helper.c | 2 +-
target-sparc/int64_helper.c | 2 +-
target-unicore32/helper.c | 14 +++-----
target-unicore32/softmmu.c | 13 ++++---
target-unicore32/translate.c | 28 +++++++++++++--
target-unicore32/ucf64_helper.c | 3 +-
translate-all.c | 16 ++++-----
40 files changed, 317 insertions(+), 222 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index f8b9566..20a1efe 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -335,7 +335,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
if (cc->do_unassigned_access) {
cc->do_unassigned_access(cpu, addr, false, true, 0, 4);
} else {
- cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x"
+ cpu_abort(cpu, "Trying to execute code outside RAM or ROM at 0x"
TARGET_FMT_lx "\n", addr);
}
}
diff --git a/exec.c b/exec.c
index ffbf4c3..16e3c4d 100644
--- a/exec.c
+++ b/exec.c
@@ -599,9 +599,8 @@ void cpu_single_step(CPUState *cpu, int enabled)
#endif
}
-void cpu_abort(CPUArchState *env, const char *fmt, ...)
+void cpu_abort(CPUState *cpu, const char *fmt, ...)
{
- CPUState *cpu = ENV_GET_CPU(env);
va_list ap;
va_list ap2;
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index a26d653..0490454 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -359,9 +359,6 @@ int page_check_range(target_ulong start, target_ulong len, int flags);
CPUArchState *cpu_copy(CPUArchState *env);
-void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...)
- GCC_FMT_ATTR(2, 3);
-
/* Flags for use in ENV->INTERRUPT_PENDING.
The numbers assigned here are non-sequential in order to preserve
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 85ba419..0427a71 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -622,6 +622,9 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
+void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
+ GCC_FMT_ATTR(2, 3);
+
#ifdef CONFIG_SOFTMMU
extern const struct VMStateDescription vmstate_cpu_common;
#else
diff --git a/linux-user/m68k-sim.c b/linux-user/m68k-sim.c
index d5926ee..1994e40 100644
--- a/linux-user/m68k-sim.c
+++ b/linux-user/m68k-sim.c
@@ -98,6 +98,7 @@ static int translate_openflags(int flags)
#define ARG(x) tswap32(args[x])
void do_m68k_simcall(CPUM68KState *env, int nr)
{
+ M68kCPU *cpu = m68k_env_get_cpu(env);
uint32_t *args;
args = (uint32_t *)(unsigned long)(env->aregs[7] + 4);
@@ -165,6 +166,6 @@ void do_m68k_simcall(CPUM68KState *env, int nr)
check_err(env, lseek(ARG(0), (int32_t)ARG(1), ARG(2)));
break;
default:
- cpu_abort(env, "Unsupported m68k sim syscall %d\n", nr);
+ cpu_abort(CPU(cpu), "Unsupported m68k sim syscall %d\n", nr);
}
}
diff --git a/linux-user/main.c b/linux-user/main.c
index cadefbe..b3b4ff6 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -1351,11 +1351,11 @@ void cpu_loop(CPUPPCState *env)
/* Just go on */
break;
case POWERPC_EXCP_CRITICAL: /* Critical input */
- cpu_abort(env, "Critical interrupt while in user mode. "
+ cpu_abort(cs, "Critical interrupt while in user mode. "
"Aborting\n");
break;
case POWERPC_EXCP_MCHECK: /* Machine check exception */
- cpu_abort(env, "Machine check exception while in user mode. "
+ cpu_abort(cs, "Machine check exception while in user mode. "
"Aborting\n");
break;
case POWERPC_EXCP_DSI: /* Data storage exception */
@@ -1419,7 +1419,7 @@ void cpu_loop(CPUPPCState *env)
queue_signal(env, info.si_signo, &info);
break;
case POWERPC_EXCP_EXTERNAL: /* External input */
- cpu_abort(env, "External interrupt while in user mode. "
+ cpu_abort(cs, "External interrupt while in user mode. "
"Aborting\n");
break;
case POWERPC_EXCP_ALIGN: /* Alignment exception */
@@ -1513,11 +1513,11 @@ void cpu_loop(CPUPPCState *env)
}
break;
case POWERPC_EXCP_TRAP:
- cpu_abort(env, "Tried to call a TRAP\n");
+ cpu_abort(cs, "Tried to call a TRAP\n");
break;
default:
/* Should not happen ! */
- cpu_abort(env, "Unknown program exception (%02x)\n",
+ cpu_abort(cs, "Unknown program exception (%02x)\n",
env->error_code);
break;
}
@@ -1533,7 +1533,7 @@ void cpu_loop(CPUPPCState *env)
queue_signal(env, info.si_signo, &info);
break;
case POWERPC_EXCP_SYSCALL: /* System call exception */
- cpu_abort(env, "Syscall exception while in user mode. "
+ cpu_abort(cs, "Syscall exception while in user mode. "
"Aborting\n");
break;
case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
@@ -1545,23 +1545,23 @@ void cpu_loop(CPUPPCState *env)
queue_signal(env, info.si_signo, &info);
break;
case POWERPC_EXCP_DECR: /* Decrementer exception */
- cpu_abort(env, "Decrementer interrupt while in user mode. "
+ cpu_abort(cs, "Decrementer interrupt while in user mode. "
"Aborting\n");
break;
case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
- cpu_abort(env, "Fix interval timer interrupt while in user mode. "
+ cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
"Aborting\n");
break;
case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
- cpu_abort(env, "Watchdog timer interrupt while in user mode. "
+ cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
"Aborting\n");
break;
case POWERPC_EXCP_DTLB: /* Data TLB error */
- cpu_abort(env, "Data TLB exception while in user mode. "
+ cpu_abort(cs, "Data TLB exception while in user mode. "
"Aborting\n");
break;
case POWERPC_EXCP_ITLB: /* Instruction TLB error */
- cpu_abort(env, "Instruction TLB exception while in user mode. "
+ cpu_abort(cs, "Instruction TLB exception while in user mode. "
"Aborting\n");
break;
case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
@@ -1573,37 +1573,37 @@ void cpu_loop(CPUPPCState *env)
queue_signal(env, info.si_signo, &info);
break;
case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
- cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
+ cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
break;
case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
- cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
+ cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
break;
case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
- cpu_abort(env, "Performance monitor exception not handled\n");
+ cpu_abort(cs, "Performance monitor exception not handled\n");
break;
case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
- cpu_abort(env, "Doorbell interrupt while in user mode. "
+ cpu_abort(cs, "Doorbell interrupt while in user mode. "
"Aborting\n");
break;
case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
- cpu_abort(env, "Doorbell critical interrupt while in user mode. "
+ cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
"Aborting\n");
break;
case POWERPC_EXCP_RESET: /* System reset exception */
- cpu_abort(env, "Reset interrupt while in user mode. "
+ cpu_abort(cs, "Reset interrupt while in user mode. "
"Aborting\n");
break;
case POWERPC_EXCP_DSEG: /* Data segment exception */
- cpu_abort(env, "Data segment exception while in user mode. "
+ cpu_abort(cs, "Data segment exception while in user mode. "
"Aborting\n");
break;
case POWERPC_EXCP_ISEG: /* Instruction segment exception */
- cpu_abort(env, "Instruction segment exception "
+ cpu_abort(cs, "Instruction segment exception "
"while in user mode. Aborting\n");
break;
/* PowerPC 64 with hypervisor mode support */
case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
- cpu_abort(env, "Hypervisor decrementer interrupt "
+ cpu_abort(cs, "Hypervisor decrementer interrupt "
"while in user mode. Aborting\n");
break;
case POWERPC_EXCP_TRACE: /* Trace exception */
@@ -1613,19 +1613,19 @@ void cpu_loop(CPUPPCState *env)
break;
/* PowerPC 64 with hypervisor mode support */
case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
- cpu_abort(env, "Hypervisor data storage exception "
+ cpu_abort(cs, "Hypervisor data storage exception "
"while in user mode. Aborting\n");
break;
case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
- cpu_abort(env, "Hypervisor instruction storage exception "
+ cpu_abort(cs, "Hypervisor instruction storage exception "
"while in user mode. Aborting\n");
break;
case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
- cpu_abort(env, "Hypervisor data segment exception "
+ cpu_abort(cs, "Hypervisor data segment exception "
"while in user mode. Aborting\n");
break;
case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
- cpu_abort(env, "Hypervisor instruction segment exception "
+ cpu_abort(cs, "Hypervisor instruction segment exception "
"while in user mode. Aborting\n");
break;
case POWERPC_EXCP_VPU: /* Vector unavailable exception */
@@ -1637,58 +1637,58 @@ void cpu_loop(CPUPPCState *env)
queue_signal(env, info.si_signo, &info);
break;
case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
- cpu_abort(env, "Programmable interval timer interrupt "
+ cpu_abort(cs, "Programmable interval timer interrupt "
"while in user mode. Aborting\n");
break;
case POWERPC_EXCP_IO: /* IO error exception */
- cpu_abort(env, "IO error exception while in user mode. "
+ cpu_abort(cs, "IO error exception while in user mode. "
"Aborting\n");
break;
case POWERPC_EXCP_RUNM: /* Run mode exception */
- cpu_abort(env, "Run mode exception while in user mode. "
+ cpu_abort(cs, "Run mode exception while in user mode. "
"Aborting\n");
break;
case POWERPC_EXCP_EMUL: /* Emulation trap exception */
- cpu_abort(env, "Emulation trap exception not handled\n");
+ cpu_abort(cs, "Emulation trap exception not handled\n");
break;
case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
- cpu_abort(env, "Instruction fetch TLB exception "
+ cpu_abort(cs, "Instruction fetch TLB exception "
"while in user-mode. Aborting");
break;
case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
- cpu_abort(env, "Data load TLB exception while in user-mode. "
+ cpu_abort(cs, "Data load TLB exception while in user-mode. "
"Aborting");
break;
case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
- cpu_abort(env, "Data store TLB exception while in user-mode. "
+ cpu_abort(cs, "Data store TLB exception while in user-mode. "
"Aborting");
break;
case POWERPC_EXCP_FPA: /* Floating-point assist exception */
- cpu_abort(env, "Floating-point assist exception not handled\n");
+ cpu_abort(cs, "Floating-point assist exception not handled\n");
break;
case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
- cpu_abort(env, "Instruction address breakpoint exception "
+ cpu_abort(cs, "Instruction address breakpoint exception "
"not handled\n");
break;
case POWERPC_EXCP_SMI: /* System management interrupt */
- cpu_abort(env, "System management interrupt while in user mode. "
+ cpu_abort(cs, "System management interrupt while in user mode. "
"Aborting\n");
break;
case POWERPC_EXCP_THERM: /* Thermal interrupt */
- cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
+ cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
"Aborting\n");
break;
case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
- cpu_abort(env, "Performance monitor exception not handled\n");
+ cpu_abort(cs, "Performance monitor exception not handled\n");
break;
case POWERPC_EXCP_VPUA: /* Vector assist exception */
- cpu_abort(env, "Vector assist exception not handled\n");
+ cpu_abort(cs, "Vector assist exception not handled\n");
break;
case POWERPC_EXCP_SOFTP: /* Soft patch exception */
- cpu_abort(env, "Soft patch exception not handled\n");
+ cpu_abort(cs, "Soft patch exception not handled\n");
break;
case POWERPC_EXCP_MAINT: /* Maintenance exception */
- cpu_abort(env, "Maintenance exception while in user mode. "
+ cpu_abort(cs, "Maintenance exception while in user mode. "
"Aborting\n");
break;
case POWERPC_EXCP_STOP: /* stop translation */
@@ -1744,7 +1744,7 @@ void cpu_loop(CPUPPCState *env)
/* just indicate that signals should be handled asap */
break;
default:
- cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
+ cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
break;
}
process_pending_signals(env);
diff --git a/target-alpha/helper.c b/target-alpha/helper.c
index fd4a70c..cd2373c 100644
--- a/target-alpha/helper.c
+++ b/target-alpha/helper.c
@@ -451,7 +451,7 @@ void alpha_cpu_do_interrupt(CPUState *cs)
}
break;
default:
- cpu_abort(env, "Unhandled CPU exception");
+ cpu_abort(cs, "Unhandled CPU exception");
}
/* Remember where the exception happened. Emulate real hardware in
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 06dd57c..34407a1 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2091,29 +2091,40 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
/* These should probably raise undefined insn exceptions. */
void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
{
- cpu_abort(env, "v7m_mrs %d\n", reg);
+ ARMCPU *cpu = arm_env_get_cpu(env);
+
+ cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
}
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
{
- cpu_abort(env, "v7m_mrs %d\n", reg);
+ ARMCPU *cpu = arm_env_get_cpu(env);
+
+ cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
return 0;
}
void switch_mode(CPUARMState *env, int mode)
{
- if (mode != ARM_CPU_MODE_USR)
- cpu_abort(env, "Tried to switch out of user mode\n");
+ ARMCPU *cpu = arm_env_get_cpu(env);
+
+ if (mode != ARM_CPU_MODE_USR) {
+ cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
+ }
}
void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
{
- cpu_abort(env, "banked r13 write\n");
+ ARMCPU *cpu = arm_env_get_cpu(env);
+
+ cpu_abort(CPU(cpu), "banked r13 write\n");
}
uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
{
- cpu_abort(env, "banked r13 read\n");
+ ARMCPU *cpu = arm_env_get_cpu(env);
+
+ cpu_abort(CPU(cpu), "banked r13 read\n");
return 0;
}
@@ -2308,7 +2319,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
do_v7m_exception_exit(env);
return;
default:
- cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
+ cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
return; /* Never happens. Keep compiler happy. */
}
@@ -2433,7 +2444,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
offset = 4;
break;
default:
- cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
+ cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
return; /* Never happens. Keep compiler happy. */
}
/* High vectors. */
@@ -3095,6 +3106,8 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
{
+ ARMCPU *cpu = arm_env_get_cpu(env);
+
switch (reg) {
case 0: /* APSR */
return xpsr_read(env) & 0xf8000000;
@@ -3125,13 +3138,15 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
return env->v7m.control;
default:
/* ??? For debugging only. */
- cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
+ cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
return 0;
}
}
void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
{
+ ARMCPU *cpu = arm_env_get_cpu(env);
+
switch (reg) {
case 0: /* APSR */
xpsr_write(env, val, 0xf8000000);
@@ -3192,7 +3207,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
break;
default:
/* ??? For debugging only. */
- cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
+ cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
return;
}
}
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 0eaec9f..bfbf1c4 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -10104,7 +10104,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
if (dc->condjmp) {
/* FIXME: This can theoretically happen with self-modifying
code. */
- cpu_abort(env, "IO on conditional branch instruction");
+ cpu_abort(cs, "IO on conditional branch instruction");
}
gen_io_end();
}
diff --git a/target-cris/helper.c b/target-cris/helper.c
index 08b3864..799cd16 100644
--- a/target-cris/helper.c
+++ b/target-cris/helper.c
@@ -89,7 +89,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
rw, mmu_idx, 0);
if (miss) {
if (cs->exception_index == EXCP_BUSFAULT) {
- cpu_abort(env,
+ cpu_abort(cs,
"CRIS: Illegal recursive bus fault."
"addr=%" VADDR_PRIx " rw=%d\n",
address, rw);
@@ -145,7 +145,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs)
break;
case EXCP_BUSFAULT:
- cpu_abort(env, "Unhandled busfault");
+ cpu_abort(cs, "Unhandled busfault");
break;
default:
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 90a4394..bf15ed6 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -129,7 +129,7 @@ static void gen_BUG(DisasContext *dc, const char *file, int line)
{
printf("BUG: pc=%x %s %d\n", dc->pc, file, line);
qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
- cpu_abort(dc->env, "%s:%d\n", file, line);
+ cpu_abort(CPU(cris_env_get_cpu(dc->env)), "%s:%d\n", file, line);
}
static const char *regnames[] =
@@ -272,7 +272,7 @@ static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,
break;
}
default:
- cpu_abort(dc->env, "Invalid fetch size %d\n", size);
+ cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Invalid fetch size %d\n", size);
break;
}
return r;
diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
index 0ade05b..734225f 100644
--- a/target-cris/translate_v10.c
+++ b/target-cris/translate_v10.c
@@ -340,7 +340,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
default:
LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
dc->pc, dc->mode, dc->opcode, dc->src, dc->dst);
- cpu_abort(dc->env, "Unhandled quickimm\n");
+ cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled quickimm\n");
break;
}
return 2;
@@ -651,7 +651,7 @@ static unsigned int dec10_reg(DisasContext *dc)
case 2: tmp = 1; break;
case 1: tmp = 0; break;
default:
- cpu_abort(dc->env, "Unhandled BIAP");
+ cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled BIAP");
break;
}
@@ -669,7 +669,7 @@ static unsigned int dec10_reg(DisasContext *dc)
default:
LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
dc->opcode, dc->src, dc->dst);
- cpu_abort(dc->env, "Unhandled opcode");
+ cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode");
break;
}
} else {
@@ -745,7 +745,7 @@ static unsigned int dec10_reg(DisasContext *dc)
default:
LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
dc->opcode, dc->src, dc->dst);
- cpu_abort(dc->env, "Unhandled opcode");
+ cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode");
break;
}
}
@@ -1105,7 +1105,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
default:
LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n",
dc->pc, size, dc->opcode, dc->src, dc->dst);
- cpu_abort(dc->env, "Unhandled opcode");
+ cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode");
break;
}
return insn_len;
@@ -1198,7 +1198,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
break;
default:
LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode);
- cpu_abort(dc->env, "Unhandled opcode");
+ cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode");
break;
}
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index d030793..a3ec4dc 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -95,6 +95,7 @@ static inline void load_seg_vm(CPUX86State *env, int seg, int selector)
static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr,
uint32_t *esp_ptr, int dpl)
{
+ X86CPU *cpu = x86_env_get_cpu(env);
int type, index, shift;
#if 0
@@ -112,11 +113,11 @@ static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr,
#endif
if (!(env->tr.flags & DESC_P_MASK)) {
- cpu_abort(env, "invalid tss");
+ cpu_abort(CPU(cpu), "invalid tss");
}
type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
if ((type & 7) != 1) {
- cpu_abort(env, "invalid tss type");
+ cpu_abort(CPU(cpu), "invalid tss type");
}
shift = type >> 3;
index = (dpl * 4 + 2) << shift;
@@ -782,6 +783,7 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,
static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level)
{
+ X86CPU *cpu = x86_env_get_cpu(env);
int index;
#if 0
@@ -790,7 +792,7 @@ static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level)
#endif
if (!(env->tr.flags & DESC_P_MASK)) {
- cpu_abort(env, "invalid tss");
+ cpu_abort(CPU(cpu), "invalid tss");
}
index = 8 * level + 4;
if ((index + 7) > env->tr.limit) {
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index daf0f2f..8f2b9fd 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -86,7 +86,7 @@ void lm32_cpu_do_interrupt(CPUState *cs)
log_cpu_state_mask(CPU_LOG_INT, cs, 0);
break;
default:
- cpu_abort(env, "unhandled exception type=%d\n",
+ cpu_abort(cs, "unhandled exception type=%d\n",
cs->exception_index);
break;
}
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 2e4951c..532345b 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -422,7 +422,7 @@ static void dec_divu(DisasContext *dc)
LOG_DIS("divu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
if (!(dc->env->features & LM32_FEATURE_DIVIDE)) {
- cpu_abort(dc->env, "hardware divider is not available\n");
+ cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware divider is not available\n");
}
l1 = gen_new_label();
@@ -500,7 +500,7 @@ static void dec_modu(DisasContext *dc)
LOG_DIS("modu r%d, r%d, %d\n", dc->r2, dc->r0, dc->r1);
if (!(dc->env->features & LM32_FEATURE_DIVIDE)) {
- cpu_abort(dc->env, "hardware divider is not available\n");
+ cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware divider is not available\n");
}
l1 = gen_new_label();
@@ -521,7 +521,7 @@ static void dec_mul(DisasContext *dc)
}
if (!(dc->env->features & LM32_FEATURE_MULTIPLY)) {
- cpu_abort(dc->env, "hardware multiplier is not available\n");
+ cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware multiplier is not available\n");
}
if (dc->format == OP_FMT_RI) {
@@ -590,7 +590,7 @@ static void dec_scall(DisasContext *dc)
} else if (dc->imm5 == 2) {
LOG_DIS("break\n");
} else {
- cpu_abort(dc->env, "invalid opcode\n");
+ cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "invalid opcode\n");
}
if (dc->imm5 == 7) {
@@ -647,10 +647,10 @@ static void dec_rcsr(DisasContext *dc)
case CSR_WP1:
case CSR_WP2:
case CSR_WP3:
- cpu_abort(dc->env, "invalid read access csr=%x\n", dc->csr);
+ cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "invalid read access csr=%x\n", dc->csr);
break;
default:
- cpu_abort(dc->env, "read_csr: unknown csr=%x\n", dc->csr);
+ cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "read_csr: unknown csr=%x\n", dc->csr);
break;
}
}
@@ -672,7 +672,7 @@ static void dec_sextb(DisasContext *dc)
LOG_DIS("sextb r%d, r%d\n", dc->r2, dc->r0);
if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) {
- cpu_abort(dc->env, "hardware sign extender is not available\n");
+ cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware sign extender is not available\n");
}
tcg_gen_ext8s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
@@ -683,7 +683,7 @@ static void dec_sexth(DisasContext *dc)
LOG_DIS("sexth r%d, r%d\n", dc->r2, dc->r0);
if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) {
- cpu_abort(dc->env, "hardware sign extender is not available\n");
+ cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware sign extender is not available\n");
}
tcg_gen_ext16s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
@@ -710,7 +710,7 @@ static void dec_sl(DisasContext *dc)
}
if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
- cpu_abort(dc->env, "hardware shifter is not available\n");
+ cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware shifter is not available\n");
}
if (dc->format == OP_FMT_RI) {
@@ -736,7 +736,7 @@ static void dec_sr(DisasContext *dc)
/* TODO: check r1 == 1 during runtime */
} else {
if (dc->imm5 != 1) {
- cpu_abort(dc->env, "hardware shifter is not available\n");
+ cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware shifter is not available\n");
}
}
}
@@ -764,7 +764,7 @@ static void dec_sru(DisasContext *dc)
/* TODO: check r1 == 1 during runtime */
} else {
if (dc->imm5 != 1) {
- cpu_abort(dc->env, "hardware shifter is not available\n");
+ cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware shifter is not available\n");
}
}
}
@@ -802,7 +802,7 @@ static void dec_user(DisasContext *dc)
{
LOG_DIS("user");
- cpu_abort(dc->env, "user insn undefined\n");
+ cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "user insn undefined\n");
}
static void dec_wcsr(DisasContext *dc)
@@ -868,7 +868,7 @@ static void dec_wcsr(DisasContext *dc)
case CSR_BP3:
no = dc->csr - CSR_BP0;
if (dc->env->num_bps <= no) {
- cpu_abort(dc->env, "breakpoint #%i is not available\n", no);
+ cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "breakpoint #%i is not available\n", no);
}
tcg_gen_mov_tl(cpu_bp[no], cpu_R[dc->r1]);
break;
@@ -878,16 +878,16 @@ static void dec_wcsr(DisasContext *dc)
case CSR_WP3:
no = dc->csr - CSR_WP0;
if (dc->env->num_wps <= no) {
- cpu_abort(dc->env, "watchpoint #%i is not available\n", no);
+ cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "watchpoint #%i is not available\n", no);
}
tcg_gen_mov_tl(cpu_wp[no], cpu_R[dc->r1]);
break;
case CSR_CC:
case CSR_CFG:
- cpu_abort(dc->env, "invalid write access csr=%x\n", dc->csr);
+ cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "invalid write access csr=%x\n", dc->csr);
break;
default:
- cpu_abort(dc->env, "write_csr unknown csr=%x\n", dc->csr);
+ cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "write_csr unknown csr=%x\n", dc->csr);
break;
}
}
@@ -933,7 +933,7 @@ static void dec_xor(DisasContext *dc)
static void dec_ill(DisasContext *dc)
{
- cpu_abort(dc->env, "unknown opcode 0x%02x\n", dc->opcode);
+ cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "unknown opcode 0x%02x\n", dc->opcode);
}
typedef void (*DecoderInfo)(DisasContext *dc);
@@ -967,7 +967,7 @@ static inline void decode(DisasContext *dc, uint32_t ir)
LOG_DIS("nr_nops=%d\t", dc->nr_nops);
dc->nr_nops++;
if (dc->nr_nops > 4) {
- cpu_abort(dc->env, "fetching nop sequence\n");
+ cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "fetching nop sequence\n");
}
}
@@ -1038,7 +1038,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
dc->nr_nops = 0;
if (pc_start & 3) {
- cpu_abort(env, "LM32: unaligned PC=%x\n", pc_start);
+ cpu_abort(cs, "LM32: unaligned PC=%x\n", pc_start);
}
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 219e8b3..5767390 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -132,6 +132,7 @@ void m68k_cpu_init_gdb(M68kCPU *cpu)
void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op)
{
+ M68kCPU *cpu = m68k_env_get_cpu(env);
int flags;
uint32_t src;
uint32_t dest;
@@ -204,7 +205,7 @@ void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op)
flags |= CCF_C;
break;
default:
- cpu_abort(env, "Bad CC_OP %d", cc_op);
+ cpu_abort(CPU(cpu), "Bad CC_OP %d", cc_op);
}
env->cc_op = CC_OP_FLAGS;
env->cc_dest = flags;
@@ -212,6 +213,8 @@ void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op)
void HELPER(movec)(CPUM68KState *env, uint32_t reg, uint32_t val)
{
+ M68kCPU *cpu = m68k_env_get_cpu(env);
+
switch (reg) {
case 0x02: /* CACR */
env->cacr = val;
@@ -225,7 +228,7 @@ void HELPER(movec)(CPUM68KState *env, uint32_t reg, uint32_t val)
break;
/* TODO: Implement control registers. */
default:
- cpu_abort(env, "Unimplemented control register write 0x%x = 0x%x\n",
+ cpu_abort(CPU(cpu), "Unimplemented control register write 0x%x = 0x%x\n",
reg, val);
}
}
diff --git a/target-m68k/m68k-semi.c b/target-m68k/m68k-semi.c
index 2dea3ca..9dffe8d 100644
--- a/target-m68k/m68k-semi.c
+++ b/target-m68k/m68k-semi.c
@@ -461,7 +461,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr)
#endif
return;
default:
- cpu_abort(env, "Unsupported semihosting syscall %d\n", nr);
+ cpu_abort(CPU(m68k_env_get_cpu(env)), "Unsupported semihosting syscall %d\n", nr);
result = 0;
}
failed:
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index c005e10..bee0d25 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -894,8 +894,10 @@ DISAS_INSN(undef_fpu)
DISAS_INSN(undef)
{
+ M68kCPU *cpu = m68k_env_get_cpu(env);
+
gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);
- cpu_abort(env, "Illegal instruction: %04x @ %08x", insn, s->pc - 2);
+ cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2);
}
DISAS_INSN(mulw)
diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
index 50aa55a..59c9ad5 100644
--- a/target-microblaze/helper.c
+++ b/target-microblaze/helper.c
@@ -98,7 +98,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
}
if (cs->exception_index == EXCP_MMU) {
- cpu_abort(env, "recursive faults\n");
+ cpu_abort(cs, "recursive faults\n");
}
/* TLB miss. */
@@ -259,7 +259,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
env->sregs[SR_PC] = env->btarget;
break;
default:
- cpu_abort(env, "unhandled exception type=%d\n",
+ cpu_abort(cs, "unhandled exception type=%d\n",
cs->exception_index);
break;
}
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 31eef0f..4471f5a 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -364,7 +364,7 @@ static void dec_pattern(DisasContext *dc)
}
break;
default:
- cpu_abort(dc->env,
+ cpu_abort(CPU(mb_env_get_cpu(dc->env)),
"unsupported pattern insn opcode=%x\n", dc->opcode);
break;
}
@@ -438,9 +438,11 @@ static inline void msr_write(DisasContext *dc, TCGv v)
static void dec_msr(DisasContext *dc)
{
+ MicroBlazeCPU *cpu = mb_env_get_cpu(dc->env);
+ CPUState *cs = CPU(cpu);
TCGv t0, t1;
unsigned int sr, to, rn;
- int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
+ int mem_index = cpu_mmu_index(cs);
sr = dc->imm & ((1 << 14) - 1);
to = dc->imm & (1 << 14);
@@ -534,7 +536,7 @@ static void dec_msr(DisasContext *dc)
tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, shr));
break;
default:
- cpu_abort(dc->env, "unknown mts reg %x\n", sr);
+ cpu_abort(CPU(mb_env_get_cpu(dc->env)), "unknown mts reg %x\n", sr);
break;
}
} else {
@@ -583,7 +585,7 @@ static void dec_msr(DisasContext *dc)
cpu_env, offsetof(CPUMBState, pvr.regs[rn]));
break;
default:
- cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
+ cpu_abort(cs, "unknown mfs reg %x\n", sr);
break;
}
}
@@ -681,7 +683,7 @@ static void dec_mul(DisasContext *dc)
t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
break;
default:
- cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
+ cpu_abort(CPU(mb_env_get_cpu(dc->env)), "unknown MUL insn %x\n", subcode);
break;
}
done:
@@ -749,9 +751,11 @@ static void dec_barrel(DisasContext *dc)
static void dec_bit(DisasContext *dc)
{
+ MicroBlazeCPU *cpu = mb_env_get_cpu(dc->env);
+ CPUState *cs = CPU(cpu);
TCGv t0, t1;
unsigned int op;
- int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
+ int mem_index = cpu_mmu_index(cs);
op = dc->ir & ((1 << 9) - 1);
switch (op) {
@@ -846,8 +850,8 @@ static void dec_bit(DisasContext *dc)
tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16);
break;
default:
- cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
- dc->pc, op, dc->rd, dc->ra, dc->rb);
+ cpu_abort(cs, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
+ dc->pc, op, dc->rd, dc->ra, dc->rb);
break;
}
}
@@ -874,7 +878,9 @@ static void dec_imm(DisasContext *dc)
static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
unsigned int size)
{
- int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
+ MicroBlazeCPU *cpu = mb_env_get_cpu(dc->env);
+ CPUState *cs = CPU(cpu);
+ int mem_index = cpu_mmu_index(cs);
if (size == 1) {
tcg_gen_qemu_ld8u(dst, addr, mem_index);
@@ -883,7 +889,7 @@ static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
} else if (size == 4) {
tcg_gen_qemu_ld32u(dst, addr, mem_index);
} else
- cpu_abort(dc->env, "Incorrect load size %d\n", size);
+ cpu_abort(cs, "Incorrect load size %d\n", size);
}
static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
@@ -1026,7 +1032,7 @@ static void dec_load(DisasContext *dc)
}
break;
default:
- cpu_abort(dc->env, "Invalid reverse size\n");
+ cpu_abort(CPU(mb_env_get_cpu(dc->env)), "Invalid reverse size\n");
break;
}
}
@@ -1093,7 +1099,9 @@ static void dec_load(DisasContext *dc)
static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
unsigned int size)
{
- int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
+ MicroBlazeCPU *cpu = mb_env_get_cpu(dc->env);
+ CPUState *cs = CPU(cpu);
+ int mem_index = cpu_mmu_index(cs);
if (size == 1)
tcg_gen_qemu_st8(val, addr, mem_index);
@@ -1101,8 +1109,9 @@ static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
tcg_gen_qemu_st16(val, addr, mem_index);
} else if (size == 4) {
tcg_gen_qemu_st32(val, addr, mem_index);
- } else
- cpu_abort(dc->env, "Incorrect store size %d\n", size);
+ } else {
+ cpu_abort(cs, "Incorrect store size %d\n", size);
+ }
}
static void dec_store(DisasContext *dc)
@@ -1188,7 +1197,7 @@ static void dec_store(DisasContext *dc)
}
break;
default:
- cpu_abort(dc->env, "Invalid reverse size\n");
+ cpu_abort(CPU(mb_env_get_cpu(dc->env)), "Invalid reverse size\n");
break;
}
@@ -1257,7 +1266,7 @@ static inline void eval_cc(DisasContext *dc, unsigned int cc,
tcg_gen_setcond_tl(TCG_COND_GT, d, a, b);
break;
default:
- cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
+ cpu_abort(CPU(mb_env_get_cpu(dc->env)), "Unknown condition code %x.\n", cc);
break;
}
}
@@ -1701,8 +1710,9 @@ static inline void decode(DisasContext *dc, uint32_t ir)
LOG_DIS("nr_nops=%d\t", dc->nr_nops);
dc->nr_nops++;
- if (dc->nr_nops > 4)
- cpu_abort(dc->env, "fetching nop sequence\n");
+ if (dc->nr_nops > 4) {
+ cpu_abort(CPU(mb_env_get_cpu(dc->env)), "fetching nop sequence\n");
+ }
}
/* bit 2 seems to indicate insn type. */
dc->type_b = ir & (1 << 29);
@@ -1773,8 +1783,9 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
dc->abort_at_next_insn = 0;
dc->nr_nops = 0;
- if (pc_start & 3)
- cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
+ if (pc_start & 3) {
+ cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start);
+ }
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
#if !SIM_COMPAT
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index dc0c1cc..14f727f 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1344,6 +1344,7 @@ void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
{
+ MIPSCPU *cpu = mips_env_get_cpu(env);
uint32_t val, old;
uint32_t mask = env->CP0_Status_rw_bitmask;
@@ -1365,7 +1366,9 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
case MIPS_HFLAG_KM: qemu_log("\n"); break;
- default: cpu_abort(env, "Invalid MMU mode!\n"); break;
+ default:
+ cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
+ break;
}
}
}
@@ -1973,6 +1976,8 @@ static void debug_pre_eret(CPUMIPSState *env)
static void debug_post_eret(CPUMIPSState *env)
{
+ MIPSCPU *cpu = mips_env_get_cpu(env);
+
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
env->active_tc.PC, env->CP0_EPC);
@@ -1984,7 +1989,9 @@ static void debug_post_eret(CPUMIPSState *env)
case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
case MIPS_HFLAG_KM: qemu_log("\n"); break;
- default: cpu_abort(env, "Invalid MMU mode!\n"); break;
+ default:
+ cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
+ break;
}
}
}
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c45b1b2..4d90ed5 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -586,6 +586,8 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
{
+ MIPSCPU *cpu = mips_env_get_cpu(env);
+
env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
switch (def->mmu_type) {
@@ -602,7 +604,7 @@ static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
case MMU_TYPE_R6000:
case MMU_TYPE_R8000:
default:
- cpu_abort(env, "MMU type not supported\n");
+ cpu_abort(CPU(cpu), "MMU type not supported\n");
}
}
#endif /* CONFIG_USER_ONLY */
diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
index 64f2ca6..52bcc6e 100644
--- a/target-openrisc/interrupt.c
+++ b/target-openrisc/interrupt.c
@@ -69,7 +69,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) {
env->pc = (cs->exception_index << 8);
} else {
- cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
+ cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
}
#endif
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 3b03ae6..ea121dd 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -2051,7 +2051,7 @@ static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
}
}
- cpu_abort(env, "Unknown TLBe: %d\n", id);
+ cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
return 0;
}
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index 7ced42d..ef67b0e 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -240,7 +240,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
break;
default:
/* Should never occur */
- cpu_abort(env, "Invalid program exception %d. Aborting\n",
+ cpu_abort(cs, "Invalid program exception %d. Aborting\n",
env->error_code);
break;
}
@@ -300,26 +300,26 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
break;
}
/* XXX: TODO */
- cpu_abort(env, "Debug exception is not implemented yet !\n");
+ cpu_abort(cs, "Debug exception is not implemented yet !\n");
goto store_next;
case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */
env->spr[SPR_BOOKE_ESR] = ESR_SPV;
goto store_current;
case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
/* XXX: TODO */
- cpu_abort(env, "Embedded floating point data exception "
+ cpu_abort(cs, "Embedded floating point data exception "
"is not implemented yet !\n");
env->spr[SPR_BOOKE_ESR] = ESR_SPV;
goto store_next;
case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
/* XXX: TODO */
- cpu_abort(env, "Embedded floating point round exception "
+ cpu_abort(cs, "Embedded floating point round exception "
"is not implemented yet !\n");
env->spr[SPR_BOOKE_ESR] = ESR_SPV;
goto store_next;
case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
/* XXX: TODO */
- cpu_abort(env,
+ cpu_abort(cs,
"Performance counter exception is not implemented yet !\n");
goto store_next;
case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
@@ -396,15 +396,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
goto store_next;
case POWERPC_EXCP_IO: /* IO error exception */
/* XXX: TODO */
- cpu_abort(env, "601 IO error exception is not implemented yet !\n");
+ cpu_abort(cs, "601 IO error exception is not implemented yet !\n");
goto store_next;
case POWERPC_EXCP_RUNM: /* Run mode exception */
/* XXX: TODO */
- cpu_abort(env, "601 run mode exception is not implemented yet !\n");
+ cpu_abort(cs, "601 run mode exception is not implemented yet !\n");
goto store_next;
case POWERPC_EXCP_EMUL: /* Emulation trap exception */
/* XXX: TODO */
- cpu_abort(env, "602 emulation trap exception "
+ cpu_abort(cs, "602 emulation trap exception "
"is not implemented yet !\n");
goto store_next;
case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
@@ -422,7 +422,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
case POWERPC_EXCP_74xx:
goto tlb_miss_74xx;
default:
- cpu_abort(env, "Invalid instruction TLB miss exception\n");
+ cpu_abort(cs, "Invalid instruction TLB miss exception\n");
break;
}
break;
@@ -441,7 +441,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
case POWERPC_EXCP_74xx:
goto tlb_miss_74xx;
default:
- cpu_abort(env, "Invalid data load TLB miss exception\n");
+ cpu_abort(cs, "Invalid data load TLB miss exception\n");
break;
}
break;
@@ -527,30 +527,30 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
msr |= env->error_code; /* key bit */
break;
default:
- cpu_abort(env, "Invalid data store TLB miss exception\n");
+ cpu_abort(cs, "Invalid data store TLB miss exception\n");
break;
}
goto store_next;
case POWERPC_EXCP_FPA: /* Floating-point assist exception */
/* XXX: TODO */
- cpu_abort(env, "Floating point assist exception "
+ cpu_abort(cs, "Floating point assist exception "
"is not implemented yet !\n");
goto store_next;
case POWERPC_EXCP_DABR: /* Data address breakpoint */
/* XXX: TODO */
- cpu_abort(env, "DABR exception is not implemented yet !\n");
+ cpu_abort(cs, "DABR exception is not implemented yet !\n");
goto store_next;
case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
/* XXX: TODO */
- cpu_abort(env, "IABR exception is not implemented yet !\n");
+ cpu_abort(cs, "IABR exception is not implemented yet !\n");
goto store_next;
case POWERPC_EXCP_SMI: /* System management interrupt */
/* XXX: TODO */
- cpu_abort(env, "SMI exception is not implemented yet !\n");
+ cpu_abort(cs, "SMI exception is not implemented yet !\n");
goto store_next;
case POWERPC_EXCP_THERM: /* Thermal interrupt */
/* XXX: TODO */
- cpu_abort(env, "Thermal management exception "
+ cpu_abort(cs, "Thermal management exception "
"is not implemented yet !\n");
goto store_next;
case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
@@ -558,36 +558,36 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
new_msr |= (target_ulong)MSR_HVB;
}
/* XXX: TODO */
- cpu_abort(env,
+ cpu_abort(cs,
"Performance counter exception is not implemented yet !\n");
goto store_next;
case POWERPC_EXCP_VPUA: /* Vector assist exception */
/* XXX: TODO */
- cpu_abort(env, "VPU assist exception is not implemented yet !\n");
+ cpu_abort(cs, "VPU assist exception is not implemented yet !\n");
goto store_next;
case POWERPC_EXCP_SOFTP: /* Soft patch exception */
/* XXX: TODO */
- cpu_abort(env,
+ cpu_abort(cs,
"970 soft-patch exception is not implemented yet !\n");
goto store_next;
case POWERPC_EXCP_MAINT: /* Maintenance exception */
/* XXX: TODO */
- cpu_abort(env,
+ cpu_abort(cs,
"970 maintenance exception is not implemented yet !\n");
goto store_next;
case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
/* XXX: TODO */
- cpu_abort(env, "Maskable external exception "
+ cpu_abort(cs, "Maskable external exception "
"is not implemented yet !\n");
goto store_next;
case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
/* XXX: TODO */
- cpu_abort(env, "Non maskable external exception "
+ cpu_abort(cs, "Non maskable external exception "
"is not implemented yet !\n");
goto store_next;
default:
excp_invalid:
- cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
+ cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
break;
store_current:
/* save current instruction location */
@@ -629,7 +629,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
/* Jump to handler */
vector = env->excp_vectors[excp];
if (vector == (target_ulong)-1ULL) {
- cpu_abort(env, "Raised an exception without defined vector %d\n",
+ cpu_abort(cs, "Raised an exception without defined vector %d\n",
excp);
}
vector |= env->excp_prefix;
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index ff70b38..f4dac00 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -746,9 +746,11 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
void store_40x_sler(CPUPPCState *env, uint32_t val)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
/* XXX: TO BE FIXED */
if (val != 0x00000000) {
- cpu_abort(env, "Little-endian regions are not supported by now\n");
+ cpu_abort(CPU(cpu), "Little-endian regions are not supported by now\n");
}
env->spr[SPR_405_SLER] = val;
}
@@ -1344,6 +1346,7 @@ static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx,
static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
target_ulong eaddr, int rw, int access_type)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
int ret = -1;
bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0)
|| (access_type != ACCESS_CODE && msr_dr == 0);
@@ -1388,17 +1391,17 @@ static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
break;
case POWERPC_MMU_MPC8xx:
/* XXX: TODO */
- cpu_abort(env, "MPC8xx MMU model is not implemented\n");
+ cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");
break;
case POWERPC_MMU_REAL:
if (real_mode) {
ret = check_physical(env, ctx, eaddr, rw);
} else {
- cpu_abort(env, "PowerPC in real mode do not do any translation\n");
+ cpu_abort(CPU(cpu), "PowerPC in real mode do not do any translation\n");
}
return -1;
default:
- cpu_abort(env, "Unknown or invalid MMU model\n");
+ cpu_abort(CPU(cpu), "Unknown or invalid MMU model\n");
return -1;
}
#if 0
@@ -1543,14 +1546,14 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
return -1;
case POWERPC_MMU_MPC8xx:
/* XXX: TODO */
- cpu_abort(env, "MPC8xx MMU model is not implemented\n");
+ cpu_abort(cs, "MPC8xx MMU model is not implemented\n");
break;
case POWERPC_MMU_REAL:
- cpu_abort(env, "PowerPC in real mode should never raise "
+ cpu_abort(cs, "PowerPC in real mode should never raise "
"any MMU exceptions\n");
return -1;
default:
- cpu_abort(env, "Unknown or invalid MMU model\n");
+ cpu_abort(cs, "Unknown or invalid MMU model\n");
return -1;
}
break;
@@ -1623,7 +1626,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
break;
case POWERPC_MMU_MPC8xx:
/* XXX: TODO */
- cpu_abort(env, "MPC8xx MMU model is not implemented\n");
+ cpu_abort(cs, "MPC8xx MMU model is not implemented\n");
break;
case POWERPC_MMU_BOOKE206:
booke206_update_mas_tlb_miss(env, address, rw);
@@ -1635,11 +1638,11 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0;
return -1;
case POWERPC_MMU_REAL:
- cpu_abort(env, "PowerPC in real mode should never raise "
+ cpu_abort(cs, "PowerPC in real mode should never raise "
"any MMU exceptions\n");
return -1;
default:
- cpu_abort(env, "Unknown or invalid MMU model\n");
+ cpu_abort(cs, "Unknown or invalid MMU model\n");
return -1;
}
break;
@@ -1893,6 +1896,8 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value)
/* TLB management */
void ppc_tlb_invalidate_all(CPUPPCState *env)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_6xx:
case POWERPC_MMU_SOFT_74xx:
@@ -1903,11 +1908,11 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
ppc4xx_tlb_invalidate_all(env);
break;
case POWERPC_MMU_REAL:
- cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
+ cpu_abort(CPU(cpu), "No TLB for PowerPC 4xx in real mode\n");
break;
case POWERPC_MMU_MPC8xx:
/* XXX: TODO */
- cpu_abort(env, "MPC8xx MMU model is not implemented\n");
+ cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");
break;
case POWERPC_MMU_BOOKE:
tlb_flush(env, 1);
@@ -1927,7 +1932,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
break;
default:
/* XXX: TODO */
- cpu_abort(env, "Unknown MMU model\n");
+ cpu_abort(CPU(cpu), "Unknown MMU model\n");
break;
}
}
@@ -1935,6 +1940,8 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
{
#if !defined(FLUSH_ALL_TLBS)
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
addr &= TARGET_PAGE_MASK;
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_6xx:
@@ -1949,19 +1956,19 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
break;
case POWERPC_MMU_REAL:
- cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
+ cpu_abort(CPU(cpu), "No TLB for PowerPC 4xx in real mode\n");
break;
case POWERPC_MMU_MPC8xx:
/* XXX: TODO */
- cpu_abort(env, "MPC8xx MMU model is not implemented\n");
+ cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");
break;
case POWERPC_MMU_BOOKE:
/* XXX: TODO */
- cpu_abort(env, "BookE MMU model is not implemented\n");
+ cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n");
break;
case POWERPC_MMU_BOOKE206:
/* XXX: TODO */
- cpu_abort(env, "BookE 2.06 MMU model is not implemented\n");
+ cpu_abort(CPU(cpu), "BookE 2.06 MMU model is not implemented\n");
break;
case POWERPC_MMU_32B:
case POWERPC_MMU_601:
@@ -2002,7 +2009,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
#endif /* defined(TARGET_PPC64) */
default:
/* XXX: TODO */
- cpu_abort(env, "Unknown MMU model\n");
+ cpu_abort(CPU(cpu), "Unknown MMU model\n");
break;
}
#else
@@ -2316,6 +2323,7 @@ target_ulong helper_4xx_tlbre_lo(CPUPPCState *env, target_ulong entry)
void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
target_ulong val)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
ppcemb_tlb_t *tlb;
target_ulong page, end;
@@ -2339,7 +2347,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
* of the ppc or ppc64 one
*/
if ((val & PPC4XX_TLBHI_V) && tlb->size < TARGET_PAGE_SIZE) {
- cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
+ cpu_abort(CPU(cpu), "TLB size " TARGET_FMT_lu " < %u "
"are not supported (%d)\n",
tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
}
@@ -2348,7 +2356,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
tlb->prot |= PAGE_VALID;
if (val & PPC4XX_TLBHI_E) {
/* XXX: TO BE FIXED */
- cpu_abort(env,
+ cpu_abort(CPU(cpu),
"Little-endian TLB entries are not supported by now\n");
}
} else {
@@ -2544,6 +2552,7 @@ target_ulong helper_440_tlbsx(CPUPPCState *env, target_ulong address)
static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
uint32_t tlbncfg = 0;
int esel = (env->spr[SPR_BOOKE_MAS0] & MAS0_ESEL_MASK) >> MAS0_ESEL_SHIFT;
int ea = (env->spr[SPR_BOOKE_MAS2] & MAS2_EPN_MASK);
@@ -2553,7 +2562,7 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env)
tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlb];
if ((tlbncfg & TLBnCFG_HES) && (env->spr[SPR_BOOKE_MAS0] & MAS0_HES)) {
- cpu_abort(env, "we don't support HES yet\n");
+ cpu_abort(CPU(cpu), "we don't support HES yet\n");
}
return booke206_get_tlbm(env, tlb, ea, esel);
@@ -2568,6 +2577,7 @@ void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid)
void helper_booke206_tlbwe(CPUPPCState *env)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
uint32_t tlbncfg, tlbn;
ppcmas_tlb_t *tlb;
uint32_t size_tlb, size_ps;
@@ -2621,7 +2631,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
}
if (msr_gs) {
- cpu_abort(env, "missing HV implementation\n");
+ cpu_abort(CPU(cpu), "missing HV implementation\n");
}
tlb->mas7_3 = ((uint64_t)env->spr[SPR_BOOKE_MAS7] << 32) |
env->spr[SPR_BOOKE_MAS3];
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index db5e526..1df82c5 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -4424,6 +4424,7 @@ enum fsl_e500_version {
static void init_proc_e500 (CPUPPCState *env, int version)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
uint32_t tlbncfg[2];
uint64_t ivor_mask;
uint64_t ivpr_mask = 0xFFFF0000ULL;
@@ -4482,7 +4483,7 @@ static void init_proc_e500 (CPUPPCState *env, int version)
tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
break;
default:
- cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
+ cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
}
#endif
/* Cache sizes */
@@ -4499,7 +4500,7 @@ static void init_proc_e500 (CPUPPCState *env, int version)
l1cfg0 |= 0x1000000; /* 64 byte cache block size */
break;
default:
- cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
+ cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
}
gen_spr_BookE206(env, 0x000000DF, tlbncfg);
/* XXX : not implemented */
diff --git a/target-s390x/cc_helper.c b/target-s390x/cc_helper.c
index d845f20..9e676a5 100644
--- a/target-s390x/cc_helper.c
+++ b/target-s390x/cc_helper.c
@@ -407,6 +407,7 @@ static uint32_t cc_calc_flogr(uint64_t dst)
static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
uint64_t src, uint64_t dst, uint64_t vr)
{
+ S390CPU *cpu = s390_env_get_cpu(env);
uint32_t r = 0;
switch (cc_op) {
@@ -524,7 +525,7 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
break;
default:
- cpu_abort(env, "Unknown CC operation: %s\n", cc_name(cc_op));
+ cpu_abort(CPU(cpu), "Unknown CC operation: %s\n", cc_name(cc_op));
}
HELPER_LOG("%s: %15s 0x%016lx 0x%016lx 0x%016lx = %d\n", __func__,
diff --git a/target-s390x/fpu_helper.c b/target-s390x/fpu_helper.c
index 94375b6..3e9c7b2 100644
--- a/target-s390x/fpu_helper.c
+++ b/target-s390x/fpu_helper.c
@@ -80,6 +80,8 @@ static void handle_exceptions(CPUS390XState *env, uintptr_t retaddr)
static inline int float_comp_to_cc(CPUS390XState *env, int float_compare)
{
+ S390CPU *cpu = s390_env_get_cpu(env);
+
switch (float_compare) {
case float_relation_equal:
return 0;
@@ -90,7 +92,7 @@ static inline int float_comp_to_cc(CPUS390XState *env, int float_compare)
case float_relation_unordered:
return 3;
default:
- cpu_abort(env, "unknown return value for float compare\n");
+ cpu_abort(CPU(cpu), "unknown return value for float compare\n");
}
}
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index 207af52..96f57d2 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -116,6 +116,7 @@ static void trigger_pgm_exception(CPUS390XState *env, uint32_t code,
static int trans_bits(CPUS390XState *env, uint64_t mode)
{
+ S390CPU *cpu = s390_env_get_cpu(env);
int bits = 0;
switch (mode) {
@@ -129,7 +130,7 @@ static int trans_bits(CPUS390XState *env, uint64_t mode)
bits = 3;
break;
default:
- cpu_abort(env, "unknown asc mode\n");
+ cpu_abort(CPU(cpu), "unknown asc mode\n");
break;
}
@@ -474,13 +475,14 @@ static uint64_t get_psw_mask(CPUS390XState *env)
static LowCore *cpu_map_lowcore(CPUS390XState *env)
{
+ S390CPU *cpu = s390_env_get_cpu(env);
LowCore *lowcore;
hwaddr len = sizeof(LowCore);
lowcore = cpu_physical_memory_map(env->psa, &len, 1);
if (len < sizeof(LowCore)) {
- cpu_abort(env, "Could not map lowcore\n");
+ cpu_abort(CPU(cpu), "Could not map lowcore\n");
}
return lowcore;
@@ -578,16 +580,17 @@ static void do_program_interrupt(CPUS390XState *env)
static void do_ext_interrupt(CPUS390XState *env)
{
+ S390CPU *cpu = s390_env_get_cpu(env);
uint64_t mask, addr;
LowCore *lowcore;
ExtQueue *q;
if (!(env->psw.mask & PSW_MASK_EXT)) {
- cpu_abort(env, "Ext int w/o ext mask\n");
+ cpu_abort(CPU(cpu), "Ext int w/o ext mask\n");
}
if (env->ext_index < 0 || env->ext_index > MAX_EXT_QUEUE) {
- cpu_abort(env, "Ext queue overrun: %d\n", env->ext_index);
+ cpu_abort(CPU(cpu), "Ext queue overrun: %d\n", env->ext_index);
}
q = &env->ext_queue[env->ext_index];
@@ -617,6 +620,7 @@ static void do_ext_interrupt(CPUS390XState *env)
static void do_io_interrupt(CPUS390XState *env)
{
+ S390CPU *cpu = s390_env_get_cpu(env);
LowCore *lowcore;
IOIntQueue *q;
uint8_t isc;
@@ -624,7 +628,7 @@ static void do_io_interrupt(CPUS390XState *env)
int found = 0;
if (!(env->psw.mask & PSW_MASK_IO)) {
- cpu_abort(env, "I/O int w/o I/O mask\n");
+ cpu_abort(CPU(cpu), "I/O int w/o I/O mask\n");
}
for (isc = 0; isc < ARRAY_SIZE(env->io_index); isc++) {
@@ -634,7 +638,7 @@ static void do_io_interrupt(CPUS390XState *env)
continue;
}
if (env->io_index[isc] > MAX_IO_QUEUE) {
- cpu_abort(env, "I/O queue overrun for isc %d: %d\n",
+ cpu_abort(CPU(cpu), "I/O queue overrun for isc %d: %d\n",
isc, env->io_index[isc]);
}
@@ -681,24 +685,25 @@ static void do_io_interrupt(CPUS390XState *env)
static void do_mchk_interrupt(CPUS390XState *env)
{
+ S390CPU *cpu = s390_env_get_cpu(env);
uint64_t mask, addr;
LowCore *lowcore;
MchkQueue *q;
int i;
if (!(env->psw.mask & PSW_MASK_MCHECK)) {
- cpu_abort(env, "Machine check w/o mchk mask\n");
+ cpu_abort(CPU(cpu), "Machine check w/o mchk mask\n");
}
if (env->mchk_index < 0 || env->mchk_index > MAX_MCHK_QUEUE) {
- cpu_abort(env, "Mchk queue overrun: %d\n", env->mchk_index);
+ cpu_abort(CPU(cpu), "Mchk queue overrun: %d\n", env->mchk_index);
}
q = &env->mchk_queue[env->mchk_index];
if (q->type != 1) {
/* Don't know how to handle this... */
- cpu_abort(env, "Unknown machine check type %d\n", q->type);
+ cpu_abort(CPU(cpu), "Unknown machine check type %d\n", q->type);
}
if (!(env->cregs[14] & (1 << 28))) {
/* CRW machine checks disabled */
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index 6a79385..cd84337 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -72,6 +72,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest,
uint8_t byte)
{
+ S390CPU *cpu = s390_env_get_cpu(env);
hwaddr dest_phys;
hwaddr len = l;
void *dest_p;
@@ -80,7 +81,7 @@ static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest,
if (mmu_translate(env, dest, 1, asc, &dest_phys, &flags)) {
cpu_stb_data(env, dest, byte);
- cpu_abort(env, "should never reach here");
+ cpu_abort(CPU(cpu), "should never reach here");
}
dest_phys |= dest & ~TARGET_PAGE_MASK;
@@ -94,6 +95,7 @@ static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest,
static void mvc_fast_memmove(CPUS390XState *env, uint32_t l, uint64_t dest,
uint64_t src)
{
+ S390CPU *cpu = s390_env_get_cpu(env);
hwaddr dest_phys;
hwaddr src_phys;
hwaddr len = l;
@@ -104,13 +106,13 @@ static void mvc_fast_memmove(CPUS390XState *env, uint32_t l, uint64_t dest,
if (mmu_translate(env, dest, 1, asc, &dest_phys, &flags)) {
cpu_stb_data(env, dest, 0);
- cpu_abort(env, "should never reach here");
+ cpu_abort(CPU(cpu), "should never reach here");
}
dest_phys |= dest & ~TARGET_PAGE_MASK;
if (mmu_translate(env, src, 0, asc, &src_phys, &flags)) {
cpu_ldub_data(env, src);
- cpu_abort(env, "should never reach here");
+ cpu_abort(CPU(cpu), "should never reach here");
}
src_phys |= src & ~TARGET_PAGE_MASK;
@@ -483,6 +485,7 @@ static uint32_t helper_icm(CPUS390XState *env, uint32_t r1, uint64_t address,
uint32_t HELPER(ex)(CPUS390XState *env, uint32_t cc, uint64_t v1,
uint64_t addr, uint64_t ret)
{
+ S390CPU *cpu = s390_env_get_cpu(env);
uint16_t insn = cpu_lduw_code(env, addr);
HELPER_LOG("%s: v1 0x%lx addr 0x%lx insn 0x%x\n", __func__, v1, addr,
@@ -534,7 +537,7 @@ uint32_t HELPER(ex)(CPUS390XState *env, uint32_t cc, uint64_t v1,
cc = helper_icm(env, r1, get_address(env, 0, b2, d2), r3);
} else {
abort:
- cpu_abort(env, "EXECUTE on instruction prefix 0x%x not implemented\n",
+ cpu_abort(CPU(cpu), "EXECUTE on instruction prefix 0x%x not implemented\n",
insn);
}
return cc;
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index b444da1..7add92d 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -234,15 +234,21 @@ static void update_itlb_use(CPUSH4State * env, int itlbnb)
static int itlb_replacement(CPUSH4State * env)
{
- if ((env->mmucr & 0xe0000000) == 0xe0000000)
+ SuperHCPU *cpu = sh_env_get_cpu(env);
+
+ if ((env->mmucr & 0xe0000000) == 0xe0000000) {
return 0;
- if ((env->mmucr & 0x98000000) == 0x18000000)
+ }
+ if ((env->mmucr & 0x98000000) == 0x18000000) {
return 1;
- if ((env->mmucr & 0x54000000) == 0x04000000)
+ }
+ if ((env->mmucr & 0x54000000) == 0x04000000) {
return 2;
- if ((env->mmucr & 0x2c000000) == 0x00000000)
+ }
+ if ((env->mmucr & 0x2c000000) == 0x00000000) {
return 3;
- cpu_abort(env, "Unhandled itlb_replacement");
+ }
+ cpu_abort(CPU(cpu), "Unhandled itlb_replacement");
}
/* Find the corresponding entry in the right TLB
@@ -498,7 +504,7 @@ int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
cs->exception_index = 0x100;
break;
default:
- cpu_abort(env, "Unhandled MMU fault");
+ cpu_abort(cs, "Unhandled MMU fault");
}
return 1;
}
@@ -522,6 +528,7 @@ hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
void cpu_load_tlb(CPUSH4State * env)
{
+ SuperHCPU *cpu = sh_env_get_cpu(env);
int n = cpu_mmucr_urc(env->mmucr);
tlb_t * entry = &env->utlb[n];
@@ -551,7 +558,7 @@ void cpu_load_tlb(CPUSH4State * env)
entry->size = 1024 * 1024; /* 1M */
break;
default:
- cpu_abort(env, "Unhandled load_tlb");
+ cpu_abort(CPU(cpu), "Unhandled load_tlb");
break;
}
entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
index b3ce7ba..720a97b 100644
--- a/target-sh4/op_helper.c
+++ b/target-sh4/op_helper.c
@@ -58,8 +58,10 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
void helper_ldtlb(CPUSH4State *env)
{
#ifdef CONFIG_USER_ONLY
+ SuperHCPU *cpu = sh_env_get_cpu(env);
+
/* XXXXX */
- cpu_abort(env, "Unhandled ldtlb");
+ cpu_abort(CPU(cpu), "Unhandled ldtlb");
#else
cpu_load_tlb(env);
#endif
diff --git a/target-sparc/int32_helper.c b/target-sparc/int32_helper.c
index f350a90..7c380ba 100644
--- a/target-sparc/int32_helper.c
+++ b/target-sparc/int32_helper.c
@@ -109,7 +109,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
env->def->features & CPU_FEATURE_TA0_SHUTDOWN) {
qemu_system_shutdown_request();
} else {
- cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
+ cpu_abort(cs, "Trap 0x%02x while interrupts disabled, Error state",
cs->exception_index);
}
return;
diff --git a/target-sparc/int64_helper.c b/target-sparc/int64_helper.c
index 1744245..bf24232 100644
--- a/target-sparc/int64_helper.c
+++ b/target-sparc/int64_helper.c
@@ -111,7 +111,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
#endif
#if !defined(CONFIG_USER_ONLY)
if (env->tl >= env->maxtl) {
- cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
+ cpu_abort(cs, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
" Error state", cs->exception_index, env->tl, env->maxtl);
return;
}
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index eece271..f91ed93 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -236,26 +236,22 @@ void helper_cp1_putc(target_ulong x)
#ifdef CONFIG_USER_ONLY
void switch_mode(CPUUniCore32State *env, int mode)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
+
if (mode != ASR_MODE_USER) {
- cpu_abort(env, "Tried to switch out of user mode\n");
+ cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
}
}
void uc32_cpu_do_interrupt(CPUState *cs)
{
- UniCore32CPU *cpu = UNICORE32_CPU(cs);
- CPUUniCore32State *env = &cpu->env;
-
- cpu_abort(env, "NO interrupt in user mode\n");
+ cpu_abort(cs, "NO interrupt in user mode\n");
}
int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
int access_type, int mmu_idx)
{
- UniCore32CPU *cpu = UNICORE32_CPU(cs);
- CPUUniCore32State *env = &cpu->env;
-
- cpu_abort(env, "NO mmu fault in user mode\n");
+ cpu_abort(cs, "NO mmu fault in user mode\n");
return 1;
}
#endif
diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
index d0527e5..8c2acf2 100644
--- a/target-unicore32/softmmu.c
+++ b/target-unicore32/softmmu.c
@@ -33,6 +33,8 @@
/* Map CPU modes onto saved register banks. */
static inline int bank_number(CPUUniCore32State *env, int mode)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
+
switch (mode) {
case ASR_MODE_USER:
case ASR_MODE_SUSR:
@@ -46,7 +48,7 @@ static inline int bank_number(CPUUniCore32State *env, int mode)
case ASR_MODE_INTR:
return 4;
}
- cpu_abort(env, "Bad mode %x\n", mode);
+ cpu_abort(CPU(cpu), "Bad mode %x\n", mode);
return -1;
}
@@ -99,7 +101,7 @@ void uc32_cpu_do_interrupt(CPUState *cs)
addr = 0x18;
break;
default:
- cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
+ cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
return;
}
/* High vectors. */
@@ -121,6 +123,7 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
int access_type, int is_user, uint32_t *phys_ptr, int *prot,
target_ulong *page_size)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
int code;
uint32_t table;
uint32_t desc;
@@ -167,11 +170,11 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
*page_size = TARGET_PAGE_SIZE;
break;
default:
- cpu_abort(env, "wrong page type!");
+ cpu_abort(CPU(cpu), "wrong page type!");
}
break;
default:
- cpu_abort(env, "wrong page type!");
+ cpu_abort(CPU(cpu), "wrong page type!");
}
*phys_ptr = phys_addr;
@@ -267,6 +270,6 @@ hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
UniCore32CPU *cpu = UNICORE32_CPU(cs);
- cpu_abort(&cpu->env, "%s not supported yet\n", __func__);
+ cpu_abort(CPU(cpu), "%s not supported yet\n", __func__);
return addr;
}
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index b4bee99..532d825 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -179,7 +179,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
#define UCOP_SET_L UCOP_SET(24)
#define UCOP_SET_S UCOP_SET(24)
-#define ILLEGAL cpu_abort(env, \
+#define ILLEGAL cpu_abort(CPU(cpu), \
"Illegal UniCore32 instruction %x at line %d!", \
insn, __LINE__)
@@ -187,6 +187,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s,
uint32_t insn)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
TCGv tmp, tmp2, tmp3;
if ((insn & 0xfe000000) == 0xe0000000) {
tmp2 = new_tmp();
@@ -212,6 +213,7 @@ static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s,
static void disas_ocd_insn(CPUUniCore32State *env, DisasContext *s,
uint32_t insn)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
TCGv tmp;
if ((insn & 0xff003fff) == 0xe1000400) {
@@ -692,6 +694,7 @@ static inline long ucf64_reg_offset(int reg)
/* UniCore-F64 single load/store I_offset */
static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
int offset;
TCGv tmp;
TCGv addr;
@@ -738,6 +741,7 @@ static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t in
/* UniCore-F64 load/store multiple words */
static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
unsigned int i;
int j, n, freg;
TCGv tmp;
@@ -823,6 +827,7 @@ static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t in
/* UniCore-F64 mrc/mcr */
static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
TCGv tmp;
if ((insn & 0xfe0003ff) == 0xe2000000) {
@@ -887,6 +892,8 @@ static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t ins
/* UniCore-F64 convert instructions */
static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
+
if (UCOP_UCF64_FMT == 3) {
ILLEGAL;
}
@@ -953,6 +960,8 @@ static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn
/* UniCore-F64 compare instructions */
static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
+
if (UCOP_SET(25)) {
ILLEGAL;
}
@@ -1031,6 +1040,8 @@ static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn
/* UniCore-F64 data processing */
static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
+
if (UCOP_UCF64_FMT == 3) {
ILLEGAL;
}
@@ -1064,6 +1075,8 @@ static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t ins
/* Disassemble an F64 instruction */
static void disas_ucf64_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
+
if (!UCOP_SET(29)) {
if (UCOP_SET(26)) {
do_ucf64_ldst_m(env, s, insn);
@@ -1170,6 +1183,8 @@ static void gen_exception_return(DisasContext *s, TCGv pc)
static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s,
uint32_t insn)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
+
switch (UCOP_CPNUM) {
#ifndef CONFIG_USER_ONLY
case 0:
@@ -1184,13 +1199,14 @@ static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s,
break;
default:
/* Unknown coprocessor. */
- cpu_abort(env, "Unknown coprocessor!");
+ cpu_abort(CPU(cpu), "Unknown coprocessor!");
}
}
/* data processing instructions */
static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
TCGv tmp;
TCGv tmp2;
int logic_cc;
@@ -1424,6 +1440,7 @@ static void do_mult(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
/* miscellaneous instructions */
static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
unsigned int val;
TCGv tmp;
@@ -1549,6 +1566,7 @@ static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
/* SWP instruction */
static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
TCGv addr;
TCGv tmp;
TCGv tmp2;
@@ -1576,6 +1594,7 @@ static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
/* load/store hw/sb */
static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
TCGv addr;
TCGv tmp;
@@ -1628,6 +1647,7 @@ static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
/* load/store multiple words */
static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
unsigned int val, i, mmu_idx;
int j, n, reg, user, loaded_base;
TCGv tmp;
@@ -1769,6 +1789,7 @@ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
/* branch (and link) */
static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
unsigned int val;
int32_t offset;
TCGv tmp;
@@ -1798,6 +1819,7 @@ static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
unsigned int insn;
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
@@ -1981,7 +2003,7 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
if (dc->condjmp) {
/* FIXME: This can theoretically happen with self-modifying
code. */
- cpu_abort(env, "IO on conditional branch instruction");
+ cpu_abort(cs, "IO on conditional branch instruction");
}
gen_io_end();
}
diff --git a/target-unicore32/ucf64_helper.c b/target-unicore32/ucf64_helper.c
index a516edd..34fa2a5 100644
--- a/target-unicore32/ucf64_helper.c
+++ b/target-unicore32/ucf64_helper.c
@@ -76,6 +76,7 @@ static inline int ucf64_exceptbits_to_host(int target_bits)
void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
int i;
uint32_t changed;
@@ -99,7 +100,7 @@ void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
i = float_round_down;
break;
default: /* 100 and 101 not implement */
- cpu_abort(env, "Unsupported UniCore-F64 round mode");
+ cpu_abort(CPU(cpu), "Unsupported UniCore-F64 round mode");
}
set_float_rounding_mode(i, &env->ucf64.fp_status);
}
diff --git a/translate-all.c b/translate-all.c
index 37b573b..356f2ca 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -682,7 +682,7 @@ static void page_flush_tb(void)
/* XXX: tb_flush is currently not thread safe */
void tb_flush(CPUArchState *env1)
{
- CPUState *cpu;
+ CPUState *cpu = ENV_GET_CPU(env1);
#if defined(DEBUG_FLUSH)
printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
@@ -693,7 +693,7 @@ void tb_flush(CPUArchState *env1)
#endif
if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer)
> tcg_ctx.code_gen_buffer_size) {
- cpu_abort(env1, "Internal error: code buffer overflow\n");
+ cpu_abort(cpu, "Internal error: code buffer overflow\n");
}
tcg_ctx.tb_ctx.nb_tbs = 0;
@@ -1379,12 +1379,11 @@ void tb_invalidate_phys_addr(hwaddr addr)
void tb_check_watchpoint(CPUState *cpu)
{
- CPUArchState *env = cpu->env_ptr;
TranslationBlock *tb;
tb = tb_find_pc(cpu->mem_io_pc);
if (!tb) {
- cpu_abort(env, "check_watchpoint: could not find TB for pc=%p",
+ cpu_abort(cpu, "check_watchpoint: could not find TB for pc=%p",
(void *)cpu->mem_io_pc);
}
cpu_restore_state_from_tb(cpu, tb, cpu->mem_io_pc);
@@ -1395,7 +1394,6 @@ void tb_check_watchpoint(CPUState *cpu)
/* mask must never be zero, except for A20 change call */
static void tcg_handle_interrupt(CPUState *cpu, int mask)
{
- CPUArchState *env = cpu->env_ptr;
int old_mask;
old_mask = cpu->interrupt_request;
@@ -1414,7 +1412,7 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask)
cpu->icount_decr.u16.high = 0xffff;
if (!cpu_can_do_io(cpu)
&& (mask & ~old_mask) != 0) {
- cpu_abort(env, "Raised interrupt while not in I/O function");
+ cpu_abort(cpu, "Raised interrupt while not in I/O function");
}
} else {
cpu->tcg_exit_req = 1;
@@ -1427,7 +1425,9 @@ CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt;
must be at the end of the TB */
void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
{
+#if defined(TARGET_MIPS) || defined(TARGET_SH4)
CPUArchState *env = cpu->env_ptr;
+#endif
TranslationBlock *tb;
uint32_t n, cflags;
target_ulong pc, cs_base;
@@ -1435,7 +1435,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
tb = tb_find_pc(retaddr);
if (!tb) {
- cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p",
+ cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=%p",
(void *)retaddr);
}
n = cpu->icount_decr.u16.low + tb->icount;
@@ -1465,7 +1465,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
#endif
/* This should never happen. */
if (n > CF_COUNT_MASK) {
- cpu_abort(env, "TB too big during recompile");
+ cpu_abort(cpu, "TB too big during recompile");
}
cflags = n | CF_LAST_IO;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 34/41] exec: Change cpu_abort() argument to CPUState
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 34/41] exec: Change cpu_abort() " Andreas Färber
@ 2013-09-04 12:49 ` Jia Liu
0 siblings, 0 replies; 68+ messages in thread
From: Jia Liu @ 2013-09-04 12:49 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Riku Voipio, qemu-devel@nongnu.org, Alexander Graf,
Blue Swirl, Michael Walle, open list:PowerPC, Paul Brook,
Edgar E. Iglesias, Guan Xuetao, Aurelien Jarno, Richard Henderson
On Wed, Sep 4, 2013 at 5:05 PM, Andreas Färber <afaerber@suse.de> wrote:
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
> cputlb.c | 2 +-
> exec.c | 3 +-
> include/exec/cpu-all.h | 3 --
> include/qom/cpu.h | 3 ++
> linux-user/m68k-sim.c | 3 +-
> linux-user/main.c | 80 ++++++++++++++++++++---------------------
> target-alpha/helper.c | 2 +-
> target-arm/helper.c | 35 ++++++++++++------
> target-arm/translate.c | 2 +-
> target-cris/helper.c | 4 +--
> target-cris/translate.c | 4 +--
> target-cris/translate_v10.c | 12 +++----
> target-i386/seg_helper.c | 8 +++--
> target-lm32/helper.c | 2 +-
> target-lm32/translate.c | 38 ++++++++++----------
> target-m68k/helper.c | 7 ++--
> target-m68k/m68k-semi.c | 2 +-
> target-m68k/translate.c | 4 ++-
> target-microblaze/helper.c | 4 +--
> target-microblaze/translate.c | 51 +++++++++++++++-----------
> target-mips/op_helper.c | 11 ++++--
> target-mips/translate_init.c | 4 ++-
> target-openrisc/interrupt.c | 2 +-
> target-ppc/cpu.h | 2 +-
> target-ppc/excp_helper.c | 48 ++++++++++++-------------
> target-ppc/mmu_helper.c | 54 ++++++++++++++++------------
> target-ppc/translate_init.c | 5 +--
> target-s390x/cc_helper.c | 3 +-
> target-s390x/fpu_helper.c | 4 ++-
> target-s390x/helper.c | 23 +++++++-----
> target-s390x/mem_helper.c | 11 +++---
> target-sh4/helper.c | 21 +++++++----
> target-sh4/op_helper.c | 4 ++-
> target-sparc/int32_helper.c | 2 +-
> target-sparc/int64_helper.c | 2 +-
> target-unicore32/helper.c | 14 +++-----
> target-unicore32/softmmu.c | 13 ++++---
> target-unicore32/translate.c | 28 +++++++++++++--
> target-unicore32/ucf64_helper.c | 3 +-
> translate-all.c | 16 ++++-----
> 40 files changed, 317 insertions(+), 222 deletions(-)
>
> diff --git a/cputlb.c b/cputlb.c
> index f8b9566..20a1efe 100644
> --- a/cputlb.c
> +++ b/cputlb.c
> @@ -335,7 +335,7 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
> if (cc->do_unassigned_access) {
> cc->do_unassigned_access(cpu, addr, false, true, 0, 4);
> } else {
> - cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x"
> + cpu_abort(cpu, "Trying to execute code outside RAM or ROM at 0x"
> TARGET_FMT_lx "\n", addr);
> }
> }
> diff --git a/exec.c b/exec.c
> index ffbf4c3..16e3c4d 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -599,9 +599,8 @@ void cpu_single_step(CPUState *cpu, int enabled)
> #endif
> }
>
> -void cpu_abort(CPUArchState *env, const char *fmt, ...)
> +void cpu_abort(CPUState *cpu, const char *fmt, ...)
> {
> - CPUState *cpu = ENV_GET_CPU(env);
> va_list ap;
> va_list ap2;
>
> diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
> index a26d653..0490454 100644
> --- a/include/exec/cpu-all.h
> +++ b/include/exec/cpu-all.h
> @@ -359,9 +359,6 @@ int page_check_range(target_ulong start, target_ulong len, int flags);
>
> CPUArchState *cpu_copy(CPUArchState *env);
>
> -void QEMU_NORETURN cpu_abort(CPUArchState *env, const char *fmt, ...)
> - GCC_FMT_ATTR(2, 3);
> -
> /* Flags for use in ENV->INTERRUPT_PENDING.
>
> The numbers assigned here are non-sequential in order to preserve
> diff --git a/include/qom/cpu.h b/include/qom/cpu.h
> index 85ba419..0427a71 100644
> --- a/include/qom/cpu.h
> +++ b/include/qom/cpu.h
> @@ -622,6 +622,9 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
> void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
> void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
>
> +void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
> + GCC_FMT_ATTR(2, 3);
> +
> #ifdef CONFIG_SOFTMMU
> extern const struct VMStateDescription vmstate_cpu_common;
> #else
> diff --git a/linux-user/m68k-sim.c b/linux-user/m68k-sim.c
> index d5926ee..1994e40 100644
> --- a/linux-user/m68k-sim.c
> +++ b/linux-user/m68k-sim.c
> @@ -98,6 +98,7 @@ static int translate_openflags(int flags)
> #define ARG(x) tswap32(args[x])
> void do_m68k_simcall(CPUM68KState *env, int nr)
> {
> + M68kCPU *cpu = m68k_env_get_cpu(env);
> uint32_t *args;
>
> args = (uint32_t *)(unsigned long)(env->aregs[7] + 4);
> @@ -165,6 +166,6 @@ void do_m68k_simcall(CPUM68KState *env, int nr)
> check_err(env, lseek(ARG(0), (int32_t)ARG(1), ARG(2)));
> break;
> default:
> - cpu_abort(env, "Unsupported m68k sim syscall %d\n", nr);
> + cpu_abort(CPU(cpu), "Unsupported m68k sim syscall %d\n", nr);
> }
> }
> diff --git a/linux-user/main.c b/linux-user/main.c
> index cadefbe..b3b4ff6 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -1351,11 +1351,11 @@ void cpu_loop(CPUPPCState *env)
> /* Just go on */
> break;
> case POWERPC_EXCP_CRITICAL: /* Critical input */
> - cpu_abort(env, "Critical interrupt while in user mode. "
> + cpu_abort(cs, "Critical interrupt while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_MCHECK: /* Machine check exception */
> - cpu_abort(env, "Machine check exception while in user mode. "
> + cpu_abort(cs, "Machine check exception while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_DSI: /* Data storage exception */
> @@ -1419,7 +1419,7 @@ void cpu_loop(CPUPPCState *env)
> queue_signal(env, info.si_signo, &info);
> break;
> case POWERPC_EXCP_EXTERNAL: /* External input */
> - cpu_abort(env, "External interrupt while in user mode. "
> + cpu_abort(cs, "External interrupt while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_ALIGN: /* Alignment exception */
> @@ -1513,11 +1513,11 @@ void cpu_loop(CPUPPCState *env)
> }
> break;
> case POWERPC_EXCP_TRAP:
> - cpu_abort(env, "Tried to call a TRAP\n");
> + cpu_abort(cs, "Tried to call a TRAP\n");
> break;
> default:
> /* Should not happen ! */
> - cpu_abort(env, "Unknown program exception (%02x)\n",
> + cpu_abort(cs, "Unknown program exception (%02x)\n",
> env->error_code);
> break;
> }
> @@ -1533,7 +1533,7 @@ void cpu_loop(CPUPPCState *env)
> queue_signal(env, info.si_signo, &info);
> break;
> case POWERPC_EXCP_SYSCALL: /* System call exception */
> - cpu_abort(env, "Syscall exception while in user mode. "
> + cpu_abort(cs, "Syscall exception while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_APU: /* Auxiliary processor unavailable */
> @@ -1545,23 +1545,23 @@ void cpu_loop(CPUPPCState *env)
> queue_signal(env, info.si_signo, &info);
> break;
> case POWERPC_EXCP_DECR: /* Decrementer exception */
> - cpu_abort(env, "Decrementer interrupt while in user mode. "
> + cpu_abort(cs, "Decrementer interrupt while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_FIT: /* Fixed-interval timer interrupt */
> - cpu_abort(env, "Fix interval timer interrupt while in user mode. "
> + cpu_abort(cs, "Fix interval timer interrupt while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_WDT: /* Watchdog timer interrupt */
> - cpu_abort(env, "Watchdog timer interrupt while in user mode. "
> + cpu_abort(cs, "Watchdog timer interrupt while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_DTLB: /* Data TLB error */
> - cpu_abort(env, "Data TLB exception while in user mode. "
> + cpu_abort(cs, "Data TLB exception while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_ITLB: /* Instruction TLB error */
> - cpu_abort(env, "Instruction TLB exception while in user mode. "
> + cpu_abort(cs, "Instruction TLB exception while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavail. */
> @@ -1573,37 +1573,37 @@ void cpu_loop(CPUPPCState *env)
> queue_signal(env, info.si_signo, &info);
> break;
> case POWERPC_EXCP_EFPDI: /* Embedded floating-point data IRQ */
> - cpu_abort(env, "Embedded floating-point data IRQ not handled\n");
> + cpu_abort(cs, "Embedded floating-point data IRQ not handled\n");
> break;
> case POWERPC_EXCP_EFPRI: /* Embedded floating-point round IRQ */
> - cpu_abort(env, "Embedded floating-point round IRQ not handled\n");
> + cpu_abort(cs, "Embedded floating-point round IRQ not handled\n");
> break;
> case POWERPC_EXCP_EPERFM: /* Embedded performance monitor IRQ */
> - cpu_abort(env, "Performance monitor exception not handled\n");
> + cpu_abort(cs, "Performance monitor exception not handled\n");
> break;
> case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
> - cpu_abort(env, "Doorbell interrupt while in user mode. "
> + cpu_abort(cs, "Doorbell interrupt while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_DOORCI: /* Embedded doorbell critical interrupt */
> - cpu_abort(env, "Doorbell critical interrupt while in user mode. "
> + cpu_abort(cs, "Doorbell critical interrupt while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_RESET: /* System reset exception */
> - cpu_abort(env, "Reset interrupt while in user mode. "
> + cpu_abort(cs, "Reset interrupt while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_DSEG: /* Data segment exception */
> - cpu_abort(env, "Data segment exception while in user mode. "
> + cpu_abort(cs, "Data segment exception while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_ISEG: /* Instruction segment exception */
> - cpu_abort(env, "Instruction segment exception "
> + cpu_abort(cs, "Instruction segment exception "
> "while in user mode. Aborting\n");
> break;
> /* PowerPC 64 with hypervisor mode support */
> case POWERPC_EXCP_HDECR: /* Hypervisor decrementer exception */
> - cpu_abort(env, "Hypervisor decrementer interrupt "
> + cpu_abort(cs, "Hypervisor decrementer interrupt "
> "while in user mode. Aborting\n");
> break;
> case POWERPC_EXCP_TRACE: /* Trace exception */
> @@ -1613,19 +1613,19 @@ void cpu_loop(CPUPPCState *env)
> break;
> /* PowerPC 64 with hypervisor mode support */
> case POWERPC_EXCP_HDSI: /* Hypervisor data storage exception */
> - cpu_abort(env, "Hypervisor data storage exception "
> + cpu_abort(cs, "Hypervisor data storage exception "
> "while in user mode. Aborting\n");
> break;
> case POWERPC_EXCP_HISI: /* Hypervisor instruction storage excp */
> - cpu_abort(env, "Hypervisor instruction storage exception "
> + cpu_abort(cs, "Hypervisor instruction storage exception "
> "while in user mode. Aborting\n");
> break;
> case POWERPC_EXCP_HDSEG: /* Hypervisor data segment exception */
> - cpu_abort(env, "Hypervisor data segment exception "
> + cpu_abort(cs, "Hypervisor data segment exception "
> "while in user mode. Aborting\n");
> break;
> case POWERPC_EXCP_HISEG: /* Hypervisor instruction segment excp */
> - cpu_abort(env, "Hypervisor instruction segment exception "
> + cpu_abort(cs, "Hypervisor instruction segment exception "
> "while in user mode. Aborting\n");
> break;
> case POWERPC_EXCP_VPU: /* Vector unavailable exception */
> @@ -1637,58 +1637,58 @@ void cpu_loop(CPUPPCState *env)
> queue_signal(env, info.si_signo, &info);
> break;
> case POWERPC_EXCP_PIT: /* Programmable interval timer IRQ */
> - cpu_abort(env, "Programmable interval timer interrupt "
> + cpu_abort(cs, "Programmable interval timer interrupt "
> "while in user mode. Aborting\n");
> break;
> case POWERPC_EXCP_IO: /* IO error exception */
> - cpu_abort(env, "IO error exception while in user mode. "
> + cpu_abort(cs, "IO error exception while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_RUNM: /* Run mode exception */
> - cpu_abort(env, "Run mode exception while in user mode. "
> + cpu_abort(cs, "Run mode exception while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_EMUL: /* Emulation trap exception */
> - cpu_abort(env, "Emulation trap exception not handled\n");
> + cpu_abort(cs, "Emulation trap exception not handled\n");
> break;
> case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
> - cpu_abort(env, "Instruction fetch TLB exception "
> + cpu_abort(cs, "Instruction fetch TLB exception "
> "while in user-mode. Aborting");
> break;
> case POWERPC_EXCP_DLTLB: /* Data load TLB miss */
> - cpu_abort(env, "Data load TLB exception while in user-mode. "
> + cpu_abort(cs, "Data load TLB exception while in user-mode. "
> "Aborting");
> break;
> case POWERPC_EXCP_DSTLB: /* Data store TLB miss */
> - cpu_abort(env, "Data store TLB exception while in user-mode. "
> + cpu_abort(cs, "Data store TLB exception while in user-mode. "
> "Aborting");
> break;
> case POWERPC_EXCP_FPA: /* Floating-point assist exception */
> - cpu_abort(env, "Floating-point assist exception not handled\n");
> + cpu_abort(cs, "Floating-point assist exception not handled\n");
> break;
> case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
> - cpu_abort(env, "Instruction address breakpoint exception "
> + cpu_abort(cs, "Instruction address breakpoint exception "
> "not handled\n");
> break;
> case POWERPC_EXCP_SMI: /* System management interrupt */
> - cpu_abort(env, "System management interrupt while in user mode. "
> + cpu_abort(cs, "System management interrupt while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_THERM: /* Thermal interrupt */
> - cpu_abort(env, "Thermal interrupt interrupt while in user mode. "
> + cpu_abort(cs, "Thermal interrupt interrupt while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_PERFM: /* Embedded performance monitor IRQ */
> - cpu_abort(env, "Performance monitor exception not handled\n");
> + cpu_abort(cs, "Performance monitor exception not handled\n");
> break;
> case POWERPC_EXCP_VPUA: /* Vector assist exception */
> - cpu_abort(env, "Vector assist exception not handled\n");
> + cpu_abort(cs, "Vector assist exception not handled\n");
> break;
> case POWERPC_EXCP_SOFTP: /* Soft patch exception */
> - cpu_abort(env, "Soft patch exception not handled\n");
> + cpu_abort(cs, "Soft patch exception not handled\n");
> break;
> case POWERPC_EXCP_MAINT: /* Maintenance exception */
> - cpu_abort(env, "Maintenance exception while in user mode. "
> + cpu_abort(cs, "Maintenance exception while in user mode. "
> "Aborting\n");
> break;
> case POWERPC_EXCP_STOP: /* stop translation */
> @@ -1744,7 +1744,7 @@ void cpu_loop(CPUPPCState *env)
> /* just indicate that signals should be handled asap */
> break;
> default:
> - cpu_abort(env, "Unknown exception 0x%d. Aborting\n", trapnr);
> + cpu_abort(cs, "Unknown exception 0x%d. Aborting\n", trapnr);
> break;
> }
> process_pending_signals(env);
> diff --git a/target-alpha/helper.c b/target-alpha/helper.c
> index fd4a70c..cd2373c 100644
> --- a/target-alpha/helper.c
> +++ b/target-alpha/helper.c
> @@ -451,7 +451,7 @@ void alpha_cpu_do_interrupt(CPUState *cs)
> }
> break;
> default:
> - cpu_abort(env, "Unhandled CPU exception");
> + cpu_abort(cs, "Unhandled CPU exception");
> }
>
> /* Remember where the exception happened. Emulate real hardware in
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 06dd57c..34407a1 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2091,29 +2091,40 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> /* These should probably raise undefined insn exceptions. */
> void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
> {
> - cpu_abort(env, "v7m_mrs %d\n", reg);
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> + cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
> }
>
> uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
> {
> - cpu_abort(env, "v7m_mrs %d\n", reg);
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> + cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
> return 0;
> }
>
> void switch_mode(CPUARMState *env, int mode)
> {
> - if (mode != ARM_CPU_MODE_USR)
> - cpu_abort(env, "Tried to switch out of user mode\n");
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> + if (mode != ARM_CPU_MODE_USR) {
> + cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
> + }
> }
>
> void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
> {
> - cpu_abort(env, "banked r13 write\n");
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> + cpu_abort(CPU(cpu), "banked r13 write\n");
> }
>
> uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
> {
> - cpu_abort(env, "banked r13 read\n");
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> + cpu_abort(CPU(cpu), "banked r13 read\n");
> return 0;
> }
>
> @@ -2308,7 +2319,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
> do_v7m_exception_exit(env);
> return;
> default:
> - cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
> + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
> return; /* Never happens. Keep compiler happy. */
> }
>
> @@ -2433,7 +2444,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
> offset = 4;
> break;
> default:
> - cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
> + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
> return; /* Never happens. Keep compiler happy. */
> }
> /* High vectors. */
> @@ -3095,6 +3106,8 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
>
> uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
> {
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> switch (reg) {
> case 0: /* APSR */
> return xpsr_read(env) & 0xf8000000;
> @@ -3125,13 +3138,15 @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
> return env->v7m.control;
> default:
> /* ??? For debugging only. */
> - cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
> + cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
> return 0;
> }
> }
>
> void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
> {
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> switch (reg) {
> case 0: /* APSR */
> xpsr_write(env, val, 0xf8000000);
> @@ -3192,7 +3207,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
> break;
> default:
> /* ??? For debugging only. */
> - cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
> + cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
> return;
> }
> }
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 0eaec9f..bfbf1c4 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -10104,7 +10104,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu,
> if (dc->condjmp) {
> /* FIXME: This can theoretically happen with self-modifying
> code. */
> - cpu_abort(env, "IO on conditional branch instruction");
> + cpu_abort(cs, "IO on conditional branch instruction");
> }
> gen_io_end();
> }
> diff --git a/target-cris/helper.c b/target-cris/helper.c
> index 08b3864..799cd16 100644
> --- a/target-cris/helper.c
> +++ b/target-cris/helper.c
> @@ -89,7 +89,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> rw, mmu_idx, 0);
> if (miss) {
> if (cs->exception_index == EXCP_BUSFAULT) {
> - cpu_abort(env,
> + cpu_abort(cs,
> "CRIS: Illegal recursive bus fault."
> "addr=%" VADDR_PRIx " rw=%d\n",
> address, rw);
> @@ -145,7 +145,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs)
> break;
>
> case EXCP_BUSFAULT:
> - cpu_abort(env, "Unhandled busfault");
> + cpu_abort(cs, "Unhandled busfault");
> break;
>
> default:
> diff --git a/target-cris/translate.c b/target-cris/translate.c
> index 90a4394..bf15ed6 100644
> --- a/target-cris/translate.c
> +++ b/target-cris/translate.c
> @@ -129,7 +129,7 @@ static void gen_BUG(DisasContext *dc, const char *file, int line)
> {
> printf("BUG: pc=%x %s %d\n", dc->pc, file, line);
> qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
> - cpu_abort(dc->env, "%s:%d\n", file, line);
> + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "%s:%d\n", file, line);
> }
>
> static const char *regnames[] =
> @@ -272,7 +272,7 @@ static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,
> break;
> }
> default:
> - cpu_abort(dc->env, "Invalid fetch size %d\n", size);
> + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Invalid fetch size %d\n", size);
> break;
> }
> return r;
> diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
> index 0ade05b..734225f 100644
> --- a/target-cris/translate_v10.c
> +++ b/target-cris/translate_v10.c
> @@ -340,7 +340,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
> default:
> LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
> dc->pc, dc->mode, dc->opcode, dc->src, dc->dst);
> - cpu_abort(dc->env, "Unhandled quickimm\n");
> + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled quickimm\n");
> break;
> }
> return 2;
> @@ -651,7 +651,7 @@ static unsigned int dec10_reg(DisasContext *dc)
> case 2: tmp = 1; break;
> case 1: tmp = 0; break;
> default:
> - cpu_abort(dc->env, "Unhandled BIAP");
> + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled BIAP");
> break;
> }
>
> @@ -669,7 +669,7 @@ static unsigned int dec10_reg(DisasContext *dc)
> default:
> LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
> dc->opcode, dc->src, dc->dst);
> - cpu_abort(dc->env, "Unhandled opcode");
> + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode");
> break;
> }
> } else {
> @@ -745,7 +745,7 @@ static unsigned int dec10_reg(DisasContext *dc)
> default:
> LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
> dc->opcode, dc->src, dc->dst);
> - cpu_abort(dc->env, "Unhandled opcode");
> + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode");
> break;
> }
> }
> @@ -1105,7 +1105,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
> default:
> LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n",
> dc->pc, size, dc->opcode, dc->src, dc->dst);
> - cpu_abort(dc->env, "Unhandled opcode");
> + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode");
> break;
> }
> return insn_len;
> @@ -1198,7 +1198,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
> break;
> default:
> LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode);
> - cpu_abort(dc->env, "Unhandled opcode");
> + cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode");
> break;
> }
>
> diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
> index d030793..a3ec4dc 100644
> --- a/target-i386/seg_helper.c
> +++ b/target-i386/seg_helper.c
> @@ -95,6 +95,7 @@ static inline void load_seg_vm(CPUX86State *env, int seg, int selector)
> static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr,
> uint32_t *esp_ptr, int dpl)
> {
> + X86CPU *cpu = x86_env_get_cpu(env);
> int type, index, shift;
>
> #if 0
> @@ -112,11 +113,11 @@ static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr,
> #endif
>
> if (!(env->tr.flags & DESC_P_MASK)) {
> - cpu_abort(env, "invalid tss");
> + cpu_abort(CPU(cpu), "invalid tss");
> }
> type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
> if ((type & 7) != 1) {
> - cpu_abort(env, "invalid tss type");
> + cpu_abort(CPU(cpu), "invalid tss type");
> }
> shift = type >> 3;
> index = (dpl * 4 + 2) << shift;
> @@ -782,6 +783,7 @@ static void do_interrupt_protected(CPUX86State *env, int intno, int is_int,
>
> static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level)
> {
> + X86CPU *cpu = x86_env_get_cpu(env);
> int index;
>
> #if 0
> @@ -790,7 +792,7 @@ static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level)
> #endif
>
> if (!(env->tr.flags & DESC_P_MASK)) {
> - cpu_abort(env, "invalid tss");
> + cpu_abort(CPU(cpu), "invalid tss");
> }
> index = 8 * level + 4;
> if ((index + 7) > env->tr.limit) {
> diff --git a/target-lm32/helper.c b/target-lm32/helper.c
> index daf0f2f..8f2b9fd 100644
> --- a/target-lm32/helper.c
> +++ b/target-lm32/helper.c
> @@ -86,7 +86,7 @@ void lm32_cpu_do_interrupt(CPUState *cs)
> log_cpu_state_mask(CPU_LOG_INT, cs, 0);
> break;
> default:
> - cpu_abort(env, "unhandled exception type=%d\n",
> + cpu_abort(cs, "unhandled exception type=%d\n",
> cs->exception_index);
> break;
> }
> diff --git a/target-lm32/translate.c b/target-lm32/translate.c
> index 2e4951c..532345b 100644
> --- a/target-lm32/translate.c
> +++ b/target-lm32/translate.c
> @@ -422,7 +422,7 @@ static void dec_divu(DisasContext *dc)
> LOG_DIS("divu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
>
> if (!(dc->env->features & LM32_FEATURE_DIVIDE)) {
> - cpu_abort(dc->env, "hardware divider is not available\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware divider is not available\n");
> }
>
> l1 = gen_new_label();
> @@ -500,7 +500,7 @@ static void dec_modu(DisasContext *dc)
> LOG_DIS("modu r%d, r%d, %d\n", dc->r2, dc->r0, dc->r1);
>
> if (!(dc->env->features & LM32_FEATURE_DIVIDE)) {
> - cpu_abort(dc->env, "hardware divider is not available\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware divider is not available\n");
> }
>
> l1 = gen_new_label();
> @@ -521,7 +521,7 @@ static void dec_mul(DisasContext *dc)
> }
>
> if (!(dc->env->features & LM32_FEATURE_MULTIPLY)) {
> - cpu_abort(dc->env, "hardware multiplier is not available\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware multiplier is not available\n");
> }
>
> if (dc->format == OP_FMT_RI) {
> @@ -590,7 +590,7 @@ static void dec_scall(DisasContext *dc)
> } else if (dc->imm5 == 2) {
> LOG_DIS("break\n");
> } else {
> - cpu_abort(dc->env, "invalid opcode\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "invalid opcode\n");
> }
>
> if (dc->imm5 == 7) {
> @@ -647,10 +647,10 @@ static void dec_rcsr(DisasContext *dc)
> case CSR_WP1:
> case CSR_WP2:
> case CSR_WP3:
> - cpu_abort(dc->env, "invalid read access csr=%x\n", dc->csr);
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "invalid read access csr=%x\n", dc->csr);
> break;
> default:
> - cpu_abort(dc->env, "read_csr: unknown csr=%x\n", dc->csr);
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "read_csr: unknown csr=%x\n", dc->csr);
> break;
> }
> }
> @@ -672,7 +672,7 @@ static void dec_sextb(DisasContext *dc)
> LOG_DIS("sextb r%d, r%d\n", dc->r2, dc->r0);
>
> if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) {
> - cpu_abort(dc->env, "hardware sign extender is not available\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware sign extender is not available\n");
> }
>
> tcg_gen_ext8s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
> @@ -683,7 +683,7 @@ static void dec_sexth(DisasContext *dc)
> LOG_DIS("sexth r%d, r%d\n", dc->r2, dc->r0);
>
> if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) {
> - cpu_abort(dc->env, "hardware sign extender is not available\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware sign extender is not available\n");
> }
>
> tcg_gen_ext16s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
> @@ -710,7 +710,7 @@ static void dec_sl(DisasContext *dc)
> }
>
> if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
> - cpu_abort(dc->env, "hardware shifter is not available\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware shifter is not available\n");
> }
>
> if (dc->format == OP_FMT_RI) {
> @@ -736,7 +736,7 @@ static void dec_sr(DisasContext *dc)
> /* TODO: check r1 == 1 during runtime */
> } else {
> if (dc->imm5 != 1) {
> - cpu_abort(dc->env, "hardware shifter is not available\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware shifter is not available\n");
> }
> }
> }
> @@ -764,7 +764,7 @@ static void dec_sru(DisasContext *dc)
> /* TODO: check r1 == 1 during runtime */
> } else {
> if (dc->imm5 != 1) {
> - cpu_abort(dc->env, "hardware shifter is not available\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware shifter is not available\n");
> }
> }
> }
> @@ -802,7 +802,7 @@ static void dec_user(DisasContext *dc)
> {
> LOG_DIS("user");
>
> - cpu_abort(dc->env, "user insn undefined\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "user insn undefined\n");
> }
>
> static void dec_wcsr(DisasContext *dc)
> @@ -868,7 +868,7 @@ static void dec_wcsr(DisasContext *dc)
> case CSR_BP3:
> no = dc->csr - CSR_BP0;
> if (dc->env->num_bps <= no) {
> - cpu_abort(dc->env, "breakpoint #%i is not available\n", no);
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "breakpoint #%i is not available\n", no);
> }
> tcg_gen_mov_tl(cpu_bp[no], cpu_R[dc->r1]);
> break;
> @@ -878,16 +878,16 @@ static void dec_wcsr(DisasContext *dc)
> case CSR_WP3:
> no = dc->csr - CSR_WP0;
> if (dc->env->num_wps <= no) {
> - cpu_abort(dc->env, "watchpoint #%i is not available\n", no);
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "watchpoint #%i is not available\n", no);
> }
> tcg_gen_mov_tl(cpu_wp[no], cpu_R[dc->r1]);
> break;
> case CSR_CC:
> case CSR_CFG:
> - cpu_abort(dc->env, "invalid write access csr=%x\n", dc->csr);
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "invalid write access csr=%x\n", dc->csr);
> break;
> default:
> - cpu_abort(dc->env, "write_csr unknown csr=%x\n", dc->csr);
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "write_csr unknown csr=%x\n", dc->csr);
> break;
> }
> }
> @@ -933,7 +933,7 @@ static void dec_xor(DisasContext *dc)
>
> static void dec_ill(DisasContext *dc)
> {
> - cpu_abort(dc->env, "unknown opcode 0x%02x\n", dc->opcode);
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "unknown opcode 0x%02x\n", dc->opcode);
> }
>
> typedef void (*DecoderInfo)(DisasContext *dc);
> @@ -967,7 +967,7 @@ static inline void decode(DisasContext *dc, uint32_t ir)
> LOG_DIS("nr_nops=%d\t", dc->nr_nops);
> dc->nr_nops++;
> if (dc->nr_nops > 4) {
> - cpu_abort(dc->env, "fetching nop sequence\n");
> + cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "fetching nop sequence\n");
> }
> }
>
> @@ -1038,7 +1038,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
> dc->nr_nops = 0;
>
> if (pc_start & 3) {
> - cpu_abort(env, "LM32: unaligned PC=%x\n", pc_start);
> + cpu_abort(cs, "LM32: unaligned PC=%x\n", pc_start);
> }
>
> next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
> diff --git a/target-m68k/helper.c b/target-m68k/helper.c
> index 219e8b3..5767390 100644
> --- a/target-m68k/helper.c
> +++ b/target-m68k/helper.c
> @@ -132,6 +132,7 @@ void m68k_cpu_init_gdb(M68kCPU *cpu)
>
> void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op)
> {
> + M68kCPU *cpu = m68k_env_get_cpu(env);
> int flags;
> uint32_t src;
> uint32_t dest;
> @@ -204,7 +205,7 @@ void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op)
> flags |= CCF_C;
> break;
> default:
> - cpu_abort(env, "Bad CC_OP %d", cc_op);
> + cpu_abort(CPU(cpu), "Bad CC_OP %d", cc_op);
> }
> env->cc_op = CC_OP_FLAGS;
> env->cc_dest = flags;
> @@ -212,6 +213,8 @@ void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op)
>
> void HELPER(movec)(CPUM68KState *env, uint32_t reg, uint32_t val)
> {
> + M68kCPU *cpu = m68k_env_get_cpu(env);
> +
> switch (reg) {
> case 0x02: /* CACR */
> env->cacr = val;
> @@ -225,7 +228,7 @@ void HELPER(movec)(CPUM68KState *env, uint32_t reg, uint32_t val)
> break;
> /* TODO: Implement control registers. */
> default:
> - cpu_abort(env, "Unimplemented control register write 0x%x = 0x%x\n",
> + cpu_abort(CPU(cpu), "Unimplemented control register write 0x%x = 0x%x\n",
> reg, val);
> }
> }
> diff --git a/target-m68k/m68k-semi.c b/target-m68k/m68k-semi.c
> index 2dea3ca..9dffe8d 100644
> --- a/target-m68k/m68k-semi.c
> +++ b/target-m68k/m68k-semi.c
> @@ -461,7 +461,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr)
> #endif
> return;
> default:
> - cpu_abort(env, "Unsupported semihosting syscall %d\n", nr);
> + cpu_abort(CPU(m68k_env_get_cpu(env)), "Unsupported semihosting syscall %d\n", nr);
> result = 0;
> }
> failed:
> diff --git a/target-m68k/translate.c b/target-m68k/translate.c
> index c005e10..bee0d25 100644
> --- a/target-m68k/translate.c
> +++ b/target-m68k/translate.c
> @@ -894,8 +894,10 @@ DISAS_INSN(undef_fpu)
>
> DISAS_INSN(undef)
> {
> + M68kCPU *cpu = m68k_env_get_cpu(env);
> +
> gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);
> - cpu_abort(env, "Illegal instruction: %04x @ %08x", insn, s->pc - 2);
> + cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2);
> }
>
> DISAS_INSN(mulw)
> diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c
> index 50aa55a..59c9ad5 100644
> --- a/target-microblaze/helper.c
> +++ b/target-microblaze/helper.c
> @@ -98,7 +98,7 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> }
>
> if (cs->exception_index == EXCP_MMU) {
> - cpu_abort(env, "recursive faults\n");
> + cpu_abort(cs, "recursive faults\n");
> }
>
> /* TLB miss. */
> @@ -259,7 +259,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
> env->sregs[SR_PC] = env->btarget;
> break;
> default:
> - cpu_abort(env, "unhandled exception type=%d\n",
> + cpu_abort(cs, "unhandled exception type=%d\n",
> cs->exception_index);
> break;
> }
> diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
> index 31eef0f..4471f5a 100644
> --- a/target-microblaze/translate.c
> +++ b/target-microblaze/translate.c
> @@ -364,7 +364,7 @@ static void dec_pattern(DisasContext *dc)
> }
> break;
> default:
> - cpu_abort(dc->env,
> + cpu_abort(CPU(mb_env_get_cpu(dc->env)),
> "unsupported pattern insn opcode=%x\n", dc->opcode);
> break;
> }
> @@ -438,9 +438,11 @@ static inline void msr_write(DisasContext *dc, TCGv v)
>
> static void dec_msr(DisasContext *dc)
> {
> + MicroBlazeCPU *cpu = mb_env_get_cpu(dc->env);
> + CPUState *cs = CPU(cpu);
> TCGv t0, t1;
> unsigned int sr, to, rn;
> - int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
> + int mem_index = cpu_mmu_index(cs);
>
> sr = dc->imm & ((1 << 14) - 1);
> to = dc->imm & (1 << 14);
> @@ -534,7 +536,7 @@ static void dec_msr(DisasContext *dc)
> tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, shr));
> break;
> default:
> - cpu_abort(dc->env, "unknown mts reg %x\n", sr);
> + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "unknown mts reg %x\n", sr);
> break;
> }
> } else {
> @@ -583,7 +585,7 @@ static void dec_msr(DisasContext *dc)
> cpu_env, offsetof(CPUMBState, pvr.regs[rn]));
> break;
> default:
> - cpu_abort(dc->env, "unknown mfs reg %x\n", sr);
> + cpu_abort(cs, "unknown mfs reg %x\n", sr);
> break;
> }
> }
> @@ -681,7 +683,7 @@ static void dec_mul(DisasContext *dc)
> t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
> break;
> default:
> - cpu_abort(dc->env, "unknown MUL insn %x\n", subcode);
> + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "unknown MUL insn %x\n", subcode);
> break;
> }
> done:
> @@ -749,9 +751,11 @@ static void dec_barrel(DisasContext *dc)
>
> static void dec_bit(DisasContext *dc)
> {
> + MicroBlazeCPU *cpu = mb_env_get_cpu(dc->env);
> + CPUState *cs = CPU(cpu);
> TCGv t0, t1;
> unsigned int op;
> - int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
> + int mem_index = cpu_mmu_index(cs);
>
> op = dc->ir & ((1 << 9) - 1);
> switch (op) {
> @@ -846,8 +850,8 @@ static void dec_bit(DisasContext *dc)
> tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16);
> break;
> default:
> - cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
> - dc->pc, op, dc->rd, dc->ra, dc->rb);
> + cpu_abort(cs, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
> + dc->pc, op, dc->rd, dc->ra, dc->rb);
> break;
> }
> }
> @@ -874,7 +878,9 @@ static void dec_imm(DisasContext *dc)
> static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
> unsigned int size)
> {
> - int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
> + MicroBlazeCPU *cpu = mb_env_get_cpu(dc->env);
> + CPUState *cs = CPU(cpu);
> + int mem_index = cpu_mmu_index(cs);
>
> if (size == 1) {
> tcg_gen_qemu_ld8u(dst, addr, mem_index);
> @@ -883,7 +889,7 @@ static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
> } else if (size == 4) {
> tcg_gen_qemu_ld32u(dst, addr, mem_index);
> } else
> - cpu_abort(dc->env, "Incorrect load size %d\n", size);
> + cpu_abort(cs, "Incorrect load size %d\n", size);
> }
>
> static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t)
> @@ -1026,7 +1032,7 @@ static void dec_load(DisasContext *dc)
> }
> break;
> default:
> - cpu_abort(dc->env, "Invalid reverse size\n");
> + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "Invalid reverse size\n");
> break;
> }
> }
> @@ -1093,7 +1099,9 @@ static void dec_load(DisasContext *dc)
> static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
> unsigned int size)
> {
> - int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
> + MicroBlazeCPU *cpu = mb_env_get_cpu(dc->env);
> + CPUState *cs = CPU(cpu);
> + int mem_index = cpu_mmu_index(cs);
>
> if (size == 1)
> tcg_gen_qemu_st8(val, addr, mem_index);
> @@ -1101,8 +1109,9 @@ static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
> tcg_gen_qemu_st16(val, addr, mem_index);
> } else if (size == 4) {
> tcg_gen_qemu_st32(val, addr, mem_index);
> - } else
> - cpu_abort(dc->env, "Incorrect store size %d\n", size);
> + } else {
> + cpu_abort(cs, "Incorrect store size %d\n", size);
> + }
> }
>
> static void dec_store(DisasContext *dc)
> @@ -1188,7 +1197,7 @@ static void dec_store(DisasContext *dc)
> }
> break;
> default:
> - cpu_abort(dc->env, "Invalid reverse size\n");
> + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "Invalid reverse size\n");
> break;
> }
>
> @@ -1257,7 +1266,7 @@ static inline void eval_cc(DisasContext *dc, unsigned int cc,
> tcg_gen_setcond_tl(TCG_COND_GT, d, a, b);
> break;
> default:
> - cpu_abort(dc->env, "Unknown condition code %x.\n", cc);
> + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "Unknown condition code %x.\n", cc);
> break;
> }
> }
> @@ -1701,8 +1710,9 @@ static inline void decode(DisasContext *dc, uint32_t ir)
>
> LOG_DIS("nr_nops=%d\t", dc->nr_nops);
> dc->nr_nops++;
> - if (dc->nr_nops > 4)
> - cpu_abort(dc->env, "fetching nop sequence\n");
> + if (dc->nr_nops > 4) {
> + cpu_abort(CPU(mb_env_get_cpu(dc->env)), "fetching nop sequence\n");
> + }
> }
> /* bit 2 seems to indicate insn type. */
> dc->type_b = ir & (1 << 29);
> @@ -1773,8 +1783,9 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
> dc->abort_at_next_insn = 0;
> dc->nr_nops = 0;
>
> - if (pc_start & 3)
> - cpu_abort(env, "Microblaze: unaligned PC=%x\n", pc_start);
> + if (pc_start & 3) {
> + cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start);
> + }
>
> if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
> #if !SIM_COMPAT
> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
> index dc0c1cc..14f727f 100644
> --- a/target-mips/op_helper.c
> +++ b/target-mips/op_helper.c
> @@ -1344,6 +1344,7 @@ void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
>
> void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
> {
> + MIPSCPU *cpu = mips_env_get_cpu(env);
> uint32_t val, old;
> uint32_t mask = env->CP0_Status_rw_bitmask;
>
> @@ -1365,7 +1366,9 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
> case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
> case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
> case MIPS_HFLAG_KM: qemu_log("\n"); break;
> - default: cpu_abort(env, "Invalid MMU mode!\n"); break;
> + default:
> + cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
> + break;
> }
> }
> }
> @@ -1973,6 +1976,8 @@ static void debug_pre_eret(CPUMIPSState *env)
>
> static void debug_post_eret(CPUMIPSState *env)
> {
> + MIPSCPU *cpu = mips_env_get_cpu(env);
> +
> if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
> qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
> env->active_tc.PC, env->CP0_EPC);
> @@ -1984,7 +1989,9 @@ static void debug_post_eret(CPUMIPSState *env)
> case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
> case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
> case MIPS_HFLAG_KM: qemu_log("\n"); break;
> - default: cpu_abort(env, "Invalid MMU mode!\n"); break;
> + default:
> + cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
> + break;
> }
> }
> }
> diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
> index c45b1b2..4d90ed5 100644
> --- a/target-mips/translate_init.c
> +++ b/target-mips/translate_init.c
> @@ -586,6 +586,8 @@ static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
>
> static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
> {
> + MIPSCPU *cpu = mips_env_get_cpu(env);
> +
> env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
>
> switch (def->mmu_type) {
> @@ -602,7 +604,7 @@ static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
> case MMU_TYPE_R6000:
> case MMU_TYPE_R8000:
> default:
> - cpu_abort(env, "MMU type not supported\n");
> + cpu_abort(CPU(cpu), "MMU type not supported\n");
> }
> }
> #endif /* CONFIG_USER_ONLY */
> diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
> index 64f2ca6..52bcc6e 100644
> --- a/target-openrisc/interrupt.c
> +++ b/target-openrisc/interrupt.c
> @@ -69,7 +69,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
> if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) {
> env->pc = (cs->exception_index << 8);
> } else {
> - cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
> + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
> }
> #endif
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 3b03ae6..ea121dd 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -2051,7 +2051,7 @@ static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
> }
> }
>
> - cpu_abort(env, "Unknown TLBe: %d\n", id);
> + cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
> return 0;
> }
>
> diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
> index 7ced42d..ef67b0e 100644
> --- a/target-ppc/excp_helper.c
> +++ b/target-ppc/excp_helper.c
> @@ -240,7 +240,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
> break;
> default:
> /* Should never occur */
> - cpu_abort(env, "Invalid program exception %d. Aborting\n",
> + cpu_abort(cs, "Invalid program exception %d. Aborting\n",
> env->error_code);
> break;
> }
> @@ -300,26 +300,26 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
> break;
> }
> /* XXX: TODO */
> - cpu_abort(env, "Debug exception is not implemented yet !\n");
> + cpu_abort(cs, "Debug exception is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_SPEU: /* SPE/embedded floating-point unavailable */
> env->spr[SPR_BOOKE_ESR] = ESR_SPV;
> goto store_current;
> case POWERPC_EXCP_EFPDI: /* Embedded floating-point data interrupt */
> /* XXX: TODO */
> - cpu_abort(env, "Embedded floating point data exception "
> + cpu_abort(cs, "Embedded floating point data exception "
> "is not implemented yet !\n");
> env->spr[SPR_BOOKE_ESR] = ESR_SPV;
> goto store_next;
> case POWERPC_EXCP_EFPRI: /* Embedded floating-point round interrupt */
> /* XXX: TODO */
> - cpu_abort(env, "Embedded floating point round exception "
> + cpu_abort(cs, "Embedded floating point round exception "
> "is not implemented yet !\n");
> env->spr[SPR_BOOKE_ESR] = ESR_SPV;
> goto store_next;
> case POWERPC_EXCP_EPERFM: /* Embedded performance monitor interrupt */
> /* XXX: TODO */
> - cpu_abort(env,
> + cpu_abort(cs,
> "Performance counter exception is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_DOORI: /* Embedded doorbell interrupt */
> @@ -396,15 +396,15 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
> goto store_next;
> case POWERPC_EXCP_IO: /* IO error exception */
> /* XXX: TODO */
> - cpu_abort(env, "601 IO error exception is not implemented yet !\n");
> + cpu_abort(cs, "601 IO error exception is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_RUNM: /* Run mode exception */
> /* XXX: TODO */
> - cpu_abort(env, "601 run mode exception is not implemented yet !\n");
> + cpu_abort(cs, "601 run mode exception is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_EMUL: /* Emulation trap exception */
> /* XXX: TODO */
> - cpu_abort(env, "602 emulation trap exception "
> + cpu_abort(cs, "602 emulation trap exception "
> "is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_IFTLB: /* Instruction fetch TLB error */
> @@ -422,7 +422,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
> case POWERPC_EXCP_74xx:
> goto tlb_miss_74xx;
> default:
> - cpu_abort(env, "Invalid instruction TLB miss exception\n");
> + cpu_abort(cs, "Invalid instruction TLB miss exception\n");
> break;
> }
> break;
> @@ -441,7 +441,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
> case POWERPC_EXCP_74xx:
> goto tlb_miss_74xx;
> default:
> - cpu_abort(env, "Invalid data load TLB miss exception\n");
> + cpu_abort(cs, "Invalid data load TLB miss exception\n");
> break;
> }
> break;
> @@ -527,30 +527,30 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
> msr |= env->error_code; /* key bit */
> break;
> default:
> - cpu_abort(env, "Invalid data store TLB miss exception\n");
> + cpu_abort(cs, "Invalid data store TLB miss exception\n");
> break;
> }
> goto store_next;
> case POWERPC_EXCP_FPA: /* Floating-point assist exception */
> /* XXX: TODO */
> - cpu_abort(env, "Floating point assist exception "
> + cpu_abort(cs, "Floating point assist exception "
> "is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_DABR: /* Data address breakpoint */
> /* XXX: TODO */
> - cpu_abort(env, "DABR exception is not implemented yet !\n");
> + cpu_abort(cs, "DABR exception is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_IABR: /* Instruction address breakpoint */
> /* XXX: TODO */
> - cpu_abort(env, "IABR exception is not implemented yet !\n");
> + cpu_abort(cs, "IABR exception is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_SMI: /* System management interrupt */
> /* XXX: TODO */
> - cpu_abort(env, "SMI exception is not implemented yet !\n");
> + cpu_abort(cs, "SMI exception is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_THERM: /* Thermal interrupt */
> /* XXX: TODO */
> - cpu_abort(env, "Thermal management exception "
> + cpu_abort(cs, "Thermal management exception "
> "is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
> @@ -558,36 +558,36 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
> new_msr |= (target_ulong)MSR_HVB;
> }
> /* XXX: TODO */
> - cpu_abort(env,
> + cpu_abort(cs,
> "Performance counter exception is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_VPUA: /* Vector assist exception */
> /* XXX: TODO */
> - cpu_abort(env, "VPU assist exception is not implemented yet !\n");
> + cpu_abort(cs, "VPU assist exception is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_SOFTP: /* Soft patch exception */
> /* XXX: TODO */
> - cpu_abort(env,
> + cpu_abort(cs,
> "970 soft-patch exception is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_MAINT: /* Maintenance exception */
> /* XXX: TODO */
> - cpu_abort(env,
> + cpu_abort(cs,
> "970 maintenance exception is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_MEXTBR: /* Maskable external breakpoint */
> /* XXX: TODO */
> - cpu_abort(env, "Maskable external exception "
> + cpu_abort(cs, "Maskable external exception "
> "is not implemented yet !\n");
> goto store_next;
> case POWERPC_EXCP_NMEXTBR: /* Non maskable external breakpoint */
> /* XXX: TODO */
> - cpu_abort(env, "Non maskable external exception "
> + cpu_abort(cs, "Non maskable external exception "
> "is not implemented yet !\n");
> goto store_next;
> default:
> excp_invalid:
> - cpu_abort(env, "Invalid PowerPC exception %d. Aborting\n", excp);
> + cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
> break;
> store_current:
> /* save current instruction location */
> @@ -629,7 +629,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
> /* Jump to handler */
> vector = env->excp_vectors[excp];
> if (vector == (target_ulong)-1ULL) {
> - cpu_abort(env, "Raised an exception without defined vector %d\n",
> + cpu_abort(cs, "Raised an exception without defined vector %d\n",
> excp);
> }
> vector |= env->excp_prefix;
> diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
> index ff70b38..f4dac00 100644
> --- a/target-ppc/mmu_helper.c
> +++ b/target-ppc/mmu_helper.c
> @@ -746,9 +746,11 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
>
> void store_40x_sler(CPUPPCState *env, uint32_t val)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +
> /* XXX: TO BE FIXED */
> if (val != 0x00000000) {
> - cpu_abort(env, "Little-endian regions are not supported by now\n");
> + cpu_abort(CPU(cpu), "Little-endian regions are not supported by now\n");
> }
> env->spr[SPR_405_SLER] = val;
> }
> @@ -1344,6 +1346,7 @@ static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx,
> static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
> target_ulong eaddr, int rw, int access_type)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> int ret = -1;
> bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0)
> || (access_type != ACCESS_CODE && msr_dr == 0);
> @@ -1388,17 +1391,17 @@ static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
> break;
> case POWERPC_MMU_MPC8xx:
> /* XXX: TODO */
> - cpu_abort(env, "MPC8xx MMU model is not implemented\n");
> + cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");
> break;
> case POWERPC_MMU_REAL:
> if (real_mode) {
> ret = check_physical(env, ctx, eaddr, rw);
> } else {
> - cpu_abort(env, "PowerPC in real mode do not do any translation\n");
> + cpu_abort(CPU(cpu), "PowerPC in real mode do not do any translation\n");
> }
> return -1;
> default:
> - cpu_abort(env, "Unknown or invalid MMU model\n");
> + cpu_abort(CPU(cpu), "Unknown or invalid MMU model\n");
> return -1;
> }
> #if 0
> @@ -1543,14 +1546,14 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> return -1;
> case POWERPC_MMU_MPC8xx:
> /* XXX: TODO */
> - cpu_abort(env, "MPC8xx MMU model is not implemented\n");
> + cpu_abort(cs, "MPC8xx MMU model is not implemented\n");
> break;
> case POWERPC_MMU_REAL:
> - cpu_abort(env, "PowerPC in real mode should never raise "
> + cpu_abort(cs, "PowerPC in real mode should never raise "
> "any MMU exceptions\n");
> return -1;
> default:
> - cpu_abort(env, "Unknown or invalid MMU model\n");
> + cpu_abort(cs, "Unknown or invalid MMU model\n");
> return -1;
> }
> break;
> @@ -1623,7 +1626,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> break;
> case POWERPC_MMU_MPC8xx:
> /* XXX: TODO */
> - cpu_abort(env, "MPC8xx MMU model is not implemented\n");
> + cpu_abort(cs, "MPC8xx MMU model is not implemented\n");
> break;
> case POWERPC_MMU_BOOKE206:
> booke206_update_mas_tlb_miss(env, address, rw);
> @@ -1635,11 +1638,11 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0;
> return -1;
> case POWERPC_MMU_REAL:
> - cpu_abort(env, "PowerPC in real mode should never raise "
> + cpu_abort(cs, "PowerPC in real mode should never raise "
> "any MMU exceptions\n");
> return -1;
> default:
> - cpu_abort(env, "Unknown or invalid MMU model\n");
> + cpu_abort(cs, "Unknown or invalid MMU model\n");
> return -1;
> }
> break;
> @@ -1893,6 +1896,8 @@ void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong value)
> /* TLB management */
> void ppc_tlb_invalidate_all(CPUPPCState *env)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +
> switch (env->mmu_model) {
> case POWERPC_MMU_SOFT_6xx:
> case POWERPC_MMU_SOFT_74xx:
> @@ -1903,11 +1908,11 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
> ppc4xx_tlb_invalidate_all(env);
> break;
> case POWERPC_MMU_REAL:
> - cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
> + cpu_abort(CPU(cpu), "No TLB for PowerPC 4xx in real mode\n");
> break;
> case POWERPC_MMU_MPC8xx:
> /* XXX: TODO */
> - cpu_abort(env, "MPC8xx MMU model is not implemented\n");
> + cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");
> break;
> case POWERPC_MMU_BOOKE:
> tlb_flush(env, 1);
> @@ -1927,7 +1932,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
> break;
> default:
> /* XXX: TODO */
> - cpu_abort(env, "Unknown MMU model\n");
> + cpu_abort(CPU(cpu), "Unknown MMU model\n");
> break;
> }
> }
> @@ -1935,6 +1940,8 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
> void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
> {
> #if !defined(FLUSH_ALL_TLBS)
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +
> addr &= TARGET_PAGE_MASK;
> switch (env->mmu_model) {
> case POWERPC_MMU_SOFT_6xx:
> @@ -1949,19 +1956,19 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
> ppc4xx_tlb_invalidate_virt(env, addr, env->spr[SPR_40x_PID]);
> break;
> case POWERPC_MMU_REAL:
> - cpu_abort(env, "No TLB for PowerPC 4xx in real mode\n");
> + cpu_abort(CPU(cpu), "No TLB for PowerPC 4xx in real mode\n");
> break;
> case POWERPC_MMU_MPC8xx:
> /* XXX: TODO */
> - cpu_abort(env, "MPC8xx MMU model is not implemented\n");
> + cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");
> break;
> case POWERPC_MMU_BOOKE:
> /* XXX: TODO */
> - cpu_abort(env, "BookE MMU model is not implemented\n");
> + cpu_abort(CPU(cpu), "BookE MMU model is not implemented\n");
> break;
> case POWERPC_MMU_BOOKE206:
> /* XXX: TODO */
> - cpu_abort(env, "BookE 2.06 MMU model is not implemented\n");
> + cpu_abort(CPU(cpu), "BookE 2.06 MMU model is not implemented\n");
> break;
> case POWERPC_MMU_32B:
> case POWERPC_MMU_601:
> @@ -2002,7 +2009,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
> #endif /* defined(TARGET_PPC64) */
> default:
> /* XXX: TODO */
> - cpu_abort(env, "Unknown MMU model\n");
> + cpu_abort(CPU(cpu), "Unknown MMU model\n");
> break;
> }
> #else
> @@ -2316,6 +2323,7 @@ target_ulong helper_4xx_tlbre_lo(CPUPPCState *env, target_ulong entry)
> void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
> target_ulong val)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> ppcemb_tlb_t *tlb;
> target_ulong page, end;
>
> @@ -2339,7 +2347,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
> * of the ppc or ppc64 one
> */
> if ((val & PPC4XX_TLBHI_V) && tlb->size < TARGET_PAGE_SIZE) {
> - cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
> + cpu_abort(CPU(cpu), "TLB size " TARGET_FMT_lu " < %u "
> "are not supported (%d)\n",
> tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
> }
> @@ -2348,7 +2356,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
> tlb->prot |= PAGE_VALID;
> if (val & PPC4XX_TLBHI_E) {
> /* XXX: TO BE FIXED */
> - cpu_abort(env,
> + cpu_abort(CPU(cpu),
> "Little-endian TLB entries are not supported by now\n");
> }
> } else {
> @@ -2544,6 +2552,7 @@ target_ulong helper_440_tlbsx(CPUPPCState *env, target_ulong address)
>
> static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> uint32_t tlbncfg = 0;
> int esel = (env->spr[SPR_BOOKE_MAS0] & MAS0_ESEL_MASK) >> MAS0_ESEL_SHIFT;
> int ea = (env->spr[SPR_BOOKE_MAS2] & MAS2_EPN_MASK);
> @@ -2553,7 +2562,7 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env)
> tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlb];
>
> if ((tlbncfg & TLBnCFG_HES) && (env->spr[SPR_BOOKE_MAS0] & MAS0_HES)) {
> - cpu_abort(env, "we don't support HES yet\n");
> + cpu_abort(CPU(cpu), "we don't support HES yet\n");
> }
>
> return booke206_get_tlbm(env, tlb, ea, esel);
> @@ -2568,6 +2577,7 @@ void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid)
>
> void helper_booke206_tlbwe(CPUPPCState *env)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> uint32_t tlbncfg, tlbn;
> ppcmas_tlb_t *tlb;
> uint32_t size_tlb, size_ps;
> @@ -2621,7 +2631,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
> }
>
> if (msr_gs) {
> - cpu_abort(env, "missing HV implementation\n");
> + cpu_abort(CPU(cpu), "missing HV implementation\n");
> }
> tlb->mas7_3 = ((uint64_t)env->spr[SPR_BOOKE_MAS7] << 32) |
> env->spr[SPR_BOOKE_MAS3];
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index db5e526..1df82c5 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -4424,6 +4424,7 @@ enum fsl_e500_version {
>
> static void init_proc_e500 (CPUPPCState *env, int version)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> uint32_t tlbncfg[2];
> uint64_t ivor_mask;
> uint64_t ivpr_mask = 0xFFFF0000ULL;
> @@ -4482,7 +4483,7 @@ static void init_proc_e500 (CPUPPCState *env, int version)
> tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
> break;
> default:
> - cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
> + cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
> }
> #endif
> /* Cache sizes */
> @@ -4499,7 +4500,7 @@ static void init_proc_e500 (CPUPPCState *env, int version)
> l1cfg0 |= 0x1000000; /* 64 byte cache block size */
> break;
> default:
> - cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
> + cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
> }
> gen_spr_BookE206(env, 0x000000DF, tlbncfg);
> /* XXX : not implemented */
> diff --git a/target-s390x/cc_helper.c b/target-s390x/cc_helper.c
> index d845f20..9e676a5 100644
> --- a/target-s390x/cc_helper.c
> +++ b/target-s390x/cc_helper.c
> @@ -407,6 +407,7 @@ static uint32_t cc_calc_flogr(uint64_t dst)
> static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
> uint64_t src, uint64_t dst, uint64_t vr)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> uint32_t r = 0;
>
> switch (cc_op) {
> @@ -524,7 +525,7 @@ static uint32_t do_calc_cc(CPUS390XState *env, uint32_t cc_op,
> break;
>
> default:
> - cpu_abort(env, "Unknown CC operation: %s\n", cc_name(cc_op));
> + cpu_abort(CPU(cpu), "Unknown CC operation: %s\n", cc_name(cc_op));
> }
>
> HELPER_LOG("%s: %15s 0x%016lx 0x%016lx 0x%016lx = %d\n", __func__,
> diff --git a/target-s390x/fpu_helper.c b/target-s390x/fpu_helper.c
> index 94375b6..3e9c7b2 100644
> --- a/target-s390x/fpu_helper.c
> +++ b/target-s390x/fpu_helper.c
> @@ -80,6 +80,8 @@ static void handle_exceptions(CPUS390XState *env, uintptr_t retaddr)
>
> static inline int float_comp_to_cc(CPUS390XState *env, int float_compare)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> +
> switch (float_compare) {
> case float_relation_equal:
> return 0;
> @@ -90,7 +92,7 @@ static inline int float_comp_to_cc(CPUS390XState *env, int float_compare)
> case float_relation_unordered:
> return 3;
> default:
> - cpu_abort(env, "unknown return value for float compare\n");
> + cpu_abort(CPU(cpu), "unknown return value for float compare\n");
> }
> }
>
> diff --git a/target-s390x/helper.c b/target-s390x/helper.c
> index 207af52..96f57d2 100644
> --- a/target-s390x/helper.c
> +++ b/target-s390x/helper.c
> @@ -116,6 +116,7 @@ static void trigger_pgm_exception(CPUS390XState *env, uint32_t code,
>
> static int trans_bits(CPUS390XState *env, uint64_t mode)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> int bits = 0;
>
> switch (mode) {
> @@ -129,7 +130,7 @@ static int trans_bits(CPUS390XState *env, uint64_t mode)
> bits = 3;
> break;
> default:
> - cpu_abort(env, "unknown asc mode\n");
> + cpu_abort(CPU(cpu), "unknown asc mode\n");
> break;
> }
>
> @@ -474,13 +475,14 @@ static uint64_t get_psw_mask(CPUS390XState *env)
>
> static LowCore *cpu_map_lowcore(CPUS390XState *env)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> LowCore *lowcore;
> hwaddr len = sizeof(LowCore);
>
> lowcore = cpu_physical_memory_map(env->psa, &len, 1);
>
> if (len < sizeof(LowCore)) {
> - cpu_abort(env, "Could not map lowcore\n");
> + cpu_abort(CPU(cpu), "Could not map lowcore\n");
> }
>
> return lowcore;
> @@ -578,16 +580,17 @@ static void do_program_interrupt(CPUS390XState *env)
>
> static void do_ext_interrupt(CPUS390XState *env)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> uint64_t mask, addr;
> LowCore *lowcore;
> ExtQueue *q;
>
> if (!(env->psw.mask & PSW_MASK_EXT)) {
> - cpu_abort(env, "Ext int w/o ext mask\n");
> + cpu_abort(CPU(cpu), "Ext int w/o ext mask\n");
> }
>
> if (env->ext_index < 0 || env->ext_index > MAX_EXT_QUEUE) {
> - cpu_abort(env, "Ext queue overrun: %d\n", env->ext_index);
> + cpu_abort(CPU(cpu), "Ext queue overrun: %d\n", env->ext_index);
> }
>
> q = &env->ext_queue[env->ext_index];
> @@ -617,6 +620,7 @@ static void do_ext_interrupt(CPUS390XState *env)
>
> static void do_io_interrupt(CPUS390XState *env)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> LowCore *lowcore;
> IOIntQueue *q;
> uint8_t isc;
> @@ -624,7 +628,7 @@ static void do_io_interrupt(CPUS390XState *env)
> int found = 0;
>
> if (!(env->psw.mask & PSW_MASK_IO)) {
> - cpu_abort(env, "I/O int w/o I/O mask\n");
> + cpu_abort(CPU(cpu), "I/O int w/o I/O mask\n");
> }
>
> for (isc = 0; isc < ARRAY_SIZE(env->io_index); isc++) {
> @@ -634,7 +638,7 @@ static void do_io_interrupt(CPUS390XState *env)
> continue;
> }
> if (env->io_index[isc] > MAX_IO_QUEUE) {
> - cpu_abort(env, "I/O queue overrun for isc %d: %d\n",
> + cpu_abort(CPU(cpu), "I/O queue overrun for isc %d: %d\n",
> isc, env->io_index[isc]);
> }
>
> @@ -681,24 +685,25 @@ static void do_io_interrupt(CPUS390XState *env)
>
> static void do_mchk_interrupt(CPUS390XState *env)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> uint64_t mask, addr;
> LowCore *lowcore;
> MchkQueue *q;
> int i;
>
> if (!(env->psw.mask & PSW_MASK_MCHECK)) {
> - cpu_abort(env, "Machine check w/o mchk mask\n");
> + cpu_abort(CPU(cpu), "Machine check w/o mchk mask\n");
> }
>
> if (env->mchk_index < 0 || env->mchk_index > MAX_MCHK_QUEUE) {
> - cpu_abort(env, "Mchk queue overrun: %d\n", env->mchk_index);
> + cpu_abort(CPU(cpu), "Mchk queue overrun: %d\n", env->mchk_index);
> }
>
> q = &env->mchk_queue[env->mchk_index];
>
> if (q->type != 1) {
> /* Don't know how to handle this... */
> - cpu_abort(env, "Unknown machine check type %d\n", q->type);
> + cpu_abort(CPU(cpu), "Unknown machine check type %d\n", q->type);
> }
> if (!(env->cregs[14] & (1 << 28))) {
> /* CRW machine checks disabled */
> diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
> index 6a79385..cd84337 100644
> --- a/target-s390x/mem_helper.c
> +++ b/target-s390x/mem_helper.c
> @@ -72,6 +72,7 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest,
> uint8_t byte)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> hwaddr dest_phys;
> hwaddr len = l;
> void *dest_p;
> @@ -80,7 +81,7 @@ static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest,
>
> if (mmu_translate(env, dest, 1, asc, &dest_phys, &flags)) {
> cpu_stb_data(env, dest, byte);
> - cpu_abort(env, "should never reach here");
> + cpu_abort(CPU(cpu), "should never reach here");
> }
> dest_phys |= dest & ~TARGET_PAGE_MASK;
>
> @@ -94,6 +95,7 @@ static void mvc_fast_memset(CPUS390XState *env, uint32_t l, uint64_t dest,
> static void mvc_fast_memmove(CPUS390XState *env, uint32_t l, uint64_t dest,
> uint64_t src)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> hwaddr dest_phys;
> hwaddr src_phys;
> hwaddr len = l;
> @@ -104,13 +106,13 @@ static void mvc_fast_memmove(CPUS390XState *env, uint32_t l, uint64_t dest,
>
> if (mmu_translate(env, dest, 1, asc, &dest_phys, &flags)) {
> cpu_stb_data(env, dest, 0);
> - cpu_abort(env, "should never reach here");
> + cpu_abort(CPU(cpu), "should never reach here");
> }
> dest_phys |= dest & ~TARGET_PAGE_MASK;
>
> if (mmu_translate(env, src, 0, asc, &src_phys, &flags)) {
> cpu_ldub_data(env, src);
> - cpu_abort(env, "should never reach here");
> + cpu_abort(CPU(cpu), "should never reach here");
> }
> src_phys |= src & ~TARGET_PAGE_MASK;
>
> @@ -483,6 +485,7 @@ static uint32_t helper_icm(CPUS390XState *env, uint32_t r1, uint64_t address,
> uint32_t HELPER(ex)(CPUS390XState *env, uint32_t cc, uint64_t v1,
> uint64_t addr, uint64_t ret)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> uint16_t insn = cpu_lduw_code(env, addr);
>
> HELPER_LOG("%s: v1 0x%lx addr 0x%lx insn 0x%x\n", __func__, v1, addr,
> @@ -534,7 +537,7 @@ uint32_t HELPER(ex)(CPUS390XState *env, uint32_t cc, uint64_t v1,
> cc = helper_icm(env, r1, get_address(env, 0, b2, d2), r3);
> } else {
> abort:
> - cpu_abort(env, "EXECUTE on instruction prefix 0x%x not implemented\n",
> + cpu_abort(CPU(cpu), "EXECUTE on instruction prefix 0x%x not implemented\n",
> insn);
> }
> return cc;
> diff --git a/target-sh4/helper.c b/target-sh4/helper.c
> index b444da1..7add92d 100644
> --- a/target-sh4/helper.c
> +++ b/target-sh4/helper.c
> @@ -234,15 +234,21 @@ static void update_itlb_use(CPUSH4State * env, int itlbnb)
>
> static int itlb_replacement(CPUSH4State * env)
> {
> - if ((env->mmucr & 0xe0000000) == 0xe0000000)
> + SuperHCPU *cpu = sh_env_get_cpu(env);
> +
> + if ((env->mmucr & 0xe0000000) == 0xe0000000) {
> return 0;
> - if ((env->mmucr & 0x98000000) == 0x18000000)
> + }
> + if ((env->mmucr & 0x98000000) == 0x18000000) {
> return 1;
> - if ((env->mmucr & 0x54000000) == 0x04000000)
> + }
> + if ((env->mmucr & 0x54000000) == 0x04000000) {
> return 2;
> - if ((env->mmucr & 0x2c000000) == 0x00000000)
> + }
> + if ((env->mmucr & 0x2c000000) == 0x00000000) {
> return 3;
> - cpu_abort(env, "Unhandled itlb_replacement");
> + }
> + cpu_abort(CPU(cpu), "Unhandled itlb_replacement");
> }
>
> /* Find the corresponding entry in the right TLB
> @@ -498,7 +504,7 @@ int superh_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
> cs->exception_index = 0x100;
> break;
> default:
> - cpu_abort(env, "Unhandled MMU fault");
> + cpu_abort(cs, "Unhandled MMU fault");
> }
> return 1;
> }
> @@ -522,6 +528,7 @@ hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
>
> void cpu_load_tlb(CPUSH4State * env)
> {
> + SuperHCPU *cpu = sh_env_get_cpu(env);
> int n = cpu_mmucr_urc(env->mmucr);
> tlb_t * entry = &env->utlb[n];
>
> @@ -551,7 +558,7 @@ void cpu_load_tlb(CPUSH4State * env)
> entry->size = 1024 * 1024; /* 1M */
> break;
> default:
> - cpu_abort(env, "Unhandled load_tlb");
> + cpu_abort(CPU(cpu), "Unhandled load_tlb");
> break;
> }
> entry->sh = (uint8_t)cpu_ptel_sh(env->ptel);
> diff --git a/target-sh4/op_helper.c b/target-sh4/op_helper.c
> index b3ce7ba..720a97b 100644
> --- a/target-sh4/op_helper.c
> +++ b/target-sh4/op_helper.c
> @@ -58,8 +58,10 @@ void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
> void helper_ldtlb(CPUSH4State *env)
> {
> #ifdef CONFIG_USER_ONLY
> + SuperHCPU *cpu = sh_env_get_cpu(env);
> +
> /* XXXXX */
> - cpu_abort(env, "Unhandled ldtlb");
> + cpu_abort(CPU(cpu), "Unhandled ldtlb");
> #else
> cpu_load_tlb(env);
> #endif
> diff --git a/target-sparc/int32_helper.c b/target-sparc/int32_helper.c
> index f350a90..7c380ba 100644
> --- a/target-sparc/int32_helper.c
> +++ b/target-sparc/int32_helper.c
> @@ -109,7 +109,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
> env->def->features & CPU_FEATURE_TA0_SHUTDOWN) {
> qemu_system_shutdown_request();
> } else {
> - cpu_abort(env, "Trap 0x%02x while interrupts disabled, Error state",
> + cpu_abort(cs, "Trap 0x%02x while interrupts disabled, Error state",
> cs->exception_index);
> }
> return;
> diff --git a/target-sparc/int64_helper.c b/target-sparc/int64_helper.c
> index 1744245..bf24232 100644
> --- a/target-sparc/int64_helper.c
> +++ b/target-sparc/int64_helper.c
> @@ -111,7 +111,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
> #endif
> #if !defined(CONFIG_USER_ONLY)
> if (env->tl >= env->maxtl) {
> - cpu_abort(env, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
> + cpu_abort(cs, "Trap 0x%04x while trap level (%d) >= MAXTL (%d),"
> " Error state", cs->exception_index, env->tl, env->maxtl);
> return;
> }
> diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
> index eece271..f91ed93 100644
> --- a/target-unicore32/helper.c
> +++ b/target-unicore32/helper.c
> @@ -236,26 +236,22 @@ void helper_cp1_putc(target_ulong x)
> #ifdef CONFIG_USER_ONLY
> void switch_mode(CPUUniCore32State *env, int mode)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> +
> if (mode != ASR_MODE_USER) {
> - cpu_abort(env, "Tried to switch out of user mode\n");
> + cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
> }
> }
>
> void uc32_cpu_do_interrupt(CPUState *cs)
> {
> - UniCore32CPU *cpu = UNICORE32_CPU(cs);
> - CPUUniCore32State *env = &cpu->env;
> -
> - cpu_abort(env, "NO interrupt in user mode\n");
> + cpu_abort(cs, "NO interrupt in user mode\n");
> }
>
> int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
> int access_type, int mmu_idx)
> {
> - UniCore32CPU *cpu = UNICORE32_CPU(cs);
> - CPUUniCore32State *env = &cpu->env;
> -
> - cpu_abort(env, "NO mmu fault in user mode\n");
> + cpu_abort(cs, "NO mmu fault in user mode\n");
> return 1;
> }
> #endif
> diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
> index d0527e5..8c2acf2 100644
> --- a/target-unicore32/softmmu.c
> +++ b/target-unicore32/softmmu.c
> @@ -33,6 +33,8 @@
> /* Map CPU modes onto saved register banks. */
> static inline int bank_number(CPUUniCore32State *env, int mode)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> +
> switch (mode) {
> case ASR_MODE_USER:
> case ASR_MODE_SUSR:
> @@ -46,7 +48,7 @@ static inline int bank_number(CPUUniCore32State *env, int mode)
> case ASR_MODE_INTR:
> return 4;
> }
> - cpu_abort(env, "Bad mode %x\n", mode);
> + cpu_abort(CPU(cpu), "Bad mode %x\n", mode);
> return -1;
> }
>
> @@ -99,7 +101,7 @@ void uc32_cpu_do_interrupt(CPUState *cs)
> addr = 0x18;
> break;
> default:
> - cpu_abort(env, "Unhandled exception 0x%x\n", cs->exception_index);
> + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
> return;
> }
> /* High vectors. */
> @@ -121,6 +123,7 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
> int access_type, int is_user, uint32_t *phys_ptr, int *prot,
> target_ulong *page_size)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> int code;
> uint32_t table;
> uint32_t desc;
> @@ -167,11 +170,11 @@ static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
> *page_size = TARGET_PAGE_SIZE;
> break;
> default:
> - cpu_abort(env, "wrong page type!");
> + cpu_abort(CPU(cpu), "wrong page type!");
> }
> break;
> default:
> - cpu_abort(env, "wrong page type!");
> + cpu_abort(CPU(cpu), "wrong page type!");
> }
>
> *phys_ptr = phys_addr;
> @@ -267,6 +270,6 @@ hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
> {
> UniCore32CPU *cpu = UNICORE32_CPU(cs);
>
> - cpu_abort(&cpu->env, "%s not supported yet\n", __func__);
> + cpu_abort(CPU(cpu), "%s not supported yet\n", __func__);
> return addr;
> }
> diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
> index b4bee99..532d825 100644
> --- a/target-unicore32/translate.c
> +++ b/target-unicore32/translate.c
> @@ -179,7 +179,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
> #define UCOP_SET_L UCOP_SET(24)
> #define UCOP_SET_S UCOP_SET(24)
>
> -#define ILLEGAL cpu_abort(env, \
> +#define ILLEGAL cpu_abort(CPU(cpu), \
> "Illegal UniCore32 instruction %x at line %d!", \
> insn, __LINE__)
>
> @@ -187,6 +187,7 @@ static void store_reg(DisasContext *s, int reg, TCGv var)
> static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s,
> uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> TCGv tmp, tmp2, tmp3;
> if ((insn & 0xfe000000) == 0xe0000000) {
> tmp2 = new_tmp();
> @@ -212,6 +213,7 @@ static void disas_cp0_insn(CPUUniCore32State *env, DisasContext *s,
> static void disas_ocd_insn(CPUUniCore32State *env, DisasContext *s,
> uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> TCGv tmp;
>
> if ((insn & 0xff003fff) == 0xe1000400) {
> @@ -692,6 +694,7 @@ static inline long ucf64_reg_offset(int reg)
> /* UniCore-F64 single load/store I_offset */
> static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> int offset;
> TCGv tmp;
> TCGv addr;
> @@ -738,6 +741,7 @@ static void do_ucf64_ldst_i(CPUUniCore32State *env, DisasContext *s, uint32_t in
> /* UniCore-F64 load/store multiple words */
> static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> unsigned int i;
> int j, n, freg;
> TCGv tmp;
> @@ -823,6 +827,7 @@ static void do_ucf64_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t in
> /* UniCore-F64 mrc/mcr */
> static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> TCGv tmp;
>
> if ((insn & 0xfe0003ff) == 0xe2000000) {
> @@ -887,6 +892,8 @@ static void do_ucf64_trans(CPUUniCore32State *env, DisasContext *s, uint32_t ins
> /* UniCore-F64 convert instructions */
> static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> +
> if (UCOP_UCF64_FMT == 3) {
> ILLEGAL;
> }
> @@ -953,6 +960,8 @@ static void do_ucf64_fcvt(CPUUniCore32State *env, DisasContext *s, uint32_t insn
> /* UniCore-F64 compare instructions */
> static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> +
> if (UCOP_SET(25)) {
> ILLEGAL;
> }
> @@ -1031,6 +1040,8 @@ static void do_ucf64_fcmp(CPUUniCore32State *env, DisasContext *s, uint32_t insn
> /* UniCore-F64 data processing */
> static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> +
> if (UCOP_UCF64_FMT == 3) {
> ILLEGAL;
> }
> @@ -1064,6 +1075,8 @@ static void do_ucf64_datap(CPUUniCore32State *env, DisasContext *s, uint32_t ins
> /* Disassemble an F64 instruction */
> static void disas_ucf64_insn(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> +
> if (!UCOP_SET(29)) {
> if (UCOP_SET(26)) {
> do_ucf64_ldst_m(env, s, insn);
> @@ -1170,6 +1183,8 @@ static void gen_exception_return(DisasContext *s, TCGv pc)
> static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s,
> uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> +
> switch (UCOP_CPNUM) {
> #ifndef CONFIG_USER_ONLY
> case 0:
> @@ -1184,13 +1199,14 @@ static void disas_coproc_insn(CPUUniCore32State *env, DisasContext *s,
> break;
> default:
> /* Unknown coprocessor. */
> - cpu_abort(env, "Unknown coprocessor!");
> + cpu_abort(CPU(cpu), "Unknown coprocessor!");
> }
> }
>
> /* data processing instructions */
> static void do_datap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> TCGv tmp;
> TCGv tmp2;
> int logic_cc;
> @@ -1424,6 +1440,7 @@ static void do_mult(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> /* miscellaneous instructions */
> static void do_misc(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> unsigned int val;
> TCGv tmp;
>
> @@ -1549,6 +1566,7 @@ static void do_ldst_ir(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> /* SWP instruction */
> static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> TCGv addr;
> TCGv tmp;
> TCGv tmp2;
> @@ -1576,6 +1594,7 @@ static void do_swap(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> /* load/store hw/sb */
> static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> TCGv addr;
> TCGv tmp;
>
> @@ -1628,6 +1647,7 @@ static void do_ldst_hwsb(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> /* load/store multiple words */
> static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> unsigned int val, i, mmu_idx;
> int j, n, reg, user, loaded_base;
> TCGv tmp;
> @@ -1769,6 +1789,7 @@ static void do_ldst_m(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> /* branch (and link) */
> static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> unsigned int val;
> int32_t offset;
> TCGv tmp;
> @@ -1798,6 +1819,7 @@ static void do_branch(CPUUniCore32State *env, DisasContext *s, uint32_t insn)
>
> static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> unsigned int insn;
>
> if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
> @@ -1981,7 +2003,7 @@ static inline void gen_intermediate_code_internal(UniCore32CPU *cpu,
> if (dc->condjmp) {
> /* FIXME: This can theoretically happen with self-modifying
> code. */
> - cpu_abort(env, "IO on conditional branch instruction");
> + cpu_abort(cs, "IO on conditional branch instruction");
> }
> gen_io_end();
> }
> diff --git a/target-unicore32/ucf64_helper.c b/target-unicore32/ucf64_helper.c
> index a516edd..34fa2a5 100644
> --- a/target-unicore32/ucf64_helper.c
> +++ b/target-unicore32/ucf64_helper.c
> @@ -76,6 +76,7 @@ static inline int ucf64_exceptbits_to_host(int target_bits)
>
> void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> int i;
> uint32_t changed;
>
> @@ -99,7 +100,7 @@ void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
> i = float_round_down;
> break;
> default: /* 100 and 101 not implement */
> - cpu_abort(env, "Unsupported UniCore-F64 round mode");
> + cpu_abort(CPU(cpu), "Unsupported UniCore-F64 round mode");
> }
> set_float_rounding_mode(i, &env->ucf64.fp_status);
> }
> diff --git a/translate-all.c b/translate-all.c
> index 37b573b..356f2ca 100644
> --- a/translate-all.c
> +++ b/translate-all.c
> @@ -682,7 +682,7 @@ static void page_flush_tb(void)
> /* XXX: tb_flush is currently not thread safe */
> void tb_flush(CPUArchState *env1)
> {
> - CPUState *cpu;
> + CPUState *cpu = ENV_GET_CPU(env1);
>
> #if defined(DEBUG_FLUSH)
> printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n",
> @@ -693,7 +693,7 @@ void tb_flush(CPUArchState *env1)
> #endif
> if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer)
> > tcg_ctx.code_gen_buffer_size) {
> - cpu_abort(env1, "Internal error: code buffer overflow\n");
> + cpu_abort(cpu, "Internal error: code buffer overflow\n");
> }
> tcg_ctx.tb_ctx.nb_tbs = 0;
>
> @@ -1379,12 +1379,11 @@ void tb_invalidate_phys_addr(hwaddr addr)
>
> void tb_check_watchpoint(CPUState *cpu)
> {
> - CPUArchState *env = cpu->env_ptr;
> TranslationBlock *tb;
>
> tb = tb_find_pc(cpu->mem_io_pc);
> if (!tb) {
> - cpu_abort(env, "check_watchpoint: could not find TB for pc=%p",
> + cpu_abort(cpu, "check_watchpoint: could not find TB for pc=%p",
> (void *)cpu->mem_io_pc);
> }
> cpu_restore_state_from_tb(cpu, tb, cpu->mem_io_pc);
> @@ -1395,7 +1394,6 @@ void tb_check_watchpoint(CPUState *cpu)
> /* mask must never be zero, except for A20 change call */
> static void tcg_handle_interrupt(CPUState *cpu, int mask)
> {
> - CPUArchState *env = cpu->env_ptr;
> int old_mask;
>
> old_mask = cpu->interrupt_request;
> @@ -1414,7 +1412,7 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask)
> cpu->icount_decr.u16.high = 0xffff;
> if (!cpu_can_do_io(cpu)
> && (mask & ~old_mask) != 0) {
> - cpu_abort(env, "Raised interrupt while not in I/O function");
> + cpu_abort(cpu, "Raised interrupt while not in I/O function");
> }
> } else {
> cpu->tcg_exit_req = 1;
> @@ -1427,7 +1425,9 @@ CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt;
> must be at the end of the TB */
> void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
> {
> +#if defined(TARGET_MIPS) || defined(TARGET_SH4)
> CPUArchState *env = cpu->env_ptr;
> +#endif
> TranslationBlock *tb;
> uint32_t n, cflags;
> target_ulong pc, cs_base;
> @@ -1435,7 +1435,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
>
> tb = tb_find_pc(retaddr);
> if (!tb) {
> - cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p",
> + cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=%p",
> (void *)retaddr);
> }
> n = cpu->icount_decr.u16.low + tb->icount;
> @@ -1465,7 +1465,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
> #endif
> /* This should never happen. */
> if (n > CF_COUNT_MASK) {
> - cpu_abort(env, "TB too big during recompile");
> + cpu_abort(cpu, "TB too big during recompile");
> }
>
> cflags = n | CF_LAST_IO;
target-openrisc: Tested-by: Jia Liu <proljc@gmail.com>
> --
> 1.8.1.4
>
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [RFC qom-cpu 35/41] target-cris: Replace DisasContext::env field with CRISCPU
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (33 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 34/41] exec: Change cpu_abort() " Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 36/41] target-lm32: Replace DisasContext::env field with LM32CPU Andreas Färber
` (8 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Edgar E. Iglesias, Andreas Färber
This cleans up repeated cris_env_get_cpu() for cpu_abort().
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-cris/translate.c | 16 ++++++++--------
target-cris/translate_v10.c | 16 ++++++++--------
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/target-cris/translate.c b/target-cris/translate.c
index bf15ed6..6f593d6 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -74,7 +74,7 @@ static TCGv env_pc;
/* This is the state at translation time. */
typedef struct DisasContext {
- CPUCRISState *env;
+ CRISCPU *cpu;
target_ulong pc, ppc;
/* Decoder. */
@@ -129,7 +129,7 @@ static void gen_BUG(DisasContext *dc, const char *file, int line)
{
printf("BUG: pc=%x %s %d\n", dc->pc, file, line);
qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
- cpu_abort(CPU(cris_env_get_cpu(dc->env)), "%s:%d\n", file, line);
+ cpu_abort(CPU(dc->cpu), "%s:%d\n", file, line);
}
static const char *regnames[] =
@@ -272,7 +272,7 @@ static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,
break;
}
default:
- cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Invalid fetch size %d\n", size);
+ cpu_abort(CPU(dc->cpu), "Invalid fetch size %d\n", size);
break;
}
return r;
@@ -1125,7 +1125,7 @@ static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
{
- int mem_index = cpu_mmu_index(CPU(cris_env_get_cpu(dc->env)));
+ int mem_index = cpu_mmu_index(CPU(dc->cpu));
/* If we get a fault on a delayslot we must keep the jmp state in
the cpu-state to be able to re-execute the jmp. */
@@ -1139,7 +1139,7 @@ static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
unsigned int size, int sign)
{
- int mem_index = cpu_mmu_index(CPU(cris_env_get_cpu(dc->env)));
+ int mem_index = cpu_mmu_index(CPU(dc->cpu));
/* If we get a fault on a delayslot we must keep the jmp state in
the cpu-state to be able to re-execute the jmp. */
@@ -1169,7 +1169,7 @@ static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
unsigned int size)
{
- int mem_index = cpu_mmu_index(CPU(cris_env_get_cpu(dc->env)));
+ int mem_index = cpu_mmu_index(CPU(dc->cpu));
/* If we get a fault on a delayslot we must keep the jmp state in
the cpu-state to be able to re-execute the jmp. */
@@ -3191,7 +3191,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
* delayslot, like in real hw.
*/
pc_start = tb->pc & ~1;
- dc->env = env;
+ dc->cpu = cpu;
dc->tb = tb;
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
@@ -3412,7 +3412,7 @@ gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
#if !DISAS_CRIS
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
log_target_disas(env, pc_start, dc->pc - pc_start,
- dc->env->pregs[PR_VR]);
+ env->pregs[PR_VR]);
qemu_log("\nisize=%d osize=%td\n",
dc->pc - pc_start, tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf);
}
diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
index 734225f..4d77f16 100644
--- a/target-cris/translate_v10.c
+++ b/target-cris/translate_v10.c
@@ -96,7 +96,7 @@ static void gen_store_v10_conditional(DisasContext *dc, TCGv addr, TCGv val,
static void gen_store_v10(DisasContext *dc, TCGv addr, TCGv val,
unsigned int size)
{
- int mem_index = cpu_mmu_index(CPU(cris_env_get_cpu(dc->env)));
+ int mem_index = cpu_mmu_index(CPU(dc->cpu));
/* If we get a fault on a delayslot we must keep the jmp state in
the cpu-state to be able to re-execute the jmp. */
@@ -340,7 +340,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc)
default:
LOG_DIS("pc=%x mode=%x quickimm %d r%d r%d\n",
dc->pc, dc->mode, dc->opcode, dc->src, dc->dst);
- cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled quickimm\n");
+ cpu_abort(CPU(dc->cpu), "Unhandled quickimm\n");
break;
}
return 2;
@@ -651,7 +651,7 @@ static unsigned int dec10_reg(DisasContext *dc)
case 2: tmp = 1; break;
case 1: tmp = 0; break;
default:
- cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled BIAP");
+ cpu_abort(CPU(dc->cpu), "Unhandled BIAP");
break;
}
@@ -669,7 +669,7 @@ static unsigned int dec10_reg(DisasContext *dc)
default:
LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
dc->opcode, dc->src, dc->dst);
- cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode");
+ cpu_abort(CPU(dc->cpu), "Unhandled opcode");
break;
}
} else {
@@ -745,7 +745,7 @@ static unsigned int dec10_reg(DisasContext *dc)
default:
LOG_DIS("pc=%x reg %d r%d r%d\n", dc->pc,
dc->opcode, dc->src, dc->dst);
- cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode");
+ cpu_abort(CPU(dc->cpu), "Unhandled opcode");
break;
}
}
@@ -1006,7 +1006,7 @@ static int dec10_bdap_m(CPUCRISState *env, DisasContext *dc, int size)
if (!dc->postinc && (dc->ir & (1 << 11))) {
int simm = dc->ir & 0xff;
- /* cpu_abort(dc->env, "Unhandled opcode"); */
+ /* cpu_abort(CPU(dc->cpu), "Unhandled opcode"); */
/* sign extended. */
simm = (int8_t)simm;
@@ -1105,7 +1105,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
default:
LOG_DIS("pc=%x var-ind.%d %d r%d r%d\n",
dc->pc, size, dc->opcode, dc->src, dc->dst);
- cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode");
+ cpu_abort(CPU(dc->cpu), "Unhandled opcode");
break;
}
return insn_len;
@@ -1198,7 +1198,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc)
break;
default:
LOG_DIS("ERROR pc=%x opcode=%d\n", dc->pc, dc->opcode);
- cpu_abort(CPU(cris_env_get_cpu(dc->env)), "Unhandled opcode");
+ cpu_abort(CPU(dc->cpu), "Unhandled opcode");
break;
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 36/41] target-lm32: Replace DisasContext::env field with LM32CPU
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (34 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 35/41] target-cris: Replace DisasContext::env field with CRISCPU Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 37/41] target-microblaze: Replace DisasContext::env field with MicroBlazeCPU Andreas Färber
` (7 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Michael Walle, Andreas Färber
This cleans up some lm32_env_get_cpu() introduced for cpu_abort().
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-lm32/translate.c | 60 ++++++++++++++++++++++++-------------------------
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 532345b..57b91c4 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -64,7 +64,7 @@ enum {
/* This is the state at translation time. */
typedef struct DisasContext {
- CPULM32State *env;
+ LM32CPU *cpu;
target_ulong pc;
/* Decoder. */
@@ -421,8 +421,8 @@ static void dec_divu(DisasContext *dc)
LOG_DIS("divu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
- if (!(dc->env->features & LM32_FEATURE_DIVIDE)) {
- cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware divider is not available\n");
+ if (!(dc->cpu->env.features & LM32_FEATURE_DIVIDE)) {
+ cpu_abort(CPU(dc->cpu), "hardware divider is not available\n");
}
l1 = gen_new_label();
@@ -499,8 +499,8 @@ static void dec_modu(DisasContext *dc)
LOG_DIS("modu r%d, r%d, %d\n", dc->r2, dc->r0, dc->r1);
- if (!(dc->env->features & LM32_FEATURE_DIVIDE)) {
- cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware divider is not available\n");
+ if (!(dc->cpu->env.features & LM32_FEATURE_DIVIDE)) {
+ cpu_abort(CPU(dc->cpu), "hardware divider is not available\n");
}
l1 = gen_new_label();
@@ -520,8 +520,8 @@ static void dec_mul(DisasContext *dc)
LOG_DIS("mul r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
}
- if (!(dc->env->features & LM32_FEATURE_MULTIPLY)) {
- cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware multiplier is not available\n");
+ if (!(dc->cpu->env.features & LM32_FEATURE_MULTIPLY)) {
+ cpu_abort(CPU(dc->cpu), "hardware multiplier is not available\n");
}
if (dc->format == OP_FMT_RI) {
@@ -590,7 +590,7 @@ static void dec_scall(DisasContext *dc)
} else if (dc->imm5 == 2) {
LOG_DIS("break\n");
} else {
- cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "invalid opcode\n");
+ cpu_abort(CPU(dc->cpu), "invalid opcode\n");
}
if (dc->imm5 == 7) {
@@ -647,10 +647,10 @@ static void dec_rcsr(DisasContext *dc)
case CSR_WP1:
case CSR_WP2:
case CSR_WP3:
- cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "invalid read access csr=%x\n", dc->csr);
+ cpu_abort(CPU(dc->cpu), "invalid read access csr=%x\n", dc->csr);
break;
default:
- cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "read_csr: unknown csr=%x\n", dc->csr);
+ cpu_abort(CPU(dc->cpu), "read_csr: unknown csr=%x\n", dc->csr);
break;
}
}
@@ -671,8 +671,8 @@ static void dec_sextb(DisasContext *dc)
{
LOG_DIS("sextb r%d, r%d\n", dc->r2, dc->r0);
- if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) {
- cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware sign extender is not available\n");
+ if (!(dc->cpu->env.features & LM32_FEATURE_SIGN_EXTEND)) {
+ cpu_abort(CPU(dc->cpu), "hardware sign extender is not available\n");
}
tcg_gen_ext8s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
@@ -682,8 +682,8 @@ static void dec_sexth(DisasContext *dc)
{
LOG_DIS("sexth r%d, r%d\n", dc->r2, dc->r0);
- if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) {
- cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware sign extender is not available\n");
+ if (!(dc->cpu->env.features & LM32_FEATURE_SIGN_EXTEND)) {
+ cpu_abort(CPU(dc->cpu), "hardware sign extender is not available\n");
}
tcg_gen_ext16s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
@@ -709,8 +709,8 @@ static void dec_sl(DisasContext *dc)
LOG_DIS("sl r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
}
- if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
- cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware shifter is not available\n");
+ if (!(dc->cpu->env.features & LM32_FEATURE_SHIFT)) {
+ cpu_abort(CPU(dc->cpu), "hardware shifter is not available\n");
}
if (dc->format == OP_FMT_RI) {
@@ -731,12 +731,12 @@ static void dec_sr(DisasContext *dc)
LOG_DIS("sr r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
}
- if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
+ if (!(dc->cpu->env.features & LM32_FEATURE_SHIFT)) {
if (dc->format == OP_FMT_RI) {
/* TODO: check r1 == 1 during runtime */
} else {
if (dc->imm5 != 1) {
- cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware shifter is not available\n");
+ cpu_abort(CPU(dc->cpu), "hardware shifter is not available\n");
}
}
}
@@ -759,12 +759,12 @@ static void dec_sru(DisasContext *dc)
LOG_DIS("sru r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
}
- if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
+ if (!(dc->cpu->env.features & LM32_FEATURE_SHIFT)) {
if (dc->format == OP_FMT_RI) {
/* TODO: check r1 == 1 during runtime */
} else {
if (dc->imm5 != 1) {
- cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "hardware shifter is not available\n");
+ cpu_abort(CPU(dc->cpu), "hardware shifter is not available\n");
}
}
}
@@ -802,7 +802,7 @@ static void dec_user(DisasContext *dc)
{
LOG_DIS("user");
- cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "user insn undefined\n");
+ cpu_abort(CPU(dc->cpu), "user insn undefined\n");
}
static void dec_wcsr(DisasContext *dc)
@@ -867,8 +867,8 @@ static void dec_wcsr(DisasContext *dc)
case CSR_BP2:
case CSR_BP3:
no = dc->csr - CSR_BP0;
- if (dc->env->num_bps <= no) {
- cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "breakpoint #%i is not available\n", no);
+ if (dc->cpu->env.num_bps <= no) {
+ cpu_abort(CPU(dc->cpu), "breakpoint #%i is not available\n", no);
}
tcg_gen_mov_tl(cpu_bp[no], cpu_R[dc->r1]);
break;
@@ -877,17 +877,17 @@ static void dec_wcsr(DisasContext *dc)
case CSR_WP2:
case CSR_WP3:
no = dc->csr - CSR_WP0;
- if (dc->env->num_wps <= no) {
- cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "watchpoint #%i is not available\n", no);
+ if (dc->cpu->env.num_wps <= no) {
+ cpu_abort(CPU(dc->cpu), "watchpoint #%i is not available\n", no);
}
tcg_gen_mov_tl(cpu_wp[no], cpu_R[dc->r1]);
break;
case CSR_CC:
case CSR_CFG:
- cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "invalid write access csr=%x\n", dc->csr);
+ cpu_abort(CPU(dc->cpu), "invalid write access csr=%x\n", dc->csr);
break;
default:
- cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "write_csr unknown csr=%x\n", dc->csr);
+ cpu_abort(CPU(dc->cpu), "write_csr unknown csr=%x\n", dc->csr);
break;
}
}
@@ -933,7 +933,7 @@ static void dec_xor(DisasContext *dc)
static void dec_ill(DisasContext *dc)
{
- cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "unknown opcode 0x%02x\n", dc->opcode);
+ cpu_abort(CPU(dc->cpu), "unknown opcode 0x%02x\n", dc->opcode);
}
typedef void (*DecoderInfo)(DisasContext *dc);
@@ -967,7 +967,7 @@ static inline void decode(DisasContext *dc, uint32_t ir)
LOG_DIS("nr_nops=%d\t", dc->nr_nops);
dc->nr_nops++;
if (dc->nr_nops > 4) {
- cpu_abort(CPU(lm32_env_get_cpu(dc->env)), "fetching nop sequence\n");
+ cpu_abort(CPU(dc->cpu), "fetching nop sequence\n");
}
}
@@ -1027,7 +1027,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
int max_insns;
pc_start = tb->pc;
- dc->env = env;
+ dc->cpu = cpu;
dc->tb = tb;
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 37/41] target-microblaze: Replace DisasContext::env field with MicroBlazeCPU
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (35 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 36/41] target-lm32: Replace DisasContext::env field with LM32CPU Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 38/41] target-lm32: Move features field from CPULM32State to LM32CPU Andreas Färber
` (6 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Edgar E. Iglesias, Andreas Färber
This cleans up some mb_env_get_cpu() needed for cpu_abort().
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-microblaze/translate.c | 84 +++++++++++++++++++++----------------------
1 file changed, 40 insertions(+), 44 deletions(-)
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 4471f5a..611ed82 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -54,7 +54,7 @@ static TCGv env_iflags;
/* This is the state at translation time. */
typedef struct DisasContext {
- CPUMBState *env;
+ MicroBlazeCPU *cpu;
target_ulong pc;
/* Decoder. */
@@ -321,8 +321,8 @@ static void dec_pattern(DisasContext *dc)
int l1;
if ((dc->tb_flags & MSR_EE_FLAG)
- && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
- && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
+ && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
+ && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
}
@@ -364,7 +364,7 @@ static void dec_pattern(DisasContext *dc)
}
break;
default:
- cpu_abort(CPU(mb_env_get_cpu(dc->env)),
+ cpu_abort(CPU(dc->cpu),
"unsupported pattern insn opcode=%x\n", dc->opcode);
break;
}
@@ -438,8 +438,7 @@ static inline void msr_write(DisasContext *dc, TCGv v)
static void dec_msr(DisasContext *dc)
{
- MicroBlazeCPU *cpu = mb_env_get_cpu(dc->env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = CPU(dc->cpu);
TCGv t0, t1;
unsigned int sr, to, rn;
int mem_index = cpu_mmu_index(cs);
@@ -457,7 +456,7 @@ static void dec_msr(DisasContext *dc)
LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
dc->rd, dc->imm);
- if (!(dc->env->pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
+ if (!(dc->cpu->env.pvr.regs[2] & PVR2_USE_MSR_INSTR)) {
/* nop??? */
return;
}
@@ -536,7 +535,7 @@ static void dec_msr(DisasContext *dc)
tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUMBState, shr));
break;
default:
- cpu_abort(CPU(mb_env_get_cpu(dc->env)), "unknown mts reg %x\n", sr);
+ cpu_abort(CPU(dc->cpu), "unknown mts reg %x\n", sr);
break;
}
} else {
@@ -642,8 +641,8 @@ static void dec_mul(DisasContext *dc)
unsigned int subcode;
if ((dc->tb_flags & MSR_EE_FLAG)
- && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
- && !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
+ && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
+ && !(dc->cpu->env.pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
return;
@@ -661,7 +660,7 @@ static void dec_mul(DisasContext *dc)
/* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */
if (subcode >= 1 && subcode <= 3
- && !((dc->env->pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
+ && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_MUL64_MASK))) {
/* nop??? */
}
@@ -683,7 +682,7 @@ static void dec_mul(DisasContext *dc)
t_gen_mulu(d[0], cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
break;
default:
- cpu_abort(CPU(mb_env_get_cpu(dc->env)), "unknown MUL insn %x\n", subcode);
+ cpu_abort(CPU(dc->cpu), "unknown MUL insn %x\n", subcode);
break;
}
done:
@@ -699,8 +698,8 @@ static void dec_div(DisasContext *dc)
u = dc->imm & 2;
LOG_DIS("div\n");
- if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
- && !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
+ if ((dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
+ && !((dc->cpu->env.pvr.regs[0] & PVR0_USE_DIV_MASK))) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
}
@@ -721,8 +720,8 @@ static void dec_barrel(DisasContext *dc)
unsigned int s, t;
if ((dc->tb_flags & MSR_EE_FLAG)
- && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
- && !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
+ && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
+ && !(dc->cpu->env.pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
return;
@@ -751,8 +750,7 @@ static void dec_barrel(DisasContext *dc)
static void dec_bit(DisasContext *dc)
{
- MicroBlazeCPU *cpu = mb_env_get_cpu(dc->env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = CPU(dc->cpu);
TCGv t0, t1;
unsigned int op;
int mem_index = cpu_mmu_index(cs);
@@ -830,12 +828,12 @@ static void dec_bit(DisasContext *dc)
break;
case 0xe0:
if ((dc->tb_flags & MSR_EE_FLAG)
- && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
- && !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
+ && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
+ && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
}
- if (dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR) {
+ if (dc->cpu->env.pvr.regs[2] & PVR2_USE_PCMP_INSTR) {
gen_helper_clz(cpu_R[dc->rd], cpu_R[dc->ra]);
}
break;
@@ -878,8 +876,7 @@ static void dec_imm(DisasContext *dc)
static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
unsigned int size)
{
- MicroBlazeCPU *cpu = mb_env_get_cpu(dc->env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = CPU(dc->cpu);
int mem_index = cpu_mmu_index(cs);
if (size == 1) {
@@ -956,7 +953,7 @@ static inline void dec_byteswap(DisasContext *dc, TCGv dst, TCGv src, int size)
tcg_temp_free(t);
} else {
/* Ignore.
- cpu_abort(dc->env, "Invalid ldst byteswap size %d\n", size);
+ cpu_abort(CPU(dc->cpu), "Invalid ldst byteswap size %d\n", size);
*/
}
}
@@ -974,7 +971,7 @@ static void dec_load(DisasContext *dc)
}
if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
- && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
+ && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
return;
@@ -1032,7 +1029,7 @@ static void dec_load(DisasContext *dc)
}
break;
default:
- cpu_abort(CPU(mb_env_get_cpu(dc->env)), "Invalid reverse size\n");
+ cpu_abort(CPU(dc->cpu), "Invalid reverse size\n");
break;
}
}
@@ -1052,7 +1049,7 @@ static void dec_load(DisasContext *dc)
sync_jmpstate(dc);
/* Verify alignment if needed. */
- if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
+ if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
TCGv v = tcg_temp_new();
/*
@@ -1099,8 +1096,7 @@ static void dec_load(DisasContext *dc)
static void gen_store(DisasContext *dc, TCGv addr, TCGv val,
unsigned int size)
{
- MicroBlazeCPU *cpu = mb_env_get_cpu(dc->env);
- CPUState *cs = CPU(cpu);
+ CPUState *cs = CPU(dc->cpu);
int mem_index = cpu_mmu_index(cs);
if (size == 1)
@@ -1127,7 +1123,7 @@ static void dec_store(DisasContext *dc)
}
if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
- && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
+ && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
return;
@@ -1197,7 +1193,7 @@ static void dec_store(DisasContext *dc)
}
break;
default:
- cpu_abort(CPU(mb_env_get_cpu(dc->env)), "Invalid reverse size\n");
+ cpu_abort(CPU(dc->cpu), "Invalid reverse size\n");
break;
}
@@ -1221,7 +1217,7 @@ static void dec_store(DisasContext *dc)
}
/* Verify alignment if needed. */
- if ((dc->env->pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
+ if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc);
/* FIXME: if the alignment is wrong, we should restore the value
* in memory. One possible way to achieve this is to probe
@@ -1266,7 +1262,7 @@ static inline void eval_cc(DisasContext *dc, unsigned int cc,
tcg_gen_setcond_tl(TCG_COND_GT, d, a, b);
break;
default:
- cpu_abort(CPU(mb_env_get_cpu(dc->env)), "Unknown condition code %x.\n", cc);
+ cpu_abort(CPU(dc->cpu), "Unknown condition code %x.\n", cc);
break;
}
}
@@ -1317,7 +1313,7 @@ static void dec_bcc(DisasContext *dc)
static void dec_br(DisasContext *dc)
{
unsigned int dslot, link, abs, mbar;
- int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
+ int mem_index = cpu_mmu_index(CPU(dc->cpu));
dslot = dc->ir & (1 << 20);
abs = dc->ir & (1 << 19);
@@ -1449,7 +1445,7 @@ static inline void do_rte(DisasContext *dc)
static void dec_rts(DisasContext *dc)
{
unsigned int b_bit, i_bit, e_bit;
- int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
+ int mem_index = cpu_mmu_index(CPU(dc->cpu));
i_bit = dc->ir & (1 << 21);
b_bit = dc->ir & (1 << 22);
@@ -1496,7 +1492,7 @@ static int dec_check_fpuv2(DisasContext *dc)
{
int r;
- r = dc->env->pvr.regs[2] & PVR2_USE_FPU2_MASK;
+ r = dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU2_MASK;
if (!r && (dc->tb_flags & MSR_EE_FLAG)) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
@@ -1510,8 +1506,8 @@ static void dec_fpu(DisasContext *dc)
unsigned int fpu_insn;
if ((dc->tb_flags & MSR_EE_FLAG)
- && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
- && !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
+ && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
+ && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU_MASK))) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
return;
@@ -1613,7 +1609,7 @@ static void dec_fpu(DisasContext *dc)
static void dec_null(DisasContext *dc)
{
if ((dc->tb_flags & MSR_EE_FLAG)
- && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
+ && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
return;
@@ -1625,7 +1621,7 @@ static void dec_null(DisasContext *dc)
/* Insns connected to FSL or AXI stream attached devices. */
static void dec_stream(DisasContext *dc)
{
- int mem_index = cpu_mmu_index(CPU(mb_env_get_cpu(dc->env)));
+ int mem_index = cpu_mmu_index(CPU(dc->cpu));
TCGv_i32 t_id, t_ctrl;
int ctrl;
@@ -1701,8 +1697,8 @@ static inline void decode(DisasContext *dc, uint32_t ir)
dc->nr_nops = 0;
else {
if ((dc->tb_flags & MSR_EE_FLAG)
- && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
- && (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
+ && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
+ && (dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
return;
@@ -1711,7 +1707,7 @@ static inline void decode(DisasContext *dc, uint32_t ir)
LOG_DIS("nr_nops=%d\t", dc->nr_nops);
dc->nr_nops++;
if (dc->nr_nops > 4) {
- cpu_abort(CPU(mb_env_get_cpu(dc->env)), "fetching nop sequence\n");
+ cpu_abort(CPU(dc->cpu), "fetching nop sequence\n");
}
}
/* bit 2 seems to indicate insn type. */
@@ -1765,7 +1761,7 @@ gen_intermediate_code_internal(MicroBlazeCPU *cpu, TranslationBlock *tb,
int max_insns;
pc_start = tb->pc;
- dc->env = env;
+ dc->cpu = cpu;
dc->tb = tb;
org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 38/41] target-lm32: Move features field from CPULM32State to LM32CPU
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (36 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 37/41] target-microblaze: Replace DisasContext::env field with MicroBlazeCPU Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 39/41] cputlb: Change tlb_flush_page() argument to CPUState Andreas Färber
` (5 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Michael Walle, Andreas Färber
This simplifies the code after conversion to DisasContext::cpu.
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
target-lm32/cpu-qom.h | 3 +++
target-lm32/cpu.h | 2 --
target-lm32/helper.c | 2 +-
target-lm32/translate.c | 16 ++++++++--------
4 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/target-lm32/cpu-qom.h b/target-lm32/cpu-qom.h
index 723f604..16ef037 100644
--- a/target-lm32/cpu-qom.h
+++ b/target-lm32/cpu-qom.h
@@ -51,6 +51,7 @@ typedef struct LM32CPUClass {
/**
* LM32CPU:
* @env: #CPULM32State
+ * @features: Processor core features.
*
* A LatticeMico32 CPU.
*/
@@ -60,6 +61,8 @@ typedef struct LM32CPU {
/*< public >*/
CPULM32State env;
+
+ uint32_t features;
} LM32CPU;
static inline LM32CPU *lm32_env_get_cpu(CPULM32State *env)
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index 85c89e8..0ff8e7c 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -173,8 +173,6 @@ struct CPULM32State {
/* JTAG UART handle for callbacks */
DeviceState *juart_state;
- /* processor core features */
- uint32_t features;
uint32_t flags;
uint8_t num_bps;
uint8_t num_wps;
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index 8f2b9fd..68de4ee 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -218,7 +218,7 @@ LM32CPU *cpu_lm32_init(const char *cpu_model)
cpu = LM32_CPU(object_new(TYPE_LM32_CPU));
env = &cpu->env;
- env->features = def->features;
+ cpu->features = def->features;
env->num_bps = def->num_breakpoints;
env->num_wps = def->num_watchpoints;
env->cfg = cfg_by_def(def);
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 57b91c4..d4e8106 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -421,7 +421,7 @@ static void dec_divu(DisasContext *dc)
LOG_DIS("divu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
- if (!(dc->cpu->env.features & LM32_FEATURE_DIVIDE)) {
+ if (!(dc->cpu->features & LM32_FEATURE_DIVIDE)) {
cpu_abort(CPU(dc->cpu), "hardware divider is not available\n");
}
@@ -499,7 +499,7 @@ static void dec_modu(DisasContext *dc)
LOG_DIS("modu r%d, r%d, %d\n", dc->r2, dc->r0, dc->r1);
- if (!(dc->cpu->env.features & LM32_FEATURE_DIVIDE)) {
+ if (!(dc->cpu->features & LM32_FEATURE_DIVIDE)) {
cpu_abort(CPU(dc->cpu), "hardware divider is not available\n");
}
@@ -520,7 +520,7 @@ static void dec_mul(DisasContext *dc)
LOG_DIS("mul r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
}
- if (!(dc->cpu->env.features & LM32_FEATURE_MULTIPLY)) {
+ if (!(dc->cpu->features & LM32_FEATURE_MULTIPLY)) {
cpu_abort(CPU(dc->cpu), "hardware multiplier is not available\n");
}
@@ -671,7 +671,7 @@ static void dec_sextb(DisasContext *dc)
{
LOG_DIS("sextb r%d, r%d\n", dc->r2, dc->r0);
- if (!(dc->cpu->env.features & LM32_FEATURE_SIGN_EXTEND)) {
+ if (!(dc->cpu->features & LM32_FEATURE_SIGN_EXTEND)) {
cpu_abort(CPU(dc->cpu), "hardware sign extender is not available\n");
}
@@ -682,7 +682,7 @@ static void dec_sexth(DisasContext *dc)
{
LOG_DIS("sexth r%d, r%d\n", dc->r2, dc->r0);
- if (!(dc->cpu->env.features & LM32_FEATURE_SIGN_EXTEND)) {
+ if (!(dc->cpu->features & LM32_FEATURE_SIGN_EXTEND)) {
cpu_abort(CPU(dc->cpu), "hardware sign extender is not available\n");
}
@@ -709,7 +709,7 @@ static void dec_sl(DisasContext *dc)
LOG_DIS("sl r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
}
- if (!(dc->cpu->env.features & LM32_FEATURE_SHIFT)) {
+ if (!(dc->cpu->features & LM32_FEATURE_SHIFT)) {
cpu_abort(CPU(dc->cpu), "hardware shifter is not available\n");
}
@@ -731,7 +731,7 @@ static void dec_sr(DisasContext *dc)
LOG_DIS("sr r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
}
- if (!(dc->cpu->env.features & LM32_FEATURE_SHIFT)) {
+ if (!(dc->cpu->features & LM32_FEATURE_SHIFT)) {
if (dc->format == OP_FMT_RI) {
/* TODO: check r1 == 1 during runtime */
} else {
@@ -759,7 +759,7 @@ static void dec_sru(DisasContext *dc)
LOG_DIS("sru r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
}
- if (!(dc->cpu->env.features & LM32_FEATURE_SHIFT)) {
+ if (!(dc->cpu->features & LM32_FEATURE_SHIFT)) {
if (dc->format == OP_FMT_RI) {
/* TODO: check r1 == 1 during runtime */
} else {
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* [Qemu-devel] [RFC qom-cpu 39/41] cputlb: Change tlb_flush_page() argument to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (37 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 38/41] target-lm32: Move features field from CPULM32State to LM32CPU Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 12:50 ` Jia Liu
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 40/41] cputlb: Change tlb_flush() " Andreas Färber
` (4 subsequent siblings)
43 siblings, 1 reply; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Alexander Graf, Blue Swirl, Max Filippov,
open list:PowerPC, Paul Brook, Edgar E. Iglesias,
Andreas Färber, Aurelien Jarno, Richard Henderson
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cputlb.c | 4 +--
exec.c | 7 ++----
include/exec/exec-all.h | 4 +--
target-alpha/sys_helper.c | 2 +-
target-arm/helper.c | 8 ++++--
target-cris/mmu.c | 3 ++-
target-cris/op_helper.c | 12 ++++++---
target-i386/misc_helper.c | 4 ++-
target-i386/svm_helper.c | 3 ++-
target-microblaze/mmu.c | 3 ++-
target-mips/helper.c | 8 ++++--
target-openrisc/sys_helper.c | 4 +--
target-ppc/mmu_helper.c | 58 +++++++++++++++++++++++++-------------------
target-s390x/mem_helper.c | 7 +++---
target-s390x/misc_helper.c | 6 +++--
target-sh4/helper.c | 19 +++++++++------
target-sparc/ldst_helper.c | 7 ++++--
target-xtensa/op_helper.c | 11 ++++++---
18 files changed, 103 insertions(+), 67 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index 20a1efe..817180e 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -91,9 +91,9 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
}
}
-void tlb_flush_page(CPUArchState *env, target_ulong addr)
+void tlb_flush_page(CPUState *cpu, target_ulong addr)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUArchState *env = cpu->env_ptr;
int i;
int mmu_idx;
diff --git a/exec.c b/exec.c
index 16e3c4d..9210834 100644
--- a/exec.c
+++ b/exec.c
@@ -433,7 +433,6 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
int flags, CPUWatchpoint **watchpoint)
{
- CPUArchState *env = cpu->env_ptr;
vaddr len_mask = ~(len - 1);
CPUWatchpoint *wp;
@@ -457,7 +456,7 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
}
- tlb_flush_page(env, addr);
+ tlb_flush_page(cpu, addr);
if (watchpoint)
*watchpoint = wp;
@@ -484,11 +483,9 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
/* Remove a specific watchpoint by reference. */
void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
{
- CPUArchState *env = cpu->env_ptr;
-
QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
- tlb_flush_page(env, watchpoint->vaddr);
+ tlb_flush_page(cpu, watchpoint->vaddr);
g_free(watchpoint);
}
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 847ed84..550e58d 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -96,14 +96,14 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
int is_cpu_write_access);
#if !defined(CONFIG_USER_ONLY)
/* cputlb.c */
-void tlb_flush_page(CPUArchState *env, target_ulong addr);
+void tlb_flush_page(CPUState *cpu, target_ulong addr);
void tlb_flush(CPUArchState *env, int flush_global);
void tlb_set_page(CPUState *cpu, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size);
void tb_invalidate_phys_addr(hwaddr addr);
#else
-static inline void tlb_flush_page(CPUArchState *env, target_ulong addr)
+static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
{
}
diff --git a/target-alpha/sys_helper.c b/target-alpha/sys_helper.c
index 035810c..5f7d7dd 100644
--- a/target-alpha/sys_helper.c
+++ b/target-alpha/sys_helper.c
@@ -69,7 +69,7 @@ void helper_tbia(CPUAlphaState *env)
void helper_tbis(CPUAlphaState *env, uint64_t p)
{
- tlb_flush_page(env, p);
+ tlb_flush_page(CPU(alpha_env_get_cpu(env)), p);
}
void helper_tb_flush(CPUAlphaState *env)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 34407a1..4daf82e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -311,8 +311,10 @@ static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
+ ARMCPU *cpu = arm_env_get_cpu(env);
+
/* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
- tlb_flush_page(env, value & TARGET_PAGE_MASK);
+ tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
return 0;
}
@@ -327,8 +329,10 @@ static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
+ ARMCPU *cpu = arm_env_get_cpu(env);
+
/* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
- tlb_flush_page(env, value & TARGET_PAGE_MASK);
+ tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
return 0;
}
diff --git a/target-cris/mmu.c b/target-cris/mmu.c
index 512e28b..1c95a41 100644
--- a/target-cris/mmu.c
+++ b/target-cris/mmu.c
@@ -290,6 +290,7 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
{
+ CRISCPU *cpu = cris_env_get_cpu(env);
target_ulong vaddr;
unsigned int idx;
uint32_t lo, hi;
@@ -315,7 +316,7 @@ void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
vaddr = tlb_vpn << TARGET_PAGE_BITS;
D_LOG("flush pid=%x vaddr=%x\n",
pid, vaddr);
- tlb_flush_page(env, vaddr);
+ tlb_flush_page(CPU(cpu), vaddr);
}
}
}
diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
index d28bd61..bd9a583 100644
--- a/target-cris/op_helper.c
+++ b/target-cris/op_helper.c
@@ -98,8 +98,11 @@ void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
{
#if !defined(CONFIG_USER_ONLY)
- tlb_flush_page(env, env->pregs[PR_SPC]);
- tlb_flush_page(env, new_spc);
+ CRISCPU *cpu = cris_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
+
+ tlb_flush_page(cs, env->pregs[PR_SPC]);
+ tlb_flush_page(cs, new_spc);
#endif
}
@@ -114,6 +117,9 @@ void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
{
+#if !defined(CONFIG_USER_ONLY)
+ CRISCPU *cpu = cris_env_get_cpu(env);
+#endif
uint32_t srs;
srs = env->pregs[PR_SRS];
srs &= 3;
@@ -155,7 +161,7 @@ void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
vaddr, tlb_v, env->pc);
if (tlb_v) {
- tlb_flush_page(env, vaddr);
+ tlb_flush_page(CPU(cpu), vaddr);
}
}
}
diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c
index 4b7a142..64dceca 100644
--- a/target-i386/misc_helper.c
+++ b/target-i386/misc_helper.c
@@ -221,8 +221,10 @@ void helper_lmsw(CPUX86State *env, target_ulong t0)
void helper_invlpg(CPUX86State *env, target_ulong addr)
{
+ X86CPU *cpu = x86_env_get_cpu(env);
+
cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0);
- tlb_flush_page(env, addr);
+ tlb_flush_page(CPU(cpu), addr);
}
void helper_rdtsc(CPUX86State *env)
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index fbf8359..197269b 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -435,6 +435,7 @@ void helper_skinit(CPUX86State *env)
void helper_invlpga(CPUX86State *env, int aflag)
{
+ X86CPU *cpu = x86_env_get_cpu(env);
target_ulong addr;
cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPGA, 0);
@@ -447,7 +448,7 @@ void helper_invlpga(CPUX86State *env, int aflag)
/* XXX: could use the ASID to see if it is needed to do the
flush */
- tlb_flush_page(env, addr);
+ tlb_flush_page(CPU(cpu), addr);
}
void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
diff --git a/target-microblaze/mmu.c b/target-microblaze/mmu.c
index 9182934..5b768f2 100644
--- a/target-microblaze/mmu.c
+++ b/target-microblaze/mmu.c
@@ -34,6 +34,7 @@ static unsigned int tlb_decode_size(unsigned int f)
static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
{
+ CPUState *cs = CPU(mb_env_get_cpu(env));
struct microblaze_mmu *mmu = &env->mmu;
unsigned int tlb_size;
uint32_t tlb_tag, end, t;
@@ -47,7 +48,7 @@ static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
end = tlb_tag + tlb_size;
while (tlb_tag < end) {
- tlb_flush_page(env, tlb_tag);
+ tlb_flush_page(cs, tlb_tag);
tlb_tag += TARGET_PAGE_SIZE;
}
}
diff --git a/target-mips/helper.c b/target-mips/helper.c
index ca2f0e7..b28ae9b 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -653,6 +653,8 @@ void mips_cpu_do_interrupt(CPUState *cs)
#if !defined(CONFIG_USER_ONLY)
void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
{
+ MIPSCPU *cpu = mips_env_get_cpu(env);
+ CPUState *cs;
r4k_tlb_t *tlb;
target_ulong addr;
target_ulong end;
@@ -678,6 +680,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
/* 1k pages are not supported. */
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
if (tlb->V0) {
+ cs = CPU(cpu);
addr = tlb->VPN & ~mask;
#if defined(TARGET_MIPS64)
if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
@@ -686,11 +689,12 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
#endif
end = addr | (mask >> 1);
while (addr < end) {
- tlb_flush_page (env, addr);
+ tlb_flush_page(cs, addr);
addr += TARGET_PAGE_SIZE;
}
}
if (tlb->V1) {
+ cs = CPU(cpu);
addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
#if defined(TARGET_MIPS64)
if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
@@ -699,7 +703,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
#endif
end = addr | mask;
while (addr - 1 < end) {
- tlb_flush_page (env, addr);
+ tlb_flush_page(cs, addr);
addr += TARGET_PAGE_SIZE;
}
}
diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c
index cccbc0e..8f07f78 100644
--- a/target-openrisc/sys_helper.c
+++ b/target-openrisc/sys_helper.c
@@ -84,7 +84,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
case TO_SPR(1, 512) ... TO_SPR(1, 639): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
if (!(rb & 1)) {
- tlb_flush_page(env, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
+ tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
}
env->tlb->dtlb[0][idx].mr = rb;
break;
@@ -103,7 +103,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
case TO_SPR(2, 512) ... TO_SPR(2, 639): /* ITLBW0MR 0-127 */
idx = spr - TO_SPR(2, 512);
if (!(rb & 1)) {
- tlb_flush_page(env, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
+ tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
}
env->tlb->itlb[0][idx].mr = rb;
break;
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index f4dac00..cf652b7 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -252,6 +252,7 @@ static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env,
int is_code, int match_epn)
{
#if !defined(FLUSH_ALL_TLBS)
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
ppc6xx_tlb_t *tlb;
int way, nr;
@@ -263,7 +264,7 @@ static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env,
LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr,
env->nb_tlb, eaddr);
pte_invalidate(&tlb->pte0);
- tlb_flush_page(env, tlb->EPN);
+ tlb_flush_page(cs, tlb->EPN);
}
}
#else
@@ -657,6 +658,7 @@ static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env,
target_ulong eaddr, uint32_t pid)
{
#if !defined(FLUSH_ALL_TLBS)
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
ppcemb_tlb_t *tlb;
hwaddr raddr;
target_ulong page, end;
@@ -667,7 +669,7 @@ static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env,
if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
end = tlb->EPN + tlb->size;
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) {
- tlb_flush_page(env, page);
+ tlb_flush_page(cs, page);
}
tlb->prot &= ~PAGE_VALID;
break;
@@ -1727,6 +1729,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu,
target_ulong mask)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
target_ulong base, end, page;
base = BATu & ~0x0001FFFF;
@@ -1734,7 +1737,7 @@ static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu,
LOG_BATS("Flush BAT from " TARGET_FMT_lx " to " TARGET_FMT_lx " ("
TARGET_FMT_lx ")\n", base, end, mask);
for (page = base; page != end; page += TARGET_PAGE_SIZE) {
- tlb_flush_page(env, page);
+ tlb_flush_page(cs, page);
}
LOG_BATS("Flush done\n");
}
@@ -1941,6 +1944,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
{
#if !defined(FLUSH_ALL_TLBS)
PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ CPUState *cs;
addr &= TARGET_PAGE_MASK;
switch (env->mmu_model) {
@@ -1974,25 +1978,26 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
case POWERPC_MMU_601:
/* tlbie invalidate TLBs for all segments */
addr &= ~((target_ulong)-1ULL << 28);
+ cs = CPU(cpu);
/* XXX: this case should be optimized,
* giving a mask to tlb_flush_page
*/
- tlb_flush_page(env, addr | (0x0 << 28));
- tlb_flush_page(env, addr | (0x1 << 28));
- tlb_flush_page(env, addr | (0x2 << 28));
- tlb_flush_page(env, addr | (0x3 << 28));
- tlb_flush_page(env, addr | (0x4 << 28));
- tlb_flush_page(env, addr | (0x5 << 28));
- tlb_flush_page(env, addr | (0x6 << 28));
- tlb_flush_page(env, addr | (0x7 << 28));
- tlb_flush_page(env, addr | (0x8 << 28));
- tlb_flush_page(env, addr | (0x9 << 28));
- tlb_flush_page(env, addr | (0xA << 28));
- tlb_flush_page(env, addr | (0xB << 28));
- tlb_flush_page(env, addr | (0xC << 28));
- tlb_flush_page(env, addr | (0xD << 28));
- tlb_flush_page(env, addr | (0xE << 28));
- tlb_flush_page(env, addr | (0xF << 28));
+ tlb_flush_page(cs, addr | (0x0 << 28));
+ tlb_flush_page(cs, addr | (0x1 << 28));
+ tlb_flush_page(cs, addr | (0x2 << 28));
+ tlb_flush_page(cs, addr | (0x3 << 28));
+ tlb_flush_page(cs, addr | (0x4 << 28));
+ tlb_flush_page(cs, addr | (0x5 << 28));
+ tlb_flush_page(cs, addr | (0x6 << 28));
+ tlb_flush_page(cs, addr | (0x7 << 28));
+ tlb_flush_page(cs, addr | (0x8 << 28));
+ tlb_flush_page(cs, addr | (0x9 << 28));
+ tlb_flush_page(cs, addr | (0xA << 28));
+ tlb_flush_page(cs, addr | (0xB << 28));
+ tlb_flush_page(cs, addr | (0xC << 28));
+ tlb_flush_page(cs, addr | (0xD << 28));
+ tlb_flush_page(cs, addr | (0xE << 28));
+ tlb_flush_page(cs, addr | (0xF << 28));
break;
#if defined(TARGET_PPC64)
case POWERPC_MMU_64B:
@@ -2324,6 +2329,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
target_ulong val)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
+ CPUState *cs = CPU(cpu);
ppcemb_tlb_t *tlb;
target_ulong page, end;
@@ -2337,7 +2343,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
LOG_SWTLB("%s: invalidate old TLB %d start " TARGET_FMT_lx " end "
TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end);
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) {
- tlb_flush_page(env, page);
+ tlb_flush_page(cs, page);
}
}
tlb->size = booke_tlb_to_page_size((val >> PPC4XX_TLBHI_SIZE_SHIFT)
@@ -2347,7 +2353,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
* of the ppc or ppc64 one
*/
if ((val & PPC4XX_TLBHI_V) && tlb->size < TARGET_PAGE_SIZE) {
- cpu_abort(CPU(cpu), "TLB size " TARGET_FMT_lu " < %u "
+ cpu_abort(cs, "TLB size " TARGET_FMT_lu " < %u "
"are not supported (%d)\n",
tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
}
@@ -2356,7 +2362,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
tlb->prot |= PAGE_VALID;
if (val & PPC4XX_TLBHI_E) {
/* XXX: TO BE FIXED */
- cpu_abort(CPU(cpu),
+ cpu_abort(cs,
"Little-endian TLB entries are not supported by now\n");
}
} else {
@@ -2376,7 +2382,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
LOG_SWTLB("%s: invalidate TLB %d start " TARGET_FMT_lx " end "
TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end);
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) {
- tlb_flush_page(env, page);
+ tlb_flush_page(cs, page);
}
}
}
@@ -2665,7 +2671,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
}
if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) {
- tlb_flush_page(env, tlb->mas2 & MAS2_EPN_MASK);
+ tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK);
} else {
tlb_flush(env, 1);
}
@@ -2774,6 +2780,8 @@ static inline void booke206_invalidate_ea_tlb(CPUPPCState *env, int tlbn,
void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
if (address & 0x4) {
/* flush all entries */
if (address & 0x8) {
@@ -2793,7 +2801,7 @@ void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address)
} else {
/* flush TLB0 entries */
booke206_invalidate_ea_tlb(env, 0, address);
- tlb_flush_page(env, address & MAS2_EPN_MASK);
+ tlb_flush_page(CPU(cpu), address & MAS2_EPN_MASK);
}
}
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index cd84337..6bff6cc 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -1012,6 +1012,7 @@ uint32_t HELPER(mvcp)(CPUS390XState *env, uint64_t l, uint64_t a1, uint64_t a2)
/* invalidate pte */
void HELPER(ipte)(CPUS390XState *env, uint64_t pte_addr, uint64_t vaddr)
{
+ CPUState *cs = CPU(s390_env_get_cpu(env));
uint64_t page = vaddr & TARGET_PAGE_MASK;
uint64_t pte = 0;
@@ -1025,13 +1026,13 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pte_addr, uint64_t vaddr)
/* XXX we exploit the fact that Linux passes the exact virtual
address here - it's not obliged to! */
- tlb_flush_page(env, page);
+ tlb_flush_page(cs, page);
/* XXX 31-bit hack */
if (page & 0x80000000) {
- tlb_flush_page(env, page & ~0x80000000);
+ tlb_flush_page(cs, page & ~0x80000000);
} else {
- tlb_flush_page(env, page | 0x80000000);
+ tlb_flush_page(cs, page | 0x80000000);
}
}
diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
index 54e6d36..d638955 100644
--- a/target-s390x/misc_helper.c
+++ b/target-s390x/misc_helper.c
@@ -290,11 +290,13 @@ uint64_t HELPER(diag)(CPUS390XState *env, uint32_t num, uint64_t mem,
/* Set Prefix */
void HELPER(spx)(CPUS390XState *env, uint64_t a1)
{
+ CPUState *cs = CPU(s390_env_get_cpu(env));
uint32_t prefix = a1 & 0x7fffe000;
+
env->psa = prefix;
qemu_log("prefix: %#x\n", prefix);
- tlb_flush_page(env, 0);
- tlb_flush_page(env, TARGET_PAGE_SIZE);
+ tlb_flush_page(cs, 0);
+ tlb_flush_page(cs, TARGET_PAGE_SIZE);
}
static inline uint64_t clock_value(CPUS390XState *env)
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 7add92d..c56e543 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -304,7 +304,7 @@ static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
itlb = itlb_replacement(env);
ientry = &env->itlb[itlb];
if (ientry->v) {
- tlb_flush_page(env, ientry->vpn << 10);
+ tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10);
}
*ientry = env->utlb[utlb];
update_itlb_use(env, itlb);
@@ -535,7 +535,7 @@ void cpu_load_tlb(CPUSH4State * env)
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(env, address);
+ tlb_flush_page(CPU(cpu), address);
}
/* Take values into cpu status from registers. */
@@ -611,7 +611,7 @@ void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
if (entry->v) {
/* Overwriting valid entry in itlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(s, address);
+ tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
}
entry->asid = asid;
entry->vpn = vpn;
@@ -653,7 +653,7 @@ void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(s, address);
+ tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
}
entry->ppn = (mem_value & 0x1ffffc00) >> 10;
entry->v = (mem_value & 0x00000100) >> 8;
@@ -737,16 +737,19 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
}
}
- if (needs_tlb_flush)
- tlb_flush_page(s, vpn << 10);
+ if (needs_tlb_flush) {
+ tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10);
+ }
} else {
int index = (addr & 0x00003f00) >> 8;
tlb_t * entry = &s->utlb[index];
if (entry->v) {
+ CPUState *cs = CPU(sh_env_get_cpu(s));
+
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(s, address);
+ tlb_flush_page(cs, address);
}
entry->asid = asid;
entry->vpn = vpn;
@@ -797,7 +800,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
if (entry->v) {
/* Overwriting valid entry in utlb. */
target_ulong address = entry->vpn << 10;
- tlb_flush_page(s, address);
+ tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
}
entry->ppn = (mem_value & 0x1ffffc00) >> 10;
entry->v = (mem_value & 0x00000100) >> 8;
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index b222dff..44c54f1 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -141,6 +141,7 @@ static void replace_tlb_entry(SparcTLBEntry *tlb,
/* flush page range if translation is valid */
if (TTE_IS_VALID(tlb->tte)) {
+ CPUState *cs = CPU(sparc_env_get_cpu(env1));
mask = 0xffffffffffffe000ULL;
mask <<= 3 * ((tlb->tte >> 61) & 3);
@@ -149,7 +150,7 @@ static void replace_tlb_entry(SparcTLBEntry *tlb,
va = tlb->tag & mask;
for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
- tlb_flush_page(env1, va + offset);
+ tlb_flush_page(cs, va + offset);
}
}
@@ -715,6 +716,8 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
int size)
{
+ SPARCCPU *cpu = sparc_env_get_cpu(env);
+
helper_check_align(env, addr, size - 1);
switch (asi) {
case 2: /* SuperSparc MXCC registers and Leon3 cache control */
@@ -856,7 +859,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
DPRINTF_MMU("mmu flush level %d\n", mmulev);
switch (mmulev) {
case 0: /* flush page */
- tlb_flush_page(env, addr & 0xfffff000);
+ tlb_flush_page(CPU(cpu), addr & 0xfffff000);
break;
case 1: /* flush segment (256k) */
case 2: /* flush region (16M) */
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 5952ed8..5771841 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -679,7 +679,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
uint32_t wi;
xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
if (entry->variable && entry->asid) {
- tlb_flush_page(env, entry->vaddr);
+ tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr);
entry->asid = 0;
}
}
@@ -724,21 +724,24 @@ void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
{
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+ CPUState *cs;
xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
if (entry->variable) {
+ cs = CPU(cpu);
if (entry->asid) {
- tlb_flush_page(env, entry->vaddr);
+ tlb_flush_page(cs, entry->vaddr);
}
xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte);
- tlb_flush_page(env, entry->vaddr);
+ tlb_flush_page(cs, entry->vaddr);
} else {
qemu_log("%s %d, %d, %d trying to set immutable entry\n",
__func__, dtlb, wi, ei);
}
} else {
- tlb_flush_page(env, entry->vaddr);
+ tlb_flush_page(CPU(cpu), entry->vaddr);
if (xtensa_option_enabled(env->config,
XTENSA_OPTION_REGION_TRANSLATION)) {
entry->paddr = pte & REGION_PAGE_MASK;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 39/41] cputlb: Change tlb_flush_page() argument to CPUState
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 39/41] cputlb: Change tlb_flush_page() argument to CPUState Andreas Färber
@ 2013-09-04 12:50 ` Jia Liu
0 siblings, 0 replies; 68+ messages in thread
From: Jia Liu @ 2013-09-04 12:50 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, qemu-devel@nongnu.org, Alexander Graf, Blue Swirl,
Max Filippov, open list:PowerPC, Paul Brook, Edgar E. Iglesias,
Aurelien Jarno, Richard Henderson
On Wed, Sep 4, 2013 at 5:05 PM, Andreas Färber <afaerber@suse.de> wrote:
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
> cputlb.c | 4 +--
> exec.c | 7 ++----
> include/exec/exec-all.h | 4 +--
> target-alpha/sys_helper.c | 2 +-
> target-arm/helper.c | 8 ++++--
> target-cris/mmu.c | 3 ++-
> target-cris/op_helper.c | 12 ++++++---
> target-i386/misc_helper.c | 4 ++-
> target-i386/svm_helper.c | 3 ++-
> target-microblaze/mmu.c | 3 ++-
> target-mips/helper.c | 8 ++++--
> target-openrisc/sys_helper.c | 4 +--
> target-ppc/mmu_helper.c | 58 +++++++++++++++++++++++++-------------------
> target-s390x/mem_helper.c | 7 +++---
> target-s390x/misc_helper.c | 6 +++--
> target-sh4/helper.c | 19 +++++++++------
> target-sparc/ldst_helper.c | 7 ++++--
> target-xtensa/op_helper.c | 11 ++++++---
> 18 files changed, 103 insertions(+), 67 deletions(-)
>
> diff --git a/cputlb.c b/cputlb.c
> index 20a1efe..817180e 100644
> --- a/cputlb.c
> +++ b/cputlb.c
> @@ -91,9 +91,9 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
> }
> }
>
> -void tlb_flush_page(CPUArchState *env, target_ulong addr)
> +void tlb_flush_page(CPUState *cpu, target_ulong addr)
> {
> - CPUState *cpu = ENV_GET_CPU(env);
> + CPUArchState *env = cpu->env_ptr;
> int i;
> int mmu_idx;
>
> diff --git a/exec.c b/exec.c
> index 16e3c4d..9210834 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -433,7 +433,6 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
> int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
> int flags, CPUWatchpoint **watchpoint)
> {
> - CPUArchState *env = cpu->env_ptr;
> vaddr len_mask = ~(len - 1);
> CPUWatchpoint *wp;
>
> @@ -457,7 +456,7 @@ int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
> QTAILQ_INSERT_TAIL(&cpu->watchpoints, wp, entry);
> }
>
> - tlb_flush_page(env, addr);
> + tlb_flush_page(cpu, addr);
>
> if (watchpoint)
> *watchpoint = wp;
> @@ -484,11 +483,9 @@ int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
> /* Remove a specific watchpoint by reference. */
> void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
> {
> - CPUArchState *env = cpu->env_ptr;
> -
> QTAILQ_REMOVE(&cpu->watchpoints, watchpoint, entry);
>
> - tlb_flush_page(env, watchpoint->vaddr);
> + tlb_flush_page(cpu, watchpoint->vaddr);
>
> g_free(watchpoint);
> }
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index 847ed84..550e58d 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -96,14 +96,14 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
> int is_cpu_write_access);
> #if !defined(CONFIG_USER_ONLY)
> /* cputlb.c */
> -void tlb_flush_page(CPUArchState *env, target_ulong addr);
> +void tlb_flush_page(CPUState *cpu, target_ulong addr);
> void tlb_flush(CPUArchState *env, int flush_global);
> void tlb_set_page(CPUState *cpu, target_ulong vaddr,
> hwaddr paddr, int prot,
> int mmu_idx, target_ulong size);
> void tb_invalidate_phys_addr(hwaddr addr);
> #else
> -static inline void tlb_flush_page(CPUArchState *env, target_ulong addr)
> +static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
> {
> }
>
> diff --git a/target-alpha/sys_helper.c b/target-alpha/sys_helper.c
> index 035810c..5f7d7dd 100644
> --- a/target-alpha/sys_helper.c
> +++ b/target-alpha/sys_helper.c
> @@ -69,7 +69,7 @@ void helper_tbia(CPUAlphaState *env)
>
> void helper_tbis(CPUAlphaState *env, uint64_t p)
> {
> - tlb_flush_page(env, p);
> + tlb_flush_page(CPU(alpha_env_get_cpu(env)), p);
> }
>
> void helper_tb_flush(CPUAlphaState *env)
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 34407a1..4daf82e 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -311,8 +311,10 @@ static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
> static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
> - tlb_flush_page(env, value & TARGET_PAGE_MASK);
> + tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
> return 0;
> }
>
> @@ -327,8 +329,10 @@ static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
> static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
> - tlb_flush_page(env, value & TARGET_PAGE_MASK);
> + tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
> return 0;
> }
>
> diff --git a/target-cris/mmu.c b/target-cris/mmu.c
> index 512e28b..1c95a41 100644
> --- a/target-cris/mmu.c
> +++ b/target-cris/mmu.c
> @@ -290,6 +290,7 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res,
>
> void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
> {
> + CRISCPU *cpu = cris_env_get_cpu(env);
> target_ulong vaddr;
> unsigned int idx;
> uint32_t lo, hi;
> @@ -315,7 +316,7 @@ void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid)
> vaddr = tlb_vpn << TARGET_PAGE_BITS;
> D_LOG("flush pid=%x vaddr=%x\n",
> pid, vaddr);
> - tlb_flush_page(env, vaddr);
> + tlb_flush_page(CPU(cpu), vaddr);
> }
> }
> }
> diff --git a/target-cris/op_helper.c b/target-cris/op_helper.c
> index d28bd61..bd9a583 100644
> --- a/target-cris/op_helper.c
> +++ b/target-cris/op_helper.c
> @@ -98,8 +98,11 @@ void helper_tlb_flush_pid(CPUCRISState *env, uint32_t pid)
> void helper_spc_write(CPUCRISState *env, uint32_t new_spc)
> {
> #if !defined(CONFIG_USER_ONLY)
> - tlb_flush_page(env, env->pregs[PR_SPC]);
> - tlb_flush_page(env, new_spc);
> + CRISCPU *cpu = cris_env_get_cpu(env);
> + CPUState *cs = CPU(cpu);
> +
> + tlb_flush_page(cs, env->pregs[PR_SPC]);
> + tlb_flush_page(cs, new_spc);
> #endif
> }
>
> @@ -114,6 +117,9 @@ void helper_dump(uint32_t a0, uint32_t a1, uint32_t a2)
>
> void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
> {
> +#if !defined(CONFIG_USER_ONLY)
> + CRISCPU *cpu = cris_env_get_cpu(env);
> +#endif
> uint32_t srs;
> srs = env->pregs[PR_SRS];
> srs &= 3;
> @@ -155,7 +161,7 @@ void helper_movl_sreg_reg(CPUCRISState *env, uint32_t sreg, uint32_t reg)
> D_LOG("tlb flush vaddr=%x v=%d pc=%x\n",
> vaddr, tlb_v, env->pc);
> if (tlb_v) {
> - tlb_flush_page(env, vaddr);
> + tlb_flush_page(CPU(cpu), vaddr);
> }
> }
> }
> diff --git a/target-i386/misc_helper.c b/target-i386/misc_helper.c
> index 4b7a142..64dceca 100644
> --- a/target-i386/misc_helper.c
> +++ b/target-i386/misc_helper.c
> @@ -221,8 +221,10 @@ void helper_lmsw(CPUX86State *env, target_ulong t0)
>
> void helper_invlpg(CPUX86State *env, target_ulong addr)
> {
> + X86CPU *cpu = x86_env_get_cpu(env);
> +
> cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPG, 0);
> - tlb_flush_page(env, addr);
> + tlb_flush_page(CPU(cpu), addr);
> }
>
> void helper_rdtsc(CPUX86State *env)
> diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
> index fbf8359..197269b 100644
> --- a/target-i386/svm_helper.c
> +++ b/target-i386/svm_helper.c
> @@ -435,6 +435,7 @@ void helper_skinit(CPUX86State *env)
>
> void helper_invlpga(CPUX86State *env, int aflag)
> {
> + X86CPU *cpu = x86_env_get_cpu(env);
> target_ulong addr;
>
> cpu_svm_check_intercept_param(env, SVM_EXIT_INVLPGA, 0);
> @@ -447,7 +448,7 @@ void helper_invlpga(CPUX86State *env, int aflag)
>
> /* XXX: could use the ASID to see if it is needed to do the
> flush */
> - tlb_flush_page(env, addr);
> + tlb_flush_page(CPU(cpu), addr);
> }
>
> void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
> diff --git a/target-microblaze/mmu.c b/target-microblaze/mmu.c
> index 9182934..5b768f2 100644
> --- a/target-microblaze/mmu.c
> +++ b/target-microblaze/mmu.c
> @@ -34,6 +34,7 @@ static unsigned int tlb_decode_size(unsigned int f)
>
> static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
> {
> + CPUState *cs = CPU(mb_env_get_cpu(env));
> struct microblaze_mmu *mmu = &env->mmu;
> unsigned int tlb_size;
> uint32_t tlb_tag, end, t;
> @@ -47,7 +48,7 @@ static void mmu_flush_idx(CPUMBState *env, unsigned int idx)
> end = tlb_tag + tlb_size;
>
> while (tlb_tag < end) {
> - tlb_flush_page(env, tlb_tag);
> + tlb_flush_page(cs, tlb_tag);
> tlb_tag += TARGET_PAGE_SIZE;
> }
> }
> diff --git a/target-mips/helper.c b/target-mips/helper.c
> index ca2f0e7..b28ae9b 100644
> --- a/target-mips/helper.c
> +++ b/target-mips/helper.c
> @@ -653,6 +653,8 @@ void mips_cpu_do_interrupt(CPUState *cs)
> #if !defined(CONFIG_USER_ONLY)
> void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
> {
> + MIPSCPU *cpu = mips_env_get_cpu(env);
> + CPUState *cs;
> r4k_tlb_t *tlb;
> target_ulong addr;
> target_ulong end;
> @@ -678,6 +680,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
> /* 1k pages are not supported. */
> mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
> if (tlb->V0) {
> + cs = CPU(cpu);
> addr = tlb->VPN & ~mask;
> #if defined(TARGET_MIPS64)
> if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
> @@ -686,11 +689,12 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
> #endif
> end = addr | (mask >> 1);
> while (addr < end) {
> - tlb_flush_page (env, addr);
> + tlb_flush_page(cs, addr);
> addr += TARGET_PAGE_SIZE;
> }
> }
> if (tlb->V1) {
> + cs = CPU(cpu);
> addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
> #if defined(TARGET_MIPS64)
> if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
> @@ -699,7 +703,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
> #endif
> end = addr | mask;
> while (addr - 1 < end) {
> - tlb_flush_page (env, addr);
> + tlb_flush_page(cs, addr);
> addr += TARGET_PAGE_SIZE;
> }
> }
> diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c
> index cccbc0e..8f07f78 100644
> --- a/target-openrisc/sys_helper.c
> +++ b/target-openrisc/sys_helper.c
> @@ -84,7 +84,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
> case TO_SPR(1, 512) ... TO_SPR(1, 639): /* DTLBW0MR 0-127 */
> idx = spr - TO_SPR(1, 512);
> if (!(rb & 1)) {
> - tlb_flush_page(env, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
> + tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
> }
> env->tlb->dtlb[0][idx].mr = rb;
> break;
> @@ -103,7 +103,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
> case TO_SPR(2, 512) ... TO_SPR(2, 639): /* ITLBW0MR 0-127 */
> idx = spr - TO_SPR(2, 512);
> if (!(rb & 1)) {
> - tlb_flush_page(env, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
> + tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
> }
> env->tlb->itlb[0][idx].mr = rb;
> break;
> diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
> index f4dac00..cf652b7 100644
> --- a/target-ppc/mmu_helper.c
> +++ b/target-ppc/mmu_helper.c
> @@ -252,6 +252,7 @@ static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env,
> int is_code, int match_epn)
> {
> #if !defined(FLUSH_ALL_TLBS)
> + CPUState *cs = CPU(ppc_env_get_cpu(env));
> ppc6xx_tlb_t *tlb;
> int way, nr;
>
> @@ -263,7 +264,7 @@ static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env,
> LOG_SWTLB("TLB invalidate %d/%d " TARGET_FMT_lx "\n", nr,
> env->nb_tlb, eaddr);
> pte_invalidate(&tlb->pte0);
> - tlb_flush_page(env, tlb->EPN);
> + tlb_flush_page(cs, tlb->EPN);
> }
> }
> #else
> @@ -657,6 +658,7 @@ static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env,
> target_ulong eaddr, uint32_t pid)
> {
> #if !defined(FLUSH_ALL_TLBS)
> + CPUState *cs = CPU(ppc_env_get_cpu(env));
> ppcemb_tlb_t *tlb;
> hwaddr raddr;
> target_ulong page, end;
> @@ -667,7 +669,7 @@ static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env,
> if (ppcemb_tlb_check(env, tlb, &raddr, eaddr, pid, 0, i) == 0) {
> end = tlb->EPN + tlb->size;
> for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) {
> - tlb_flush_page(env, page);
> + tlb_flush_page(cs, page);
> }
> tlb->prot &= ~PAGE_VALID;
> break;
> @@ -1727,6 +1729,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
> static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu,
> target_ulong mask)
> {
> + CPUState *cs = CPU(ppc_env_get_cpu(env));
> target_ulong base, end, page;
>
> base = BATu & ~0x0001FFFF;
> @@ -1734,7 +1737,7 @@ static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu,
> LOG_BATS("Flush BAT from " TARGET_FMT_lx " to " TARGET_FMT_lx " ("
> TARGET_FMT_lx ")\n", base, end, mask);
> for (page = base; page != end; page += TARGET_PAGE_SIZE) {
> - tlb_flush_page(env, page);
> + tlb_flush_page(cs, page);
> }
> LOG_BATS("Flush done\n");
> }
> @@ -1941,6 +1944,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
> {
> #if !defined(FLUSH_ALL_TLBS)
> PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + CPUState *cs;
>
> addr &= TARGET_PAGE_MASK;
> switch (env->mmu_model) {
> @@ -1974,25 +1978,26 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
> case POWERPC_MMU_601:
> /* tlbie invalidate TLBs for all segments */
> addr &= ~((target_ulong)-1ULL << 28);
> + cs = CPU(cpu);
> /* XXX: this case should be optimized,
> * giving a mask to tlb_flush_page
> */
> - tlb_flush_page(env, addr | (0x0 << 28));
> - tlb_flush_page(env, addr | (0x1 << 28));
> - tlb_flush_page(env, addr | (0x2 << 28));
> - tlb_flush_page(env, addr | (0x3 << 28));
> - tlb_flush_page(env, addr | (0x4 << 28));
> - tlb_flush_page(env, addr | (0x5 << 28));
> - tlb_flush_page(env, addr | (0x6 << 28));
> - tlb_flush_page(env, addr | (0x7 << 28));
> - tlb_flush_page(env, addr | (0x8 << 28));
> - tlb_flush_page(env, addr | (0x9 << 28));
> - tlb_flush_page(env, addr | (0xA << 28));
> - tlb_flush_page(env, addr | (0xB << 28));
> - tlb_flush_page(env, addr | (0xC << 28));
> - tlb_flush_page(env, addr | (0xD << 28));
> - tlb_flush_page(env, addr | (0xE << 28));
> - tlb_flush_page(env, addr | (0xF << 28));
> + tlb_flush_page(cs, addr | (0x0 << 28));
> + tlb_flush_page(cs, addr | (0x1 << 28));
> + tlb_flush_page(cs, addr | (0x2 << 28));
> + tlb_flush_page(cs, addr | (0x3 << 28));
> + tlb_flush_page(cs, addr | (0x4 << 28));
> + tlb_flush_page(cs, addr | (0x5 << 28));
> + tlb_flush_page(cs, addr | (0x6 << 28));
> + tlb_flush_page(cs, addr | (0x7 << 28));
> + tlb_flush_page(cs, addr | (0x8 << 28));
> + tlb_flush_page(cs, addr | (0x9 << 28));
> + tlb_flush_page(cs, addr | (0xA << 28));
> + tlb_flush_page(cs, addr | (0xB << 28));
> + tlb_flush_page(cs, addr | (0xC << 28));
> + tlb_flush_page(cs, addr | (0xD << 28));
> + tlb_flush_page(cs, addr | (0xE << 28));
> + tlb_flush_page(cs, addr | (0xF << 28));
> break;
> #if defined(TARGET_PPC64)
> case POWERPC_MMU_64B:
> @@ -2324,6 +2329,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
> target_ulong val)
> {
> PowerPCCPU *cpu = ppc_env_get_cpu(env);
> + CPUState *cs = CPU(cpu);
> ppcemb_tlb_t *tlb;
> target_ulong page, end;
>
> @@ -2337,7 +2343,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
> LOG_SWTLB("%s: invalidate old TLB %d start " TARGET_FMT_lx " end "
> TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end);
> for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) {
> - tlb_flush_page(env, page);
> + tlb_flush_page(cs, page);
> }
> }
> tlb->size = booke_tlb_to_page_size((val >> PPC4XX_TLBHI_SIZE_SHIFT)
> @@ -2347,7 +2353,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
> * of the ppc or ppc64 one
> */
> if ((val & PPC4XX_TLBHI_V) && tlb->size < TARGET_PAGE_SIZE) {
> - cpu_abort(CPU(cpu), "TLB size " TARGET_FMT_lu " < %u "
> + cpu_abort(cs, "TLB size " TARGET_FMT_lu " < %u "
> "are not supported (%d)\n",
> tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
> }
> @@ -2356,7 +2362,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
> tlb->prot |= PAGE_VALID;
> if (val & PPC4XX_TLBHI_E) {
> /* XXX: TO BE FIXED */
> - cpu_abort(CPU(cpu),
> + cpu_abort(cs,
> "Little-endian TLB entries are not supported by now\n");
> }
> } else {
> @@ -2376,7 +2382,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry,
> LOG_SWTLB("%s: invalidate TLB %d start " TARGET_FMT_lx " end "
> TARGET_FMT_lx "\n", __func__, (int)entry, tlb->EPN, end);
> for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE) {
> - tlb_flush_page(env, page);
> + tlb_flush_page(cs, page);
> }
> }
> }
> @@ -2665,7 +2671,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
> }
>
> if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) {
> - tlb_flush_page(env, tlb->mas2 & MAS2_EPN_MASK);
> + tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK);
> } else {
> tlb_flush(env, 1);
> }
> @@ -2774,6 +2780,8 @@ static inline void booke206_invalidate_ea_tlb(CPUPPCState *env, int tlbn,
>
> void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +
> if (address & 0x4) {
> /* flush all entries */
> if (address & 0x8) {
> @@ -2793,7 +2801,7 @@ void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address)
> } else {
> /* flush TLB0 entries */
> booke206_invalidate_ea_tlb(env, 0, address);
> - tlb_flush_page(env, address & MAS2_EPN_MASK);
> + tlb_flush_page(CPU(cpu), address & MAS2_EPN_MASK);
> }
> }
>
> diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
> index cd84337..6bff6cc 100644
> --- a/target-s390x/mem_helper.c
> +++ b/target-s390x/mem_helper.c
> @@ -1012,6 +1012,7 @@ uint32_t HELPER(mvcp)(CPUS390XState *env, uint64_t l, uint64_t a1, uint64_t a2)
> /* invalidate pte */
> void HELPER(ipte)(CPUS390XState *env, uint64_t pte_addr, uint64_t vaddr)
> {
> + CPUState *cs = CPU(s390_env_get_cpu(env));
> uint64_t page = vaddr & TARGET_PAGE_MASK;
> uint64_t pte = 0;
>
> @@ -1025,13 +1026,13 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pte_addr, uint64_t vaddr)
>
> /* XXX we exploit the fact that Linux passes the exact virtual
> address here - it's not obliged to! */
> - tlb_flush_page(env, page);
> + tlb_flush_page(cs, page);
>
> /* XXX 31-bit hack */
> if (page & 0x80000000) {
> - tlb_flush_page(env, page & ~0x80000000);
> + tlb_flush_page(cs, page & ~0x80000000);
> } else {
> - tlb_flush_page(env, page | 0x80000000);
> + tlb_flush_page(cs, page | 0x80000000);
> }
> }
>
> diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
> index 54e6d36..d638955 100644
> --- a/target-s390x/misc_helper.c
> +++ b/target-s390x/misc_helper.c
> @@ -290,11 +290,13 @@ uint64_t HELPER(diag)(CPUS390XState *env, uint32_t num, uint64_t mem,
> /* Set Prefix */
> void HELPER(spx)(CPUS390XState *env, uint64_t a1)
> {
> + CPUState *cs = CPU(s390_env_get_cpu(env));
> uint32_t prefix = a1 & 0x7fffe000;
> +
> env->psa = prefix;
> qemu_log("prefix: %#x\n", prefix);
> - tlb_flush_page(env, 0);
> - tlb_flush_page(env, TARGET_PAGE_SIZE);
> + tlb_flush_page(cs, 0);
> + tlb_flush_page(cs, TARGET_PAGE_SIZE);
> }
>
> static inline uint64_t clock_value(CPUS390XState *env)
> diff --git a/target-sh4/helper.c b/target-sh4/helper.c
> index 7add92d..c56e543 100644
> --- a/target-sh4/helper.c
> +++ b/target-sh4/helper.c
> @@ -304,7 +304,7 @@ static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
> itlb = itlb_replacement(env);
> ientry = &env->itlb[itlb];
> if (ientry->v) {
> - tlb_flush_page(env, ientry->vpn << 10);
> + tlb_flush_page(CPU(sh_env_get_cpu(env)), ientry->vpn << 10);
> }
> *ientry = env->utlb[utlb];
> update_itlb_use(env, itlb);
> @@ -535,7 +535,7 @@ void cpu_load_tlb(CPUSH4State * env)
> if (entry->v) {
> /* Overwriting valid entry in utlb. */
> target_ulong address = entry->vpn << 10;
> - tlb_flush_page(env, address);
> + tlb_flush_page(CPU(cpu), address);
> }
>
> /* Take values into cpu status from registers. */
> @@ -611,7 +611,7 @@ void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, hwaddr addr,
> if (entry->v) {
> /* Overwriting valid entry in itlb. */
> target_ulong address = entry->vpn << 10;
> - tlb_flush_page(s, address);
> + tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
> }
> entry->asid = asid;
> entry->vpn = vpn;
> @@ -653,7 +653,7 @@ void cpu_sh4_write_mmaped_itlb_data(CPUSH4State *s, hwaddr addr,
> if (entry->v) {
> /* Overwriting valid entry in utlb. */
> target_ulong address = entry->vpn << 10;
> - tlb_flush_page(s, address);
> + tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
> }
> entry->ppn = (mem_value & 0x1ffffc00) >> 10;
> entry->v = (mem_value & 0x00000100) >> 8;
> @@ -737,16 +737,19 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
> }
> }
>
> - if (needs_tlb_flush)
> - tlb_flush_page(s, vpn << 10);
> + if (needs_tlb_flush) {
> + tlb_flush_page(CPU(sh_env_get_cpu(s)), vpn << 10);
> + }
>
> } else {
> int index = (addr & 0x00003f00) >> 8;
> tlb_t * entry = &s->utlb[index];
> if (entry->v) {
> + CPUState *cs = CPU(sh_env_get_cpu(s));
> +
> /* Overwriting valid entry in utlb. */
> target_ulong address = entry->vpn << 10;
> - tlb_flush_page(s, address);
> + tlb_flush_page(cs, address);
> }
> entry->asid = asid;
> entry->vpn = vpn;
> @@ -797,7 +800,7 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
> if (entry->v) {
> /* Overwriting valid entry in utlb. */
> target_ulong address = entry->vpn << 10;
> - tlb_flush_page(s, address);
> + tlb_flush_page(CPU(sh_env_get_cpu(s)), address);
> }
> entry->ppn = (mem_value & 0x1ffffc00) >> 10;
> entry->v = (mem_value & 0x00000100) >> 8;
> diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
> index b222dff..44c54f1 100644
> --- a/target-sparc/ldst_helper.c
> +++ b/target-sparc/ldst_helper.c
> @@ -141,6 +141,7 @@ static void replace_tlb_entry(SparcTLBEntry *tlb,
>
> /* flush page range if translation is valid */
> if (TTE_IS_VALID(tlb->tte)) {
> + CPUState *cs = CPU(sparc_env_get_cpu(env1));
>
> mask = 0xffffffffffffe000ULL;
> mask <<= 3 * ((tlb->tte >> 61) & 3);
> @@ -149,7 +150,7 @@ static void replace_tlb_entry(SparcTLBEntry *tlb,
> va = tlb->tag & mask;
>
> for (offset = 0; offset < size; offset += TARGET_PAGE_SIZE) {
> - tlb_flush_page(env1, va + offset);
> + tlb_flush_page(cs, va + offset);
> }
> }
>
> @@ -715,6 +716,8 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
> void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
> int size)
> {
> + SPARCCPU *cpu = sparc_env_get_cpu(env);
> +
> helper_check_align(env, addr, size - 1);
> switch (asi) {
> case 2: /* SuperSparc MXCC registers and Leon3 cache control */
> @@ -856,7 +859,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
> DPRINTF_MMU("mmu flush level %d\n", mmulev);
> switch (mmulev) {
> case 0: /* flush page */
> - tlb_flush_page(env, addr & 0xfffff000);
> + tlb_flush_page(CPU(cpu), addr & 0xfffff000);
> break;
> case 1: /* flush segment (256k) */
> case 2: /* flush region (16M) */
> diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
> index 5952ed8..5771841 100644
> --- a/target-xtensa/op_helper.c
> +++ b/target-xtensa/op_helper.c
> @@ -679,7 +679,7 @@ void HELPER(itlb)(CPUXtensaState *env, uint32_t v, uint32_t dtlb)
> uint32_t wi;
> xtensa_tlb_entry *entry = get_tlb_entry(env, v, dtlb, &wi);
> if (entry->variable && entry->asid) {
> - tlb_flush_page(env, entry->vaddr);
> + tlb_flush_page(CPU(xtensa_env_get_cpu(env)), entry->vaddr);
> entry->asid = 0;
> }
> }
> @@ -724,21 +724,24 @@ void xtensa_tlb_set_entry_mmu(const CPUXtensaState *env,
> void xtensa_tlb_set_entry(CPUXtensaState *env, bool dtlb,
> unsigned wi, unsigned ei, uint32_t vpn, uint32_t pte)
> {
> + XtensaCPU *cpu = xtensa_env_get_cpu(env);
> + CPUState *cs;
> xtensa_tlb_entry *entry = xtensa_tlb_get_entry(env, dtlb, wi, ei);
>
> if (xtensa_option_enabled(env->config, XTENSA_OPTION_MMU)) {
> if (entry->variable) {
> + cs = CPU(cpu);
> if (entry->asid) {
> - tlb_flush_page(env, entry->vaddr);
> + tlb_flush_page(cs, entry->vaddr);
> }
> xtensa_tlb_set_entry_mmu(env, entry, dtlb, wi, ei, vpn, pte);
> - tlb_flush_page(env, entry->vaddr);
> + tlb_flush_page(cs, entry->vaddr);
> } else {
> qemu_log("%s %d, %d, %d trying to set immutable entry\n",
> __func__, dtlb, wi, ei);
> }
> } else {
> - tlb_flush_page(env, entry->vaddr);
> + tlb_flush_page(CPU(cpu), entry->vaddr);
> if (xtensa_option_enabled(env->config,
> XTENSA_OPTION_REGION_TRANSLATION)) {
> entry->paddr = pte & REGION_PAGE_MASK;
target-openrisc: Tested-by: Jia Liu <proljc@gmail.com>
> --
> 1.8.1.4
>
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [RFC qom-cpu 40/41] cputlb: Change tlb_flush() argument to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (38 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 39/41] cputlb: Change tlb_flush_page() argument to CPUState Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-04 12:50 ` Jia Liu
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 41/41] user-exec: Change exception_action() " Andreas Färber
` (3 subsequent siblings)
43 siblings, 1 reply; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Jia Liu, Anthony Green, Alexander Graf, Blue Swirl,
Max Filippov, Michael Walle, open list:PowerPC, Paul Brook,
Edgar E. Iglesias, Guan Xuetao, Andreas Färber,
Aurelien Jarno, Richard Henderson
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
cputlb.c | 6 +++---
exec.c | 4 +---
hw/sh4/sh7750.c | 2 +-
include/exec/exec-all.h | 4 ++--
target-alpha/cpu.c | 2 +-
target-alpha/sys_helper.c | 2 +-
target-arm/cpu.c | 2 +-
target-arm/helper.c | 28 +++++++++++++++++-------
target-cris/cpu.c | 2 +-
target-i386/cpu.c | 2 +-
target-i386/helper.c | 17 ++++++++++-----
target-i386/machine.c | 2 +-
target-i386/svm_helper.c | 2 +-
target-lm32/cpu.c | 2 +-
target-m68k/cpu.c | 2 +-
target-microblaze/cpu.c | 2 +-
target-microblaze/mmu.c | 2 +-
target-mips/cpu.c | 2 +-
target-mips/machine.c | 3 ++-
target-mips/op_helper.c | 4 +++-
target-moxie/cpu.c | 2 +-
target-openrisc/cpu.c | 2 +-
target-openrisc/interrupt.c | 2 +-
target-openrisc/interrupt_helper.c | 2 +-
target-openrisc/sys_helper.c | 2 +-
target-ppc/excp_helper.c | 4 ++--
target-ppc/helper_regs.h | 2 +-
target-ppc/misc_helper.c | 4 +++-
target-ppc/mmu-hash64.c | 6 ++++--
target-ppc/mmu_helper.c | 44 ++++++++++++++++++++++++--------------
target-ppc/translate_init.c | 2 +-
target-s390x/cpu.c | 5 ++---
target-s390x/mem_helper.c | 13 +++++++----
target-sh4/cpu.c | 2 +-
target-sh4/helper.c | 2 +-
target-sparc/cpu.c | 2 +-
target-sparc/ldst_helper.c | 16 ++++++++------
target-sparc/machine.c | 3 ++-
target-unicore32/cpu.c | 2 +-
target-unicore32/helper.c | 4 +++-
target-xtensa/op_helper.c | 4 +++-
41 files changed, 132 insertions(+), 85 deletions(-)
diff --git a/cputlb.c b/cputlb.c
index 817180e..bfa7417 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -52,9 +52,9 @@ static const CPUTLBEntry s_cputlb_empty_entry = {
* entries from the TLB at any time, so flushing more entries than
* required is only an efficiency issue, not a correctness issue.
*/
-void tlb_flush(CPUArchState *env, int flush_global)
+void tlb_flush(CPUState *cpu, int flush_global)
{
- CPUState *cpu = ENV_GET_CPU(env);
+ CPUArchState *env = cpu->env_ptr;
int i;
#if defined(DEBUG_TLB)
@@ -107,7 +107,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr)
VADDR_PRIx "/%" VADDR_PRIx ")\n",
cpu->tlb_flush_addr, cpu->tlb_flush_mask);
#endif
- tlb_flush(env, 1);
+ tlb_flush(cpu, 1);
return;
}
/* must reset current TB so that interrupts cannot modify the
diff --git a/exec.c b/exec.c
index 9210834..8e514e8 100644
--- a/exec.c
+++ b/exec.c
@@ -1720,9 +1720,7 @@ static void tcg_commit(MemoryListener *listener)
reset the modified entries */
/* XXX: slow ! */
CPU_FOREACH(cpu) {
- CPUArchState *env = cpu->env_ptr;
-
- tlb_flush(env, 1);
+ tlb_flush(cpu, 1);
}
}
diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c
index 1439ba4..4a39357 100644
--- a/hw/sh4/sh7750.c
+++ b/hw/sh4/sh7750.c
@@ -416,7 +416,7 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr,
case SH7750_PTEH_A7:
/* If asid changes, clear all registered tlb entries. */
if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) {
- tlb_flush(&s->cpu->env, 1);
+ tlb_flush(CPU(s->cpu), 1);
}
s->cpu->env.pteh = mem_value;
return;
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 550e58d..f2d1c6c 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -97,7 +97,7 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
#if !defined(CONFIG_USER_ONLY)
/* cputlb.c */
void tlb_flush_page(CPUState *cpu, target_ulong addr);
-void tlb_flush(CPUArchState *env, int flush_global);
+void tlb_flush(CPUState *cpu, int flush_global);
void tlb_set_page(CPUState *cpu, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size);
@@ -107,7 +107,7 @@ static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
{
}
-static inline void tlb_flush(CPUArchState *env, int flush_global)
+static inline void tlb_flush(CPUState *cpu, int flush_global)
{
}
#endif
diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
index 9931f9f..d839d53 100644
--- a/target-alpha/cpu.c
+++ b/target-alpha/cpu.c
@@ -294,7 +294,7 @@ static void alpha_cpu_initfn(Object *obj)
cs->env_ptr = env;
cpu_exec_init(env);
- tlb_flush(env, 1);
+ tlb_flush(cs, 1);
alpha_translate_init();
diff --git a/target-alpha/sys_helper.c b/target-alpha/sys_helper.c
index 5f7d7dd..187ccf7 100644
--- a/target-alpha/sys_helper.c
+++ b/target-alpha/sys_helper.c
@@ -64,7 +64,7 @@ void helper_call_pal(CPUAlphaState *env, uint64_t pc, uint64_t entry_ofs)
void helper_tbia(CPUAlphaState *env)
{
- tlb_flush(env, 1);
+ tlb_flush(CPU(alpha_env_get_cpu(env)), 1);
}
void helper_tbis(CPUAlphaState *env, uint64_t p)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index f9f6930..2a0e891 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -163,7 +163,7 @@ static void arm_cpu_reset(CPUState *s)
&env->vfp.fp_status);
set_float_detect_tininess(float_tininess_before_rounding,
&env->vfp.standard_fp_status);
- tlb_flush(env, 1);
+ tlb_flush(s, 1);
/* Reset is a state change for some CPUARMState fields which we
* bake assumptions about into translated code, so we need to
* tb_flush().
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4daf82e..7c87ffa 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -270,18 +270,22 @@ void init_cpreg_list(ARMCPU *cpu)
static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
+ ARMCPU *cpu = arm_env_get_cpu(env);
+
env->cp15.c3 = value;
- tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
+ tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
return 0;
}
static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
+ ARMCPU *cpu = arm_env_get_cpu(env);
+
if (env->cp15.c13_fcse != value) {
/* Unlike real hardware the qemu TLB uses virtual addresses,
* not modified virtual addresses, so this causes a TLB flush.
*/
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
env->cp15.c13_fcse = value;
}
return 0;
@@ -289,12 +293,14 @@ static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
+ ARMCPU *cpu = arm_env_get_cpu(env);
+
if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
/* For VMSA (when not using the LPAE long descriptor page table
* format) this register includes the ASID, so do a TLB flush.
* For PMSA it is purely a process ID and no action is needed.
*/
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
env->cp15.c13_context = value;
return 0;
@@ -303,8 +309,10 @@ static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
+ ARMCPU *cpu = arm_env_get_cpu(env);
+
/* Invalidate all (TLBIALL) */
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
return 0;
}
@@ -321,8 +329,10 @@ static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
+ ARMCPU *cpu = arm_env_get_cpu(env);
+
/* Invalidate by ASID (TLBIASID) */
- tlb_flush(env, value == 0);
+ tlb_flush(CPU(cpu), value == 0);
return 0;
}
@@ -1178,11 +1188,13 @@ static int vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
+ ARMCPU *cpu = arm_env_get_cpu(env);
+
if (arm_feature(env, ARM_FEATURE_LPAE)) {
/* With LPAE the TTBCR could result in a change of ASID
* via the TTBCR.A1 bit, so do a TLB flush.
*/
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
return vmsa_ttbcr_raw_write(env, ri, value);
}
@@ -1444,7 +1456,7 @@ static int ttbr064_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
/* Writes to the 64 bit format TTBRs may change the ASID */
- tlb_flush(env, 1);
+ tlb_flush(CPU(arm_env_get_cpu(env)), 1);
return ttbr064_raw_write(env, ri, value);
}
@@ -1508,7 +1520,7 @@ static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
env->cp15.c1_sys = value;
/* ??? Lots of these bits are not implemented. */
/* This may enable/disable the MMU, so do a TLB flush. */
- tlb_flush(env, 1);
+ tlb_flush(CPU(arm_env_get_cpu(env)), 1);
return 0;
}
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index b229a10..b7dbd08 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -71,7 +71,7 @@ static void cris_cpu_reset(CPUState *s)
vr = env->pregs[PR_VR];
memset(env, 0, offsetof(CPUCRISState, load_info));
env->pregs[PR_VR] = vr;
- tlb_flush(env, 1);
+ tlb_flush(s, 1);
#if defined(CONFIG_USER_ONLY)
/* start in user mode with interrupts enabled. */
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 944c3d7..b08c367 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2330,7 +2330,7 @@ static void x86_cpu_reset(CPUState *s)
memset(env, 0, offsetof(CPUX86State, pat));
- tlb_flush(env, 1);
+ tlb_flush(s, 1);
env->old_exception = -1;
diff --git a/target-i386/helper.c b/target-i386/helper.c
index e0df092..ac21cc4 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -385,22 +385,25 @@ void x86_cpu_set_a20(X86CPU *cpu, int a20_state)
a20_state = (a20_state != 0);
if (a20_state != ((env->a20_mask >> 20) & 1)) {
+ CPUState *cs = CPU(cpu);
+
#if defined(DEBUG_MMU)
printf("A20 update: a20=%d\n", a20_state);
#endif
/* if the cpu is currently executing code, we must unlink it and
all the potentially executing TB */
- cpu_interrupt(CPU(cpu), CPU_INTERRUPT_EXITTB);
+ cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
/* when a20 is changed, all the MMU mappings are invalid, so
we must flush everything */
- tlb_flush(env, 1);
+ tlb_flush(cs, 1);
env->a20_mask = ~(1 << 20) | (a20_state << 20);
}
}
void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
{
+ X86CPU *cpu = x86_env_get_cpu(env);
int pe_state;
#if defined(DEBUG_MMU)
@@ -408,7 +411,7 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
#endif
if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
(env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
#ifdef TARGET_X86_64
@@ -444,24 +447,28 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
the PDPT */
void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
{
+ X86CPU *cpu = x86_env_get_cpu(env);
+
env->cr[3] = new_cr3;
if (env->cr[0] & CR0_PG_MASK) {
#if defined(DEBUG_MMU)
printf("CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
#endif
- tlb_flush(env, 0);
+ tlb_flush(CPU(cpu), 0);
}
}
void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
{
+ X86CPU *cpu = x86_env_get_cpu(env);
+
#if defined(DEBUG_MMU)
printf("CR4 update: CR4=%08x\n", (uint32_t)env->cr[4]);
#endif
if ((new_cr4 ^ env->cr[4]) &
(CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK |
CR4_SMEP_MASK | CR4_SMAP_MASK)) {
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
/* SSE handling */
if (!(env->features[FEAT_1_EDX] & CPUID_SSE)) {
diff --git a/target-i386/machine.c b/target-i386/machine.c
index 54dd2ab..371c126 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -310,7 +310,7 @@ static int cpu_post_load(void *opaque, int version_id)
for (i = 0; i < DR7_MAX_BP; i++) {
hw_breakpoint_insert(env, i);
}
- tlb_flush(env, 1);
+ tlb_flush(cs, 1);
return 0;
}
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index 197269b..c8dd553 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -265,7 +265,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
break;
case TLB_CONTROL_FLUSH_ALL_ASID:
/* FIXME: this is not 100% correct but should work for now */
- tlb_flush(env, 1);
+ tlb_flush(cs, 1);
break;
}
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
index 69bc6bb..2d04bae 100644
--- a/target-lm32/cpu.c
+++ b/target-lm32/cpu.c
@@ -56,7 +56,7 @@ static void lm32_cpu_reset(CPUState *s)
/* reset cpu state */
memset(env, 0, offsetof(CPULM32State, eba));
- tlb_flush(env, 1);
+ tlb_flush(s, 1);
}
static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index b24120d..096de44 100644
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -78,7 +78,7 @@ static void m68k_cpu_reset(CPUState *s)
env->cc_op = CC_OP_FLAGS;
/* TODO: We should set PC from the interrupt vector. */
env->pc = 0;
- tlb_flush(env, 1);
+ tlb_flush(s, 1);
}
/* CPU models */
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index d724b6e..5a5fa5b 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -75,7 +75,7 @@ static void mb_cpu_reset(CPUState *s)
memset(env, 0, sizeof(CPUMBState));
env->res_addr = RES_ADDR_NONE;
- tlb_flush(env, 1);
+ tlb_flush(s, 1);
/* Disable stack protector. */
env->shr = ~0;
diff --git a/target-microblaze/mmu.c b/target-microblaze/mmu.c
index 5b768f2..d10146e 100644
--- a/target-microblaze/mmu.c
+++ b/target-microblaze/mmu.c
@@ -253,7 +253,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
/* Changes to the zone protection reg flush the QEMU TLB.
Fortunately, these are very uncommon. */
if (v != env->mmu.regs[rn]) {
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
env->mmu.regs[rn] = v;
break;
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index 8f26d11..c322f9b 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -102,7 +102,7 @@ static void mips_cpu_reset(CPUState *s)
mcc->parent_reset(s);
memset(env, 0, offsetof(CPUMIPSState, mvp));
- tlb_flush(env, 1);
+ tlb_flush(s, 1);
cpu_state_reset(env);
}
diff --git a/target-mips/machine.c b/target-mips/machine.c
index 23504ba..0a07db8 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -191,6 +191,7 @@ static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
CPUMIPSState *env = opaque;
+ MIPSCPU *cpu = mips_env_get_cpu(env);
int i;
if (version_id != 3)
@@ -303,6 +304,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
load_fpu(f, &env->fpus[i]);
/* XXX: ensure compatibility for halted bit ? */
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
return 0;
}
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 14f727f..04fa7a2 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1775,8 +1775,10 @@ target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
/* TLB management */
static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
{
+ MIPSCPU *cpu = mips_env_get_cpu(env);
+
/* Flush qemu's TLB and discard all shadowed entries. */
- tlb_flush (env, flush_global);
+ tlb_flush(CPU(cpu), flush_global);
env->tlb->tlb_in_use = env->tlb->nb_tlb;
}
diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
index f7d1e6c..708501e 100644
--- a/target-moxie/cpu.c
+++ b/target-moxie/cpu.c
@@ -55,7 +55,7 @@ static void moxie_cpu_reset(CPUState *s)
memset(env, 0, sizeof(CPUMoxieState));
env->pc = 0x1000;
- tlb_flush(env, 1);
+ tlb_flush(s, 1);
}
static void moxie_cpu_realizefn(DeviceState *dev, Error **errp)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 3eae4e9..04dd8eb 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -68,7 +68,7 @@ static void openrisc_cpu_reset(CPUState *s)
memset(&cpu->env, 0, offsetof(CPUOpenRISCState, irq));
#endif
- tlb_flush(&cpu->env, 1);
+ tlb_flush(s, 1);
/*tb_flush(&cpu->env); FIXME: Do we need it? */
cpu->env.pc = 0x100;
diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
index 52bcc6e..062e205 100644
--- a/target-openrisc/interrupt.c
+++ b/target-openrisc/interrupt.c
@@ -55,7 +55,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
/* For machine-state changed between user-mode and supervisor mode,
we need flush TLB when we enter&exit EXCP. */
- tlb_flush(env, 1);
+ tlb_flush(cs, 1);
env->esr = env->sr;
env->sr &= ~SR_DME;
diff --git a/target-openrisc/interrupt_helper.c b/target-openrisc/interrupt_helper.c
index 844648f..8194057 100644
--- a/target-openrisc/interrupt_helper.c
+++ b/target-openrisc/interrupt_helper.c
@@ -51,7 +51,7 @@ void HELPER(rfe)(CPUOpenRISCState *env)
}
if (need_flush_tlb) {
- tlb_flush(&cpu->env, 1);
+ tlb_flush(cs, 1);
}
#endif
cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c
index 8f07f78..677f2d7 100644
--- a/target-openrisc/sys_helper.c
+++ b/target-openrisc/sys_helper.c
@@ -45,7 +45,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
case TO_SPR(0, 17): /* SR */
if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
(rb & (SR_IME | SR_DME | SR_SM))) {
- tlb_flush(env, 1);
+ tlb_flush(cs, 1);
}
env->sr = rb;
env->sr |= SR_FO; /* FO is const equal to 1 */
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index ef67b0e..449e78a 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -609,7 +609,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
}
/* If we disactivated any translation, flush TLBs */
if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) {
- tlb_flush(env, 1);
+ tlb_flush(cs, 1);
}
#ifdef TARGET_PPC64
@@ -664,7 +664,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
/* XXX: The BookE changes address space when switching modes,
we should probably implement that as different MMU indexes,
but for the moment we do it the slow way and flush all. */
- tlb_flush(env, 1);
+ tlb_flush(cs, 1);
}
}
diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
index a6d5e2f..a09bf03 100644
--- a/target-ppc/helper_regs.h
+++ b/target-ppc/helper_regs.h
@@ -83,7 +83,7 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
if (((value >> MSR_IR) & 1) != msr_ir ||
((value >> MSR_DR) & 1) != msr_dr) {
/* Flush all tlb when changing translation mode */
- tlb_flush(env, 1);
+ tlb_flush(cs, 1);
excp = POWERPC_EXCP_NONE;
cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
}
diff --git a/target-ppc/misc_helper.c b/target-ppc/misc_helper.c
index 616aab6..d04dafd 100644
--- a/target-ppc/misc_helper.c
+++ b/target-ppc/misc_helper.c
@@ -60,10 +60,12 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
if (likely(env->pb[num] != value)) {
env->pb[num] = value;
/* Should be optimized */
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
}
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index b060e69..74e8ffb 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -94,6 +94,7 @@ void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
void helper_slbia(CPUPPCState *env)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
int n, do_invalidate;
do_invalidate = 0;
@@ -111,12 +112,13 @@ void helper_slbia(CPUPPCState *env)
}
}
if (do_invalidate) {
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
}
void helper_slbie(CPUPPCState *env, target_ulong addr)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
ppc_slb_t *slb;
slb = slb_lookup(env, addr);
@@ -131,7 +133,7 @@ void helper_slbie(CPUPPCState *env, target_ulong addr)
* and we still don't have a tlb_flush_mask(env, n, mask)
* in QEMU, we just invalidate all TLBs
*/
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
}
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index cf652b7..b0db1ce 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -231,6 +231,7 @@ static inline int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr,
static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
ppc6xx_tlb_t *tlb;
int nr, max;
@@ -244,7 +245,7 @@ static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env)
tlb = &env->tlb.tlb6[nr];
pte_invalidate(&tlb->pte0);
}
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env,
@@ -644,6 +645,7 @@ static int ppcemb_tlb_search(CPUPPCState *env, target_ulong address,
/* Helpers specific to PowerPC 40x implementations */
static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
ppcemb_tlb_t *tlb;
int i;
@@ -651,7 +653,7 @@ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env)
tlb = &env->tlb.tlbe[i];
tlb->prot &= ~PAGE_VALID;
}
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env,
@@ -862,6 +864,7 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
static void booke206_flush_tlb(CPUPPCState *env, int flags,
const int check_iprot)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
int tlb_size;
int i, j;
ppcmas_tlb_t *tlb = env->tlb.tlbm;
@@ -878,7 +881,7 @@ static void booke206_flush_tlb(CPUPPCState *env, int flags,
tlb += booke206_tlb_size(env, i);
}
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
static hwaddr booke206_tlb_to_page_size(CPUPPCState *env,
@@ -1918,7 +1921,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");
break;
case POWERPC_MMU_BOOKE:
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
break;
case POWERPC_MMU_BOOKE206:
booke206_flush_tlb(env, -1, 0);
@@ -1931,7 +1934,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
case POWERPC_MMU_2_06a:
case POWERPC_MMU_2_06d:
#endif /* defined(TARGET_PPC64) */
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
break;
default:
/* XXX: TODO */
@@ -2009,7 +2012,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
* and we still don't have a tlb_flush_mask(env, n, mask) in QEMU,
* we just invalidate all TLBs
*/
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
break;
#endif /* defined(TARGET_PPC64) */
default:
@@ -2026,6 +2029,8 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
/* Special registers manipulation */
void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value);
if (env->spr[SPR_SDR1] != value) {
env->spr[SPR_SDR1] = value;
@@ -2047,7 +2052,7 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
env->htab_mask = ((value & SDR_32_HTABMASK) << 16) | 0xFFFF;
env->htab_base = value & SDR_32_HTABORG;
}
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
}
@@ -2065,6 +2070,8 @@ target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num)
void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__,
(int)srnum, value, env->sr[srnum]);
#if defined(TARGET_PPC64)
@@ -2097,11 +2104,11 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value)
page = (16 << 20) * srnum;
end = page + (16 << 20);
for (; page != end; page += TARGET_PAGE_SIZE) {
- tlb_flush_page(env, page);
+ tlb_flush_page(CPU(cpu), page);
}
}
#else
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
#endif
}
}
@@ -2423,6 +2430,7 @@ target_ulong helper_4xx_tlbsx(CPUPPCState *env, target_ulong address)
void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry,
target_ulong value)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
ppcemb_tlb_t *tlb;
target_ulong EPN, RPN, size;
int do_flush_tlbs;
@@ -2458,13 +2466,13 @@ void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry,
}
tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
if (do_flush_tlbs) {
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
break;
case 1:
RPN = value & 0xFFFFFC0F;
if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN) {
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
tlb->RPN = RPN;
break;
@@ -2576,9 +2584,11 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env)
void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
+
env->spr[pidn] = pid;
/* changing PIDs mean we're in a different address space now */
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
void helper_booke206_tlbwe(CPUPPCState *env)
@@ -2673,7 +2683,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) {
tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK);
} else {
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
}
@@ -2797,7 +2807,7 @@ void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address)
if (address & 0x8) {
/* flush TLB1 entries */
booke206_invalidate_ea_tlb(env, 1, address);
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
} else {
/* flush TLB0 entries */
booke206_invalidate_ea_tlb(env, 0, address);
@@ -2813,6 +2823,7 @@ void helper_booke206_tlbilx0(CPUPPCState *env, target_ulong address)
void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
int i, j;
int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID);
ppcmas_tlb_t *tlb = env->tlb.tlbm;
@@ -2829,11 +2840,12 @@ void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address)
}
tlb += booke206_tlb_size(env, i);
}
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address)
{
+ PowerPCCPU *cpu = ppc_env_get_cpu(env);
int i, j;
ppcmas_tlb_t *tlb;
int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID);
@@ -2869,7 +2881,7 @@ void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address)
tlb->mas1 &= ~MAS1_VALID;
}
}
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
void helper_booke206_tlbflush(CPUPPCState *env, uint32_t type)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 1df82c5..eb8b7e7 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8521,7 +8521,7 @@ static void ppc_cpu_reset(CPUState *s)
#endif /* TARGET_PPC64 */
/* Flush all TLBs */
- tlb_flush(env, 1);
+ tlb_flush(s, 1);
}
static void ppc_cpu_initfn(Object *obj)
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index d9b8470..608df5e 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -113,14 +113,13 @@ static void s390_cpu_reset(CPUState *s)
{
S390CPU *cpu = S390_CPU(s);
S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
- CPUS390XState *env = &cpu->env;
s390_del_running_cpu(cpu);
scc->parent_reset(s);
#if !defined(CONFIG_USER_ONLY)
s->halted = 1;
#endif
- tlb_flush(env, 1);
+ tlb_flush(s, 1);
}
/* S390CPUClass::initial_reset() */
@@ -161,7 +160,7 @@ static void s390_cpu_full_reset(CPUState *s)
#if !defined(CONFIG_USER_ONLY)
s->halted = 1;
#endif
- tlb_flush(env, 1);
+ tlb_flush(s, 1);
}
#if !defined(CONFIG_USER_ONLY)
diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
index 6bff6cc..bae6a5b 100644
--- a/target-s390x/mem_helper.c
+++ b/target-s390x/mem_helper.c
@@ -810,6 +810,7 @@ void HELPER(tr)(CPUS390XState *env, uint32_t len, uint64_t array,
#if !defined(CONFIG_USER_ONLY)
void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
{
+ S390CPU *cpu = s390_env_get_cpu(env);
int i;
uint64_t src = a2;
@@ -824,11 +825,12 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
}
}
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
{
+ S390CPU *cpu = s390_env_get_cpu(env);
int i;
uint64_t src = a2;
@@ -842,7 +844,7 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
}
}
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
void HELPER(stctg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
@@ -935,6 +937,7 @@ uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2)
/* compare and swap and purge */
uint32_t HELPER(csp)(CPUS390XState *env, uint32_t r1, uint64_t r2)
{
+ S390CPU *cpu = s390_env_get_cpu(env);
uint32_t cc;
uint32_t o1 = env->regs[r1];
uint64_t a2 = r2 & ~3ULL;
@@ -944,7 +947,7 @@ uint32_t HELPER(csp)(CPUS390XState *env, uint32_t r1, uint64_t r2)
cpu_stl_data(env, a2, env->regs[(r1 + 1) & 15]);
if (r2 & 0x3) {
/* flush TLB / ALB */
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
cc = 0;
} else {
@@ -1039,7 +1042,9 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pte_addr, uint64_t vaddr)
/* flush local tlb */
void HELPER(ptlb)(CPUS390XState *env)
{
- tlb_flush(env, 1);
+ S390CPU *cpu = s390_env_get_cpu(env);
+
+ tlb_flush(CPU(cpu), 1);
}
/* store using real address */
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index fb176bf..05720f1 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -77,7 +77,7 @@ static void superh_cpu_reset(CPUState *s)
scc->parent_reset(s);
memset(env, 0, offsetof(CPUSH4State, id));
- tlb_flush(env, 1);
+ tlb_flush(s, 1);
env->pc = 0xA0000000;
#if defined(CONFIG_USER_ONLY)
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index c56e543..9ebdd5c 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -585,7 +585,7 @@ void cpu_load_tlb(CPUSH4State * env)
entry->v = 0;
}
- tlb_flush(s, 1);
+ tlb_flush(CPU(sh_env_get_cpu(s)), 1);
}
uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
index 6c1ff68..e1f6e61 100644
--- a/target-sparc/cpu.c
+++ b/target-sparc/cpu.c
@@ -33,7 +33,7 @@ static void sparc_cpu_reset(CPUState *s)
scc->parent_reset(s);
memset(env, 0, offsetof(CPUSPARCState, version));
- tlb_flush(env, 1);
+ tlb_flush(s, 1);
env->cwp = 0;
#ifndef TARGET_SPARC64
env->wim = 1;
diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
index 44c54f1..bf75ceb 100644
--- a/target-sparc/ldst_helper.c
+++ b/target-sparc/ldst_helper.c
@@ -865,7 +865,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
case 2: /* flush region (16M) */
case 3: /* flush context (4G) */
case 4: /* flush entire */
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
break;
default:
break;
@@ -890,7 +890,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
disabled mode are invalid in normal mode */
if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
(env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) {
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
break;
case 1: /* Context Table Pointer Register */
@@ -901,7 +901,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
if (oldreg != env->mmuregs[reg]) {
/* we flush when the MMU context changes because
QEMU has no MMU context support */
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
break;
case 3: /* Synchronous Fault Status Register with Clear */
@@ -1657,6 +1657,8 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
int asi, int size)
{
+ SPARCCPU *cpu = sparc_env_get_cpu(env);
+
#ifdef DEBUG_ASI
dump_asi("write", addr, asi, size, val);
#endif
@@ -1865,7 +1867,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
#ifdef DEBUG_MMU
dump_mmu(stdout, fprintf, env);
#endif
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
return;
}
@@ -1954,13 +1956,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
env->dmmu.mmu_primary_context = val;
/* can be optimized to only flush MMU_USER_IDX
and MMU_KERNEL_IDX entries */
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
break;
case 2: /* Secondary context */
env->dmmu.mmu_secondary_context = val;
/* can be optimized to only flush MMU_USER_SECONDARY_IDX
and MMU_KERNEL_SECONDARY_IDX entries */
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
break;
case 5: /* TSB access */
DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
@@ -2389,7 +2391,7 @@ void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
/* flush neverland mappings created during no-fault mode,
so the sequential MMU faults report proper fault types */
if (env->mmuregs[0] & MMU_NF) {
- tlb_flush(env, 1);
+ tlb_flush(cs, 1);
}
}
#else
diff --git a/target-sparc/machine.c b/target-sparc/machine.c
index a353dab..3f3de4c 100644
--- a/target-sparc/machine.c
+++ b/target-sparc/machine.c
@@ -112,6 +112,7 @@ void cpu_save(QEMUFile *f, void *opaque)
int cpu_load(QEMUFile *f, void *opaque, int version_id)
{
CPUSPARCState *env = opaque;
+ SPARCCPU *cpu = sparc_env_get_cpu(env);
int i;
uint32_t tmp;
@@ -212,6 +213,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_be64s(f, &env->ssr);
cpu_get_timer(f, env->hstick);
#endif
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
return 0;
}
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index dcf3b16..a317217 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -141,7 +141,7 @@ static void uc32_cpu_initfn(Object *obj)
env->regs[31] = 0x03000000;
#endif
- tlb_flush(env, 1);
+ tlb_flush(cs, 1);
if (tcg_enabled() && !inited) {
inited = true;
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index f91ed93..8de6a33 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -57,6 +57,8 @@ uint32_t HELPER(clz)(uint32_t x)
void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
uint32_t cop)
{
+ UniCore32CPU *cpu = uc32_env_get_cpu(env);
+
/*
* movc pp.nn, rn, #imm9
* rn: UCOP_REG_D
@@ -125,7 +127,7 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
case 6:
if ((cop <= 6) && (cop >= 2)) {
/* invalid all tlb */
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
return;
}
break;
diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
index 5771841..70937b6 100644
--- a/target-xtensa/op_helper.c
+++ b/target-xtensa/op_helper.c
@@ -479,10 +479,12 @@ void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr)
void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
{
+ XtensaCPU *cpu = xtensa_env_get_cpu(env);
+
v = (v & 0xffffff00) | 0x1;
if (v != env->sregs[RASID]) {
env->sregs[RASID] = v;
- tlb_flush(env, 1);
+ tlb_flush(CPU(cpu), 1);
}
}
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 40/41] cputlb: Change tlb_flush() argument to CPUState
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 40/41] cputlb: Change tlb_flush() " Andreas Färber
@ 2013-09-04 12:50 ` Jia Liu
0 siblings, 0 replies; 68+ messages in thread
From: Jia Liu @ 2013-09-04 12:50 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Anthony Green, qemu-devel@nongnu.org,
Alexander Graf, Blue Swirl, Max Filippov, Michael Walle,
open list:PowerPC, Paul Brook, Edgar E. Iglesias, Guan Xuetao,
Aurelien Jarno, Richard Henderson
On Wed, Sep 4, 2013 at 5:05 PM, Andreas Färber <afaerber@suse.de> wrote:
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> ---
> cputlb.c | 6 +++---
> exec.c | 4 +---
> hw/sh4/sh7750.c | 2 +-
> include/exec/exec-all.h | 4 ++--
> target-alpha/cpu.c | 2 +-
> target-alpha/sys_helper.c | 2 +-
> target-arm/cpu.c | 2 +-
> target-arm/helper.c | 28 +++++++++++++++++-------
> target-cris/cpu.c | 2 +-
> target-i386/cpu.c | 2 +-
> target-i386/helper.c | 17 ++++++++++-----
> target-i386/machine.c | 2 +-
> target-i386/svm_helper.c | 2 +-
> target-lm32/cpu.c | 2 +-
> target-m68k/cpu.c | 2 +-
> target-microblaze/cpu.c | 2 +-
> target-microblaze/mmu.c | 2 +-
> target-mips/cpu.c | 2 +-
> target-mips/machine.c | 3 ++-
> target-mips/op_helper.c | 4 +++-
> target-moxie/cpu.c | 2 +-
> target-openrisc/cpu.c | 2 +-
> target-openrisc/interrupt.c | 2 +-
> target-openrisc/interrupt_helper.c | 2 +-
> target-openrisc/sys_helper.c | 2 +-
> target-ppc/excp_helper.c | 4 ++--
> target-ppc/helper_regs.h | 2 +-
> target-ppc/misc_helper.c | 4 +++-
> target-ppc/mmu-hash64.c | 6 ++++--
> target-ppc/mmu_helper.c | 44 ++++++++++++++++++++++++--------------
> target-ppc/translate_init.c | 2 +-
> target-s390x/cpu.c | 5 ++---
> target-s390x/mem_helper.c | 13 +++++++----
> target-sh4/cpu.c | 2 +-
> target-sh4/helper.c | 2 +-
> target-sparc/cpu.c | 2 +-
> target-sparc/ldst_helper.c | 16 ++++++++------
> target-sparc/machine.c | 3 ++-
> target-unicore32/cpu.c | 2 +-
> target-unicore32/helper.c | 4 +++-
> target-xtensa/op_helper.c | 4 +++-
> 41 files changed, 132 insertions(+), 85 deletions(-)
>
> diff --git a/cputlb.c b/cputlb.c
> index 817180e..bfa7417 100644
> --- a/cputlb.c
> +++ b/cputlb.c
> @@ -52,9 +52,9 @@ static const CPUTLBEntry s_cputlb_empty_entry = {
> * entries from the TLB at any time, so flushing more entries than
> * required is only an efficiency issue, not a correctness issue.
> */
> -void tlb_flush(CPUArchState *env, int flush_global)
> +void tlb_flush(CPUState *cpu, int flush_global)
> {
> - CPUState *cpu = ENV_GET_CPU(env);
> + CPUArchState *env = cpu->env_ptr;
> int i;
>
> #if defined(DEBUG_TLB)
> @@ -107,7 +107,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr)
> VADDR_PRIx "/%" VADDR_PRIx ")\n",
> cpu->tlb_flush_addr, cpu->tlb_flush_mask);
> #endif
> - tlb_flush(env, 1);
> + tlb_flush(cpu, 1);
> return;
> }
> /* must reset current TB so that interrupts cannot modify the
> diff --git a/exec.c b/exec.c
> index 9210834..8e514e8 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -1720,9 +1720,7 @@ static void tcg_commit(MemoryListener *listener)
> reset the modified entries */
> /* XXX: slow ! */
> CPU_FOREACH(cpu) {
> - CPUArchState *env = cpu->env_ptr;
> -
> - tlb_flush(env, 1);
> + tlb_flush(cpu, 1);
> }
> }
>
> diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c
> index 1439ba4..4a39357 100644
> --- a/hw/sh4/sh7750.c
> +++ b/hw/sh4/sh7750.c
> @@ -416,7 +416,7 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr,
> case SH7750_PTEH_A7:
> /* If asid changes, clear all registered tlb entries. */
> if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) {
> - tlb_flush(&s->cpu->env, 1);
> + tlb_flush(CPU(s->cpu), 1);
> }
> s->cpu->env.pteh = mem_value;
> return;
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index 550e58d..f2d1c6c 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -97,7 +97,7 @@ void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end,
> #if !defined(CONFIG_USER_ONLY)
> /* cputlb.c */
> void tlb_flush_page(CPUState *cpu, target_ulong addr);
> -void tlb_flush(CPUArchState *env, int flush_global);
> +void tlb_flush(CPUState *cpu, int flush_global);
> void tlb_set_page(CPUState *cpu, target_ulong vaddr,
> hwaddr paddr, int prot,
> int mmu_idx, target_ulong size);
> @@ -107,7 +107,7 @@ static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
> {
> }
>
> -static inline void tlb_flush(CPUArchState *env, int flush_global)
> +static inline void tlb_flush(CPUState *cpu, int flush_global)
> {
> }
> #endif
> diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c
> index 9931f9f..d839d53 100644
> --- a/target-alpha/cpu.c
> +++ b/target-alpha/cpu.c
> @@ -294,7 +294,7 @@ static void alpha_cpu_initfn(Object *obj)
>
> cs->env_ptr = env;
> cpu_exec_init(env);
> - tlb_flush(env, 1);
> + tlb_flush(cs, 1);
>
> alpha_translate_init();
>
> diff --git a/target-alpha/sys_helper.c b/target-alpha/sys_helper.c
> index 5f7d7dd..187ccf7 100644
> --- a/target-alpha/sys_helper.c
> +++ b/target-alpha/sys_helper.c
> @@ -64,7 +64,7 @@ void helper_call_pal(CPUAlphaState *env, uint64_t pc, uint64_t entry_ofs)
>
> void helper_tbia(CPUAlphaState *env)
> {
> - tlb_flush(env, 1);
> + tlb_flush(CPU(alpha_env_get_cpu(env)), 1);
> }
>
> void helper_tbis(CPUAlphaState *env, uint64_t p)
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index f9f6930..2a0e891 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -163,7 +163,7 @@ static void arm_cpu_reset(CPUState *s)
> &env->vfp.fp_status);
> set_float_detect_tininess(float_tininess_before_rounding,
> &env->vfp.standard_fp_status);
> - tlb_flush(env, 1);
> + tlb_flush(s, 1);
> /* Reset is a state change for some CPUARMState fields which we
> * bake assumptions about into translated code, so we need to
> * tb_flush().
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 4daf82e..7c87ffa 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -270,18 +270,22 @@ void init_cpreg_list(ARMCPU *cpu)
>
> static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
> {
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> env->cp15.c3 = value;
> - tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
> + tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
> return 0;
> }
>
> static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
> {
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> if (env->cp15.c13_fcse != value) {
> /* Unlike real hardware the qemu TLB uses virtual addresses,
> * not modified virtual addresses, so this causes a TLB flush.
> */
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> env->cp15.c13_fcse = value;
> }
> return 0;
> @@ -289,12 +293,14 @@ static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
> static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
> /* For VMSA (when not using the LPAE long descriptor page table
> * format) this register includes the ASID, so do a TLB flush.
> * For PMSA it is purely a process ID and no action is needed.
> */
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
> env->cp15.c13_context = value;
> return 0;
> @@ -303,8 +309,10 @@ static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> /* Invalidate all (TLBIALL) */
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> return 0;
> }
>
> @@ -321,8 +329,10 @@ static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
> static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> /* Invalidate by ASID (TLBIASID) */
> - tlb_flush(env, value == 0);
> + tlb_flush(CPU(cpu), value == 0);
> return 0;
> }
>
> @@ -1178,11 +1188,13 @@ static int vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
> static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> + ARMCPU *cpu = arm_env_get_cpu(env);
> +
> if (arm_feature(env, ARM_FEATURE_LPAE)) {
> /* With LPAE the TTBCR could result in a change of ASID
> * via the TTBCR.A1 bit, so do a TLB flush.
> */
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
> return vmsa_ttbcr_raw_write(env, ri, value);
> }
> @@ -1444,7 +1456,7 @@ static int ttbr064_write(CPUARMState *env, const ARMCPRegInfo *ri,
> uint64_t value)
> {
> /* Writes to the 64 bit format TTBRs may change the ASID */
> - tlb_flush(env, 1);
> + tlb_flush(CPU(arm_env_get_cpu(env)), 1);
> return ttbr064_raw_write(env, ri, value);
> }
>
> @@ -1508,7 +1520,7 @@ static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
> env->cp15.c1_sys = value;
> /* ??? Lots of these bits are not implemented. */
> /* This may enable/disable the MMU, so do a TLB flush. */
> - tlb_flush(env, 1);
> + tlb_flush(CPU(arm_env_get_cpu(env)), 1);
> return 0;
> }
>
> diff --git a/target-cris/cpu.c b/target-cris/cpu.c
> index b229a10..b7dbd08 100644
> --- a/target-cris/cpu.c
> +++ b/target-cris/cpu.c
> @@ -71,7 +71,7 @@ static void cris_cpu_reset(CPUState *s)
> vr = env->pregs[PR_VR];
> memset(env, 0, offsetof(CPUCRISState, load_info));
> env->pregs[PR_VR] = vr;
> - tlb_flush(env, 1);
> + tlb_flush(s, 1);
>
> #if defined(CONFIG_USER_ONLY)
> /* start in user mode with interrupts enabled. */
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 944c3d7..b08c367 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -2330,7 +2330,7 @@ static void x86_cpu_reset(CPUState *s)
>
> memset(env, 0, offsetof(CPUX86State, pat));
>
> - tlb_flush(env, 1);
> + tlb_flush(s, 1);
>
> env->old_exception = -1;
>
> diff --git a/target-i386/helper.c b/target-i386/helper.c
> index e0df092..ac21cc4 100644
> --- a/target-i386/helper.c
> +++ b/target-i386/helper.c
> @@ -385,22 +385,25 @@ void x86_cpu_set_a20(X86CPU *cpu, int a20_state)
>
> a20_state = (a20_state != 0);
> if (a20_state != ((env->a20_mask >> 20) & 1)) {
> + CPUState *cs = CPU(cpu);
> +
> #if defined(DEBUG_MMU)
> printf("A20 update: a20=%d\n", a20_state);
> #endif
> /* if the cpu is currently executing code, we must unlink it and
> all the potentially executing TB */
> - cpu_interrupt(CPU(cpu), CPU_INTERRUPT_EXITTB);
> + cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
>
> /* when a20 is changed, all the MMU mappings are invalid, so
> we must flush everything */
> - tlb_flush(env, 1);
> + tlb_flush(cs, 1);
> env->a20_mask = ~(1 << 20) | (a20_state << 20);
> }
> }
>
> void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
> {
> + X86CPU *cpu = x86_env_get_cpu(env);
> int pe_state;
>
> #if defined(DEBUG_MMU)
> @@ -408,7 +411,7 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
> #endif
> if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
> (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
>
> #ifdef TARGET_X86_64
> @@ -444,24 +447,28 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
> the PDPT */
> void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
> {
> + X86CPU *cpu = x86_env_get_cpu(env);
> +
> env->cr[3] = new_cr3;
> if (env->cr[0] & CR0_PG_MASK) {
> #if defined(DEBUG_MMU)
> printf("CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
> #endif
> - tlb_flush(env, 0);
> + tlb_flush(CPU(cpu), 0);
> }
> }
>
> void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
> {
> + X86CPU *cpu = x86_env_get_cpu(env);
> +
> #if defined(DEBUG_MMU)
> printf("CR4 update: CR4=%08x\n", (uint32_t)env->cr[4]);
> #endif
> if ((new_cr4 ^ env->cr[4]) &
> (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK |
> CR4_SMEP_MASK | CR4_SMAP_MASK)) {
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
> /* SSE handling */
> if (!(env->features[FEAT_1_EDX] & CPUID_SSE)) {
> diff --git a/target-i386/machine.c b/target-i386/machine.c
> index 54dd2ab..371c126 100644
> --- a/target-i386/machine.c
> +++ b/target-i386/machine.c
> @@ -310,7 +310,7 @@ static int cpu_post_load(void *opaque, int version_id)
> for (i = 0; i < DR7_MAX_BP; i++) {
> hw_breakpoint_insert(env, i);
> }
> - tlb_flush(env, 1);
> + tlb_flush(cs, 1);
>
> return 0;
> }
> diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
> index 197269b..c8dd553 100644
> --- a/target-i386/svm_helper.c
> +++ b/target-i386/svm_helper.c
> @@ -265,7 +265,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
> break;
> case TLB_CONTROL_FLUSH_ALL_ASID:
> /* FIXME: this is not 100% correct but should work for now */
> - tlb_flush(env, 1);
> + tlb_flush(cs, 1);
> break;
> }
>
> diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
> index 69bc6bb..2d04bae 100644
> --- a/target-lm32/cpu.c
> +++ b/target-lm32/cpu.c
> @@ -56,7 +56,7 @@ static void lm32_cpu_reset(CPUState *s)
> /* reset cpu state */
> memset(env, 0, offsetof(CPULM32State, eba));
>
> - tlb_flush(env, 1);
> + tlb_flush(s, 1);
> }
>
> static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
> diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
> index b24120d..096de44 100644
> --- a/target-m68k/cpu.c
> +++ b/target-m68k/cpu.c
> @@ -78,7 +78,7 @@ static void m68k_cpu_reset(CPUState *s)
> env->cc_op = CC_OP_FLAGS;
> /* TODO: We should set PC from the interrupt vector. */
> env->pc = 0;
> - tlb_flush(env, 1);
> + tlb_flush(s, 1);
> }
>
> /* CPU models */
> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
> index d724b6e..5a5fa5b 100644
> --- a/target-microblaze/cpu.c
> +++ b/target-microblaze/cpu.c
> @@ -75,7 +75,7 @@ static void mb_cpu_reset(CPUState *s)
>
> memset(env, 0, sizeof(CPUMBState));
> env->res_addr = RES_ADDR_NONE;
> - tlb_flush(env, 1);
> + tlb_flush(s, 1);
>
> /* Disable stack protector. */
> env->shr = ~0;
> diff --git a/target-microblaze/mmu.c b/target-microblaze/mmu.c
> index 5b768f2..d10146e 100644
> --- a/target-microblaze/mmu.c
> +++ b/target-microblaze/mmu.c
> @@ -253,7 +253,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
> /* Changes to the zone protection reg flush the QEMU TLB.
> Fortunately, these are very uncommon. */
> if (v != env->mmu.regs[rn]) {
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
> env->mmu.regs[rn] = v;
> break;
> diff --git a/target-mips/cpu.c b/target-mips/cpu.c
> index 8f26d11..c322f9b 100644
> --- a/target-mips/cpu.c
> +++ b/target-mips/cpu.c
> @@ -102,7 +102,7 @@ static void mips_cpu_reset(CPUState *s)
> mcc->parent_reset(s);
>
> memset(env, 0, offsetof(CPUMIPSState, mvp));
> - tlb_flush(env, 1);
> + tlb_flush(s, 1);
>
> cpu_state_reset(env);
> }
> diff --git a/target-mips/machine.c b/target-mips/machine.c
> index 23504ba..0a07db8 100644
> --- a/target-mips/machine.c
> +++ b/target-mips/machine.c
> @@ -191,6 +191,7 @@ static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
> int cpu_load(QEMUFile *f, void *opaque, int version_id)
> {
> CPUMIPSState *env = opaque;
> + MIPSCPU *cpu = mips_env_get_cpu(env);
> int i;
>
> if (version_id != 3)
> @@ -303,6 +304,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
> load_fpu(f, &env->fpus[i]);
>
> /* XXX: ensure compatibility for halted bit ? */
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> return 0;
> }
> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
> index 14f727f..04fa7a2 100644
> --- a/target-mips/op_helper.c
> +++ b/target-mips/op_helper.c
> @@ -1775,8 +1775,10 @@ target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
> /* TLB management */
> static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
> {
> + MIPSCPU *cpu = mips_env_get_cpu(env);
> +
> /* Flush qemu's TLB and discard all shadowed entries. */
> - tlb_flush (env, flush_global);
> + tlb_flush(CPU(cpu), flush_global);
> env->tlb->tlb_in_use = env->tlb->nb_tlb;
> }
>
> diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
> index f7d1e6c..708501e 100644
> --- a/target-moxie/cpu.c
> +++ b/target-moxie/cpu.c
> @@ -55,7 +55,7 @@ static void moxie_cpu_reset(CPUState *s)
> memset(env, 0, sizeof(CPUMoxieState));
> env->pc = 0x1000;
>
> - tlb_flush(env, 1);
> + tlb_flush(s, 1);
> }
>
> static void moxie_cpu_realizefn(DeviceState *dev, Error **errp)
> diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
> index 3eae4e9..04dd8eb 100644
> --- a/target-openrisc/cpu.c
> +++ b/target-openrisc/cpu.c
> @@ -68,7 +68,7 @@ static void openrisc_cpu_reset(CPUState *s)
> memset(&cpu->env, 0, offsetof(CPUOpenRISCState, irq));
> #endif
>
> - tlb_flush(&cpu->env, 1);
> + tlb_flush(s, 1);
> /*tb_flush(&cpu->env); FIXME: Do we need it? */
>
> cpu->env.pc = 0x100;
> diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
> index 52bcc6e..062e205 100644
> --- a/target-openrisc/interrupt.c
> +++ b/target-openrisc/interrupt.c
> @@ -55,7 +55,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
>
> /* For machine-state changed between user-mode and supervisor mode,
> we need flush TLB when we enter&exit EXCP. */
> - tlb_flush(env, 1);
> + tlb_flush(cs, 1);
>
> env->esr = env->sr;
> env->sr &= ~SR_DME;
> diff --git a/target-openrisc/interrupt_helper.c b/target-openrisc/interrupt_helper.c
> index 844648f..8194057 100644
> --- a/target-openrisc/interrupt_helper.c
> +++ b/target-openrisc/interrupt_helper.c
> @@ -51,7 +51,7 @@ void HELPER(rfe)(CPUOpenRISCState *env)
> }
>
> if (need_flush_tlb) {
> - tlb_flush(&cpu->env, 1);
> + tlb_flush(cs, 1);
> }
> #endif
> cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
> diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c
> index 8f07f78..677f2d7 100644
> --- a/target-openrisc/sys_helper.c
> +++ b/target-openrisc/sys_helper.c
> @@ -45,7 +45,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
> case TO_SPR(0, 17): /* SR */
> if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
> (rb & (SR_IME | SR_DME | SR_SM))) {
> - tlb_flush(env, 1);
> + tlb_flush(cs, 1);
> }
> env->sr = rb;
> env->sr |= SR_FO; /* FO is const equal to 1 */
> diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
> index ef67b0e..449e78a 100644
> --- a/target-ppc/excp_helper.c
> +++ b/target-ppc/excp_helper.c
> @@ -609,7 +609,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
> }
> /* If we disactivated any translation, flush TLBs */
> if (msr & ((1 << MSR_IR) | (1 << MSR_DR))) {
> - tlb_flush(env, 1);
> + tlb_flush(cs, 1);
> }
>
> #ifdef TARGET_PPC64
> @@ -664,7 +664,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
> /* XXX: The BookE changes address space when switching modes,
> we should probably implement that as different MMU indexes,
> but for the moment we do it the slow way and flush all. */
> - tlb_flush(env, 1);
> + tlb_flush(cs, 1);
> }
> }
>
> diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
> index a6d5e2f..a09bf03 100644
> --- a/target-ppc/helper_regs.h
> +++ b/target-ppc/helper_regs.h
> @@ -83,7 +83,7 @@ static inline int hreg_store_msr(CPUPPCState *env, target_ulong value,
> if (((value >> MSR_IR) & 1) != msr_ir ||
> ((value >> MSR_DR) & 1) != msr_dr) {
> /* Flush all tlb when changing translation mode */
> - tlb_flush(env, 1);
> + tlb_flush(cs, 1);
> excp = POWERPC_EXCP_NONE;
> cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
> }
> diff --git a/target-ppc/misc_helper.c b/target-ppc/misc_helper.c
> index 616aab6..d04dafd 100644
> --- a/target-ppc/misc_helper.c
> +++ b/target-ppc/misc_helper.c
> @@ -60,10 +60,12 @@ void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
>
> void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +
> if (likely(env->pb[num] != value)) {
> env->pb[num] = value;
> /* Should be optimized */
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
> }
>
> diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
> index b060e69..74e8ffb 100644
> --- a/target-ppc/mmu-hash64.c
> +++ b/target-ppc/mmu-hash64.c
> @@ -94,6 +94,7 @@ void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
>
> void helper_slbia(CPUPPCState *env)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> int n, do_invalidate;
>
> do_invalidate = 0;
> @@ -111,12 +112,13 @@ void helper_slbia(CPUPPCState *env)
> }
> }
> if (do_invalidate) {
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
> }
>
> void helper_slbie(CPUPPCState *env, target_ulong addr)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> ppc_slb_t *slb;
>
> slb = slb_lookup(env, addr);
> @@ -131,7 +133,7 @@ void helper_slbie(CPUPPCState *env, target_ulong addr)
> * and we still don't have a tlb_flush_mask(env, n, mask)
> * in QEMU, we just invalidate all TLBs
> */
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
> }
>
> diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
> index cf652b7..b0db1ce 100644
> --- a/target-ppc/mmu_helper.c
> +++ b/target-ppc/mmu_helper.c
> @@ -231,6 +231,7 @@ static inline int ppc6xx_tlb_getnum(CPUPPCState *env, target_ulong eaddr,
>
> static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> ppc6xx_tlb_t *tlb;
> int nr, max;
>
> @@ -244,7 +245,7 @@ static inline void ppc6xx_tlb_invalidate_all(CPUPPCState *env)
> tlb = &env->tlb.tlb6[nr];
> pte_invalidate(&tlb->pte0);
> }
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
>
> static inline void ppc6xx_tlb_invalidate_virt2(CPUPPCState *env,
> @@ -644,6 +645,7 @@ static int ppcemb_tlb_search(CPUPPCState *env, target_ulong address,
> /* Helpers specific to PowerPC 40x implementations */
> static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> ppcemb_tlb_t *tlb;
> int i;
>
> @@ -651,7 +653,7 @@ static inline void ppc4xx_tlb_invalidate_all(CPUPPCState *env)
> tlb = &env->tlb.tlbe[i];
> tlb->prot &= ~PAGE_VALID;
> }
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
>
> static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env,
> @@ -862,6 +864,7 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
> static void booke206_flush_tlb(CPUPPCState *env, int flags,
> const int check_iprot)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> int tlb_size;
> int i, j;
> ppcmas_tlb_t *tlb = env->tlb.tlbm;
> @@ -878,7 +881,7 @@ static void booke206_flush_tlb(CPUPPCState *env, int flags,
> tlb += booke206_tlb_size(env, i);
> }
>
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
>
> static hwaddr booke206_tlb_to_page_size(CPUPPCState *env,
> @@ -1918,7 +1921,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
> cpu_abort(CPU(cpu), "MPC8xx MMU model is not implemented\n");
> break;
> case POWERPC_MMU_BOOKE:
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> break;
> case POWERPC_MMU_BOOKE206:
> booke206_flush_tlb(env, -1, 0);
> @@ -1931,7 +1934,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
> case POWERPC_MMU_2_06a:
> case POWERPC_MMU_2_06d:
> #endif /* defined(TARGET_PPC64) */
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> break;
> default:
> /* XXX: TODO */
> @@ -2009,7 +2012,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
> * and we still don't have a tlb_flush_mask(env, n, mask) in QEMU,
> * we just invalidate all TLBs
> */
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> break;
> #endif /* defined(TARGET_PPC64) */
> default:
> @@ -2026,6 +2029,8 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
> /* Special registers manipulation */
> void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +
> LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value);
> if (env->spr[SPR_SDR1] != value) {
> env->spr[SPR_SDR1] = value;
> @@ -2047,7 +2052,7 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
> env->htab_mask = ((value & SDR_32_HTABMASK) << 16) | 0xFFFF;
> env->htab_base = value & SDR_32_HTABORG;
> }
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
> }
>
> @@ -2065,6 +2070,8 @@ target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num)
>
> void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +
> LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__,
> (int)srnum, value, env->sr[srnum]);
> #if defined(TARGET_PPC64)
> @@ -2097,11 +2104,11 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value)
> page = (16 << 20) * srnum;
> end = page + (16 << 20);
> for (; page != end; page += TARGET_PAGE_SIZE) {
> - tlb_flush_page(env, page);
> + tlb_flush_page(CPU(cpu), page);
> }
> }
> #else
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> #endif
> }
> }
> @@ -2423,6 +2430,7 @@ target_ulong helper_4xx_tlbsx(CPUPPCState *env, target_ulong address)
> void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry,
> target_ulong value)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> ppcemb_tlb_t *tlb;
> target_ulong EPN, RPN, size;
> int do_flush_tlbs;
> @@ -2458,13 +2466,13 @@ void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry,
> }
> tlb->PID = env->spr[SPR_440_MMUCR] & 0x000000FF;
> if (do_flush_tlbs) {
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
> break;
> case 1:
> RPN = value & 0xFFFFFC0F;
> if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN) {
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
> tlb->RPN = RPN;
> break;
> @@ -2576,9 +2584,11 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env)
>
> void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> +
> env->spr[pidn] = pid;
> /* changing PIDs mean we're in a different address space now */
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
>
> void helper_booke206_tlbwe(CPUPPCState *env)
> @@ -2673,7 +2683,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
> if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) {
> tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK);
> } else {
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
> }
>
> @@ -2797,7 +2807,7 @@ void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address)
> if (address & 0x8) {
> /* flush TLB1 entries */
> booke206_invalidate_ea_tlb(env, 1, address);
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> } else {
> /* flush TLB0 entries */
> booke206_invalidate_ea_tlb(env, 0, address);
> @@ -2813,6 +2823,7 @@ void helper_booke206_tlbilx0(CPUPPCState *env, target_ulong address)
>
> void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> int i, j;
> int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID);
> ppcmas_tlb_t *tlb = env->tlb.tlbm;
> @@ -2829,11 +2840,12 @@ void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address)
> }
> tlb += booke206_tlb_size(env, i);
> }
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
>
> void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address)
> {
> + PowerPCCPU *cpu = ppc_env_get_cpu(env);
> int i, j;
> ppcmas_tlb_t *tlb;
> int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID);
> @@ -2869,7 +2881,7 @@ void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address)
> tlb->mas1 &= ~MAS1_VALID;
> }
> }
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
>
> void helper_booke206_tlbflush(CPUPPCState *env, uint32_t type)
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index 1df82c5..eb8b7e7 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8521,7 +8521,7 @@ static void ppc_cpu_reset(CPUState *s)
> #endif /* TARGET_PPC64 */
>
> /* Flush all TLBs */
> - tlb_flush(env, 1);
> + tlb_flush(s, 1);
> }
>
> static void ppc_cpu_initfn(Object *obj)
> diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
> index d9b8470..608df5e 100644
> --- a/target-s390x/cpu.c
> +++ b/target-s390x/cpu.c
> @@ -113,14 +113,13 @@ static void s390_cpu_reset(CPUState *s)
> {
> S390CPU *cpu = S390_CPU(s);
> S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
> - CPUS390XState *env = &cpu->env;
>
> s390_del_running_cpu(cpu);
> scc->parent_reset(s);
> #if !defined(CONFIG_USER_ONLY)
> s->halted = 1;
> #endif
> - tlb_flush(env, 1);
> + tlb_flush(s, 1);
> }
>
> /* S390CPUClass::initial_reset() */
> @@ -161,7 +160,7 @@ static void s390_cpu_full_reset(CPUState *s)
> #if !defined(CONFIG_USER_ONLY)
> s->halted = 1;
> #endif
> - tlb_flush(env, 1);
> + tlb_flush(s, 1);
> }
>
> #if !defined(CONFIG_USER_ONLY)
> diff --git a/target-s390x/mem_helper.c b/target-s390x/mem_helper.c
> index 6bff6cc..bae6a5b 100644
> --- a/target-s390x/mem_helper.c
> +++ b/target-s390x/mem_helper.c
> @@ -810,6 +810,7 @@ void HELPER(tr)(CPUS390XState *env, uint32_t len, uint64_t array,
> #if !defined(CONFIG_USER_ONLY)
> void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> int i;
> uint64_t src = a2;
>
> @@ -824,11 +825,12 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
> }
> }
>
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
>
> void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> int i;
> uint64_t src = a2;
>
> @@ -842,7 +844,7 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
> }
> }
>
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
>
> void HELPER(stctg)(CPUS390XState *env, uint32_t r1, uint64_t a2, uint32_t r3)
> @@ -935,6 +937,7 @@ uint32_t HELPER(rrbe)(CPUS390XState *env, uint64_t r2)
> /* compare and swap and purge */
> uint32_t HELPER(csp)(CPUS390XState *env, uint32_t r1, uint64_t r2)
> {
> + S390CPU *cpu = s390_env_get_cpu(env);
> uint32_t cc;
> uint32_t o1 = env->regs[r1];
> uint64_t a2 = r2 & ~3ULL;
> @@ -944,7 +947,7 @@ uint32_t HELPER(csp)(CPUS390XState *env, uint32_t r1, uint64_t r2)
> cpu_stl_data(env, a2, env->regs[(r1 + 1) & 15]);
> if (r2 & 0x3) {
> /* flush TLB / ALB */
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
> cc = 0;
> } else {
> @@ -1039,7 +1042,9 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pte_addr, uint64_t vaddr)
> /* flush local tlb */
> void HELPER(ptlb)(CPUS390XState *env)
> {
> - tlb_flush(env, 1);
> + S390CPU *cpu = s390_env_get_cpu(env);
> +
> + tlb_flush(CPU(cpu), 1);
> }
>
> /* store using real address */
> diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
> index fb176bf..05720f1 100644
> --- a/target-sh4/cpu.c
> +++ b/target-sh4/cpu.c
> @@ -77,7 +77,7 @@ static void superh_cpu_reset(CPUState *s)
> scc->parent_reset(s);
>
> memset(env, 0, offsetof(CPUSH4State, id));
> - tlb_flush(env, 1);
> + tlb_flush(s, 1);
>
> env->pc = 0xA0000000;
> #if defined(CONFIG_USER_ONLY)
> diff --git a/target-sh4/helper.c b/target-sh4/helper.c
> index c56e543..9ebdd5c 100644
> --- a/target-sh4/helper.c
> +++ b/target-sh4/helper.c
> @@ -585,7 +585,7 @@ void cpu_load_tlb(CPUSH4State * env)
> entry->v = 0;
> }
>
> - tlb_flush(s, 1);
> + tlb_flush(CPU(sh_env_get_cpu(s)), 1);
> }
>
> uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State *s,
> diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c
> index 6c1ff68..e1f6e61 100644
> --- a/target-sparc/cpu.c
> +++ b/target-sparc/cpu.c
> @@ -33,7 +33,7 @@ static void sparc_cpu_reset(CPUState *s)
> scc->parent_reset(s);
>
> memset(env, 0, offsetof(CPUSPARCState, version));
> - tlb_flush(env, 1);
> + tlb_flush(s, 1);
> env->cwp = 0;
> #ifndef TARGET_SPARC64
> env->wim = 1;
> diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c
> index 44c54f1..bf75ceb 100644
> --- a/target-sparc/ldst_helper.c
> +++ b/target-sparc/ldst_helper.c
> @@ -865,7 +865,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
> case 2: /* flush region (16M) */
> case 3: /* flush context (4G) */
> case 4: /* flush entire */
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> break;
> default:
> break;
> @@ -890,7 +890,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
> disabled mode are invalid in normal mode */
> if ((oldreg & (MMU_E | MMU_NF | env->def->mmu_bm)) !=
> (env->mmuregs[reg] & (MMU_E | MMU_NF | env->def->mmu_bm))) {
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
> break;
> case 1: /* Context Table Pointer Register */
> @@ -901,7 +901,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, int asi,
> if (oldreg != env->mmuregs[reg]) {
> /* we flush when the MMU context changes because
> QEMU has no MMU context support */
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
> break;
> case 3: /* Synchronous Fault Status Register with Clear */
> @@ -1657,6 +1657,8 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, int asi, int size,
> void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
> int asi, int size)
> {
> + SPARCCPU *cpu = sparc_env_get_cpu(env);
> +
> #ifdef DEBUG_ASI
> dump_asi("write", addr, asi, size, val);
> #endif
> @@ -1865,7 +1867,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
> #ifdef DEBUG_MMU
> dump_mmu(stdout, fprintf, env);
> #endif
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
> return;
> }
> @@ -1954,13 +1956,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
> env->dmmu.mmu_primary_context = val;
> /* can be optimized to only flush MMU_USER_IDX
> and MMU_KERNEL_IDX entries */
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> break;
> case 2: /* Secondary context */
> env->dmmu.mmu_secondary_context = val;
> /* can be optimized to only flush MMU_USER_SECONDARY_IDX
> and MMU_KERNEL_SECONDARY_IDX entries */
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> break;
> case 5: /* TSB access */
> DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
> @@ -2389,7 +2391,7 @@ void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
> /* flush neverland mappings created during no-fault mode,
> so the sequential MMU faults report proper fault types */
> if (env->mmuregs[0] & MMU_NF) {
> - tlb_flush(env, 1);
> + tlb_flush(cs, 1);
> }
> }
> #else
> diff --git a/target-sparc/machine.c b/target-sparc/machine.c
> index a353dab..3f3de4c 100644
> --- a/target-sparc/machine.c
> +++ b/target-sparc/machine.c
> @@ -112,6 +112,7 @@ void cpu_save(QEMUFile *f, void *opaque)
> int cpu_load(QEMUFile *f, void *opaque, int version_id)
> {
> CPUSPARCState *env = opaque;
> + SPARCCPU *cpu = sparc_env_get_cpu(env);
> int i;
> uint32_t tmp;
>
> @@ -212,6 +213,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
> qemu_get_be64s(f, &env->ssr);
> cpu_get_timer(f, env->hstick);
> #endif
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> return 0;
> }
> diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
> index dcf3b16..a317217 100644
> --- a/target-unicore32/cpu.c
> +++ b/target-unicore32/cpu.c
> @@ -141,7 +141,7 @@ static void uc32_cpu_initfn(Object *obj)
> env->regs[31] = 0x03000000;
> #endif
>
> - tlb_flush(env, 1);
> + tlb_flush(cs, 1);
>
> if (tcg_enabled() && !inited) {
> inited = true;
> diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
> index f91ed93..8de6a33 100644
> --- a/target-unicore32/helper.c
> +++ b/target-unicore32/helper.c
> @@ -57,6 +57,8 @@ uint32_t HELPER(clz)(uint32_t x)
> void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
> uint32_t cop)
> {
> + UniCore32CPU *cpu = uc32_env_get_cpu(env);
> +
> /*
> * movc pp.nn, rn, #imm9
> * rn: UCOP_REG_D
> @@ -125,7 +127,7 @@ void helper_cp0_set(CPUUniCore32State *env, uint32_t val, uint32_t creg,
> case 6:
> if ((cop <= 6) && (cop >= 2)) {
> /* invalid all tlb */
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> return;
> }
> break;
> diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c
> index 5771841..70937b6 100644
> --- a/target-xtensa/op_helper.c
> +++ b/target-xtensa/op_helper.c
> @@ -479,10 +479,12 @@ void HELPER(check_atomctl)(CPUXtensaState *env, uint32_t pc, uint32_t vaddr)
>
> void HELPER(wsr_rasid)(CPUXtensaState *env, uint32_t v)
> {
> + XtensaCPU *cpu = xtensa_env_get_cpu(env);
> +
> v = (v & 0xffffff00) | 0x1;
> if (v != env->sregs[RASID]) {
> env->sregs[RASID] = v;
> - tlb_flush(env, 1);
> + tlb_flush(CPU(cpu), 1);
> }
> }
target-openrisc: Tested-by: Jia Liu <proljc@gmail.com>
>
> --
> 1.8.1.4
>
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] [RFC qom-cpu 41/41] user-exec: Change exception_action() argument to CPUState
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (39 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 40/41] cputlb: Change tlb_flush() " Andreas Färber
@ 2013-09-04 9:05 ` Andreas Färber
2013-09-09 16:39 ` [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Michael Walle
` (2 subsequent siblings)
43 siblings, 0 replies; 68+ messages in thread
From: Andreas Färber @ 2013-09-04 9:05 UTC (permalink / raw)
To: qemu-devel; +Cc: Andreas Färber
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
user-exec.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/user-exec.c b/user-exec.c
index 3b795c1..bc58056 100644
--- a/user-exec.c
+++ b/user-exec.c
@@ -38,11 +38,12 @@
//#define DEBUG_SIGNAL
-static void exception_action(CPUArchState *env1)
+static void exception_action(CPUState *cpu)
{
- CPUState *cpu = ENV_GET_CPU(env1);
-
#if defined(TARGET_I386)
+ X86CPU *x86_cpu = X86_CPU(cpu);
+ CPUX86State *env1 = &x86_cpu->env;
+
raise_exception_err(env1, cpu->exception_index, env1->error_code);
#else
cpu_loop_exit(cpu);
@@ -86,7 +87,6 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
{
CPUState *cpu;
CPUClass *cc;
- CPUArchState *env;
int ret;
#if defined(DEBUG_SIGNAL)
@@ -105,7 +105,6 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
cpu = current_cpu;
cc = CPU_GET_CLASS(cpu);
- env = cpu->env_ptr;
/* see if it is an MMU fault */
g_assert(cc->handle_mmu_fault);
ret = cc->handle_mmu_fault(cpu, address, is_write, MMU_USER_IDX);
@@ -121,7 +120,7 @@ static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
/* we restore the process signal mask as the sigreturn should
do it (XXX: use sigsetjmp) */
sigprocmask(SIG_SETMASK, old_set, NULL);
- exception_action(env);
+ exception_action(cpu);
/* never comes here */
return 1;
--
1.8.1.4
^ permalink raw reply related [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (40 preceding siblings ...)
2013-09-04 9:05 ` [Qemu-devel] [RFC qom-cpu 41/41] user-exec: Change exception_action() " Andreas Färber
@ 2013-09-09 16:39 ` Michael Walle
2013-09-09 16:47 ` Peter Maydell
2013-09-17 17:32 ` [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Michael Walle
2014-02-07 17:43 ` Michael Walle
43 siblings, 1 reply; 68+ messages in thread
From: Michael Walle @ 2013-09-09 16:39 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Peter Crosthwaite, Eduardo Habkost, Riku Voipio,
qemu-devel, Alexander Graf, Blue Swirl, Li Guang, Anthony Liguori,
Igor Mammedov, Edgar E. Iglesias, Aurélien Jarno,
Richard Henderson
Hi,
Am 2013-09-04 11:04, schrieb Andreas Färber:
> On part 11, rth said for alpha that using CPUAlphaState in
> DisasContext was bad
> and that the relevant fields should be copied into DisasContext
> instead; a few
> targets still have an env field though and use it for register access
> and
> cpu_abort(), so I have just changed the type for now and call upon
> maintainers
> to review whether they want to do different changes.
Is there a preferred way to abort translation, if for example, the
translator finds an unknown opcode? I guess there should be some kind of
exception. But speaking of lm32, the real CPU, does not handle such a
situation, instead the behavior is just undefined. Also, the emulation
is mainly used for developing, not for hosting applications with
security in mind.
For the lm32 target, i would copy the required fields (only information
about the chosen cpu model) into the DisasContext as suggested. But then
i will still need the CPUState for the cpu_abort() call.
--
michael
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON
2013-09-09 16:39 ` [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Michael Walle
@ 2013-09-09 16:47 ` Peter Maydell
2013-09-17 17:46 ` Michael Walle
0 siblings, 1 reply; 68+ messages in thread
From: Peter Maydell @ 2013-09-09 16:47 UTC (permalink / raw)
To: Michael Walle
Cc: Peter Crosthwaite, Eduardo Habkost, Riku Voipio, QEMU Developers,
Alexander Graf, Blue Swirl, Li Guang, Anthony Liguori,
Igor Mammedov, Edgar E. Iglesias, Andreas Färber,
Aurélien Jarno, Richard Henderson
On 9 September 2013 17:39, Michael Walle <michael@walle.cc> wrote:
> Am 2013-09-04 11:04, schrieb Andreas Färber:
>> On part 11, rth said for alpha that using CPUAlphaState in
>> DisasContext was bad
>> and that the relevant fields should be copied into DisasContext
>> instead; a few
>> targets still have an env field though and use it for register access and
>> cpu_abort(), so I have just changed the type for now and call upon
>> maintainers
>> to review whether they want to do different changes.
>
>
> Is there a preferred way to abort translation, if for example, the
> translator finds an unknown opcode? I guess there should be some kind of
> exception. But speaking of lm32, the real CPU, does not handle such a
> situation, instead the behavior is just undefined.
If for the real CPU it's genuinely undefined we can do
what we like, but killing QEMU is probably a bit harsh.
If the CPU supports some kind of plausible exception
then we can use it. Otherwise translate as no-op, maybe.
In either case doing a qemu_log_mask(LOG_GUEST_ERROR, ...)
would be a good plan.
For lm32 you might consider raising EXCP_BREAKPOINT;
then if you have a gdb connected to the debug stub
the developer will get dropped into the debugger for
the offending insn and can look at it.
-- PMM
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON
2013-09-09 16:47 ` Peter Maydell
@ 2013-09-17 17:46 ` Michael Walle
2013-09-17 18:46 ` Richard Henderson
0 siblings, 1 reply; 68+ messages in thread
From: Michael Walle @ 2013-09-17 17:46 UTC (permalink / raw)
To: Peter Maydell
Cc: Peter Crosthwaite, Eduardo Habkost, Riku Voipio, QEMU Developers,
Alexander Graf, Blue Swirl, Li Guang, Anthony Liguori,
Igor Mammedov, Edgar E. Iglesias, Andreas Färber,
Aurélien Jarno, Richard Henderson
Am Montag, 9. September 2013, 18:47:21 schrieb Peter Maydell:
> On 9 September 2013 17:39, Michael Walle <michael@walle.cc> wrote:
> > Am 2013-09-04 11:04, schrieb Andreas Färber:
> >> On part 11, rth said for alpha that using CPUAlphaState in
> >> DisasContext was bad
> >> and that the relevant fields should be copied into DisasContext
> >> instead; a few
> >> targets still have an env field though and use it for register access
> >> and cpu_abort(), so I have just changed the type for now and call upon
> >> maintainers
> >> to review whether they want to do different changes.
> >
> > Is there a preferred way to abort translation, if for example, the
> > translator finds an unknown opcode? I guess there should be some kind of
> > exception. But speaking of lm32, the real CPU, does not handle such a
> > situation, instead the behavior is just undefined.
>
> If for the real CPU it's genuinely undefined we can do
> what we like, but killing QEMU is probably a bit harsh.
> If the CPU supports some kind of plausible exception
> then we can use it. Otherwise translate as no-op, maybe.
> In either case doing a qemu_log_mask(LOG_GUEST_ERROR, ...)
> would be a good plan.
Ok. i already have a patch which does this.
> For lm32 you might consider raising EXCP_BREAKPOINT;
> then if you have a gdb connected to the debug stub
> the developer will get dropped into the debugger for
> the offending insn and can look at it.
Are you sure, this will drop to the debugger? I guess the target cpu jumps to
the exception vector.
I must admit, i'm not very familiar with the gdbstub and exception handling.
--
michael
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON
2013-09-17 17:46 ` Michael Walle
@ 2013-09-17 18:46 ` Richard Henderson
2013-09-17 21:26 ` Peter Maydell
2013-09-20 17:07 ` [Qemu-devel] Stopping the VM due to an illegal instruction [was: QOM CPUState, part 13: Emptying CPU_COMMON] Michael Walle
0 siblings, 2 replies; 68+ messages in thread
From: Richard Henderson @ 2013-09-17 18:46 UTC (permalink / raw)
To: Michael Walle
Cc: Peter Maydell, Peter Crosthwaite, Eduardo Habkost, Riku Voipio,
QEMU Developers, Alexander Graf, Blue Swirl, Li Guang,
Anthony Liguori, Igor Mammedov, Edgar E. Iglesias,
Andreas Färber, Aurélien Jarno
On 09/17/2013 10:46 AM, Michael Walle wrote:
> Am Montag, 9. September 2013, 18:47:21 schrieb Peter Maydell:
>> For lm32 you might consider raising EXCP_BREAKPOINT;
>> then if you have a gdb connected to the debug stub
>> the developer will get dropped into the debugger for
>> the offending insn and can look at it.
>
> Are you sure, this will drop to the debugger? I guess the target cpu jumps to
> the exception vector.
He meant EXCP_DEBUG, I think.
It will never affect the target cpu at all, of course, that would be useless
for debugging. Issuing it will exit the cpu loop.
If the debugger is attached, all of the expected things should happen.
Otherwise, it appears as if we'll still have set cpu->stopped, and
we'll fail to run anymore instructions. Even without the debugger
you ought to be able to poke around with the monitor to see what's
going on.
r~
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON
2013-09-17 18:46 ` Richard Henderson
@ 2013-09-17 21:26 ` Peter Maydell
2013-09-20 17:07 ` [Qemu-devel] Stopping the VM due to an illegal instruction [was: QOM CPUState, part 13: Emptying CPU_COMMON] Michael Walle
1 sibling, 0 replies; 68+ messages in thread
From: Peter Maydell @ 2013-09-17 21:26 UTC (permalink / raw)
To: Richard Henderson
Cc: Peter Crosthwaite, Eduardo Habkost, Riku Voipio, QEMU Developers,
Alexander Graf, Blue Swirl, Michael Walle, Li Guang,
Anthony Liguori, Igor Mammedov, Edgar E. Iglesias,
Andreas Färber, Aurélien Jarno
On 17 September 2013 19:46, Richard Henderson <rth@twiddle.net> wrote:
> On 09/17/2013 10:46 AM, Michael Walle wrote:
>> Am Montag, 9. September 2013, 18:47:21 schrieb Peter Maydell:
>>> For lm32 you might consider raising EXCP_BREAKPOINT;
>>> then if you have a gdb connected to the debug stub
>>> the developer will get dropped into the debugger for
>>> the offending insn and can look at it.
>>
>> Are you sure, this will drop to the debugger? I guess the target cpu jumps to
>> the exception vector.
>
> He meant EXCP_DEBUG, I think.
I meant "treat it as if it were an explicit 'breakpoint' instruction".
-- PMM
^ permalink raw reply [flat|nested] 68+ messages in thread
* [Qemu-devel] Stopping the VM due to an illegal instruction [was: QOM CPUState, part 13: Emptying CPU_COMMON]
2013-09-17 18:46 ` Richard Henderson
2013-09-17 21:26 ` Peter Maydell
@ 2013-09-20 17:07 ` Michael Walle
1 sibling, 0 replies; 68+ messages in thread
From: Michael Walle @ 2013-09-20 17:07 UTC (permalink / raw)
To: Richard Henderson
Cc: Peter Maydell, Peter Crosthwaite, Eduardo Habkost, Riku Voipio,
QEMU Developers, Alexander Graf, Blue Swirl, Li Guang,
Anthony Liguori, Igor Mammedov, Edgar E. Iglesias,
Andreas Färber, Aurélien Jarno
Hi,
Am 2013-09-17 20:46, schrieb Richard Henderson:
> On 09/17/2013 10:46 AM, Michael Walle wrote:
>> Am Montag, 9. September 2013, 18:47:21 schrieb Peter Maydell:
>>> For lm32 you might consider raising EXCP_BREAKPOINT;
>>> then if you have a gdb connected to the debug stub
>>> the developer will get dropped into the debugger for
>>> the offending insn and can look at it.
>>
>> Are you sure, this will drop to the debugger? I guess the target cpu
>> jumps to
>> the exception vector.
>
> He meant EXCP_DEBUG, I think.
>
> It will never affect the target cpu at all, of course, that would be
> useless
> for debugging. Issuing it will exit the cpu loop.
>
> If the debugger is attached, all of the expected things should
> happen.
>
> Otherwise, it appears as if we'll still have set cpu->stopped, and
> we'll fail to run anymore instructions. Even without the debugger
> you ought to be able to poke around with the monitor to see what's
> going on.
Raising EXCP_DEBUG results in a segmentation fault if qemu is not
started with the -s option, because there is not gdbserver_state:
[Switching to Thread 0xb4b2eb70 (LWP 20930)]
0x081c88fa in gdb_set_stop_cpu (cpu=0x8730f88) at
/home/mw/repo/qemu/gdbstub.c:1187
1187 gdbserver_state->c_cpu = cpu;
(gdb) bt
#0 0x081c88fa in gdb_set_stop_cpu (cpu=0x8730f88) at
/home/mw/repo/qemu/gdbstub.c:1187
#1 0x081995f2 in cpu_handle_guest_debug (cpu=0x8730f88)
at /home/mw/repo/qemu/cpus.c:485
#2 0x0819ad7f in tcg_exec_all () at /home/mw/repo/qemu/cpus.c:1218
#3 0x0819a283 in qemu_tcg_cpu_thread_fn (arg=0x8730f88)
at /home/mw/repo/qemu/cpus.c:882
#4 0xb7dd7c39 in start_thread () from
/lib/i386-linux-gnu/i686/cmov/libpthread.so.0
#5 0xb7d4478e in clone () from /lib/i386-linux-gnu/i686/cmov/libc.so.6
(gdb) p gdbserver_state
$1 = (GDBState *) 0x0
(gdb)
I then tried to raise EXCP_HALTED and setting cs->stopped and the
runstate manually:
void HELPER(ill)(CPULM32State *env)
{
#ifndef CONFIG_USER_ONLY
CPUState *cs = CPU(lm32_env_get_cpu(env));
fprintf(stderr, "VM paused due to illegal instruction. "
"Connect a debugger or switch to the monitor console "
"to find out more.\n");
qemu_system_vmstop_request(RUN_STATE_PAUSED);
cs->stopped = true;
raise_exception(env, EXCP_HALTED);
#endif
}
The above works as expected, but i don't know if that is the right way
to do it.
btw, what is the difference between cs->stopped and cs->halted?
--
michael
^ permalink raw reply [flat|nested] 68+ messages in thread
* Re: [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (41 preceding siblings ...)
2013-09-09 16:39 ` [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Michael Walle
@ 2013-09-17 17:32 ` Michael Walle
2014-02-07 17:43 ` Michael Walle
43 siblings, 0 replies; 68+ messages in thread
From: Michael Walle @ 2013-09-17 17:32 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
Hi Andreas,
Am Mittwoch, 4. September 2013, 11:04:40 schrieb Andreas Färber:
> On part 11, rth said for alpha that using CPUAlphaState in DisasContext was
> bad and that the relevant fields should be copied into DisasContext
> instead; a few targets still have an env field though and use it for
> register access and cpu_abort(), so I have just changed the type for now
> and call upon maintainers to review whether they want to do different
> changes.
Just fyi, I'm currently working on removing the env pointer in the
DisasContext for target-lm32 altogether.
Hopefully, i can post the patch (along with some other target-lm32 fixes) this
weekend.
--
michael
^ permalink raw reply [flat|nested] 68+ messages in thread* Re: [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON
2013-09-04 9:04 [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Andreas Färber
` (42 preceding siblings ...)
2013-09-17 17:32 ` [Qemu-devel] [RFC qom-cpu 00/41] QOM CPUState, part 13: Emptying CPU_COMMON Michael Walle
@ 2014-02-07 17:43 ` Michael Walle
43 siblings, 0 replies; 68+ messages in thread
From: Michael Walle @ 2014-02-07 17:43 UTC (permalink / raw)
To: Andreas Färber
Cc: Peter Maydell, Peter Crosthwaite, Eduardo Habkost, Riku Voipio,
qemu-devel, Alexander Graf, Blue Swirl, Li Guang, Anthony Liguori,
Igor Mammedov, Edgar E. Iglesias, Aurélien Jarno,
Richard Henderson
Am 2013-09-04 11:04, schrieb Andreas Färber:
> On part 11, rth said for alpha that using CPUAlphaState in DisasContext
> was bad
> and that the relevant fields should be copied into DisasContext
> instead; a few
> targets still have an env field though and use it for register access
> and
> cpu_abort(), so I have just changed the type for now and call upon
> maintainers
> to review whether they want to do different changes.
Hi Andreas,
For the lm32 target, there are two patches, which also addresses this:
http://patchwork.ozlabs.org/patch/316740/
http://patchwork.ozlabs.org/patch/316725/
waiting to be merged.
-michael
^ permalink raw reply [flat|nested] 68+ messages in thread