From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48122) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VPU5T-0007PV-Mt for qemu-devel@nongnu.org; Fri, 27 Sep 2013 05:11:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VPU5N-0003wY-MY for qemu-devel@nongnu.org; Fri, 27 Sep 2013 05:11:47 -0400 Received: from mail-ea0-f172.google.com ([209.85.215.172]:40199) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VPU5N-0003sS-5b for qemu-devel@nongnu.org; Fri, 27 Sep 2013 05:11:41 -0400 Received: by mail-ea0-f172.google.com with SMTP id r16so1083601ead.17 for ; Fri, 27 Sep 2013 02:11:39 -0700 (PDT) Message-ID: <52454BDF.7020800@linaro.org> Date: Fri, 27 Sep 2013 11:11:59 +0200 From: Claudio Fontana MIME-Version: 1.0 References: <1380242934-20953-1-git-send-email-agraf@suse.de> <1380242934-20953-10-git-send-email-agraf@suse.de> In-Reply-To: <1380242934-20953-10-git-send-email-agraf@suse.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 09/60] AArch64: Add b and bl handling List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: Peter Maydell , Michael Matz , qemu-devel@nongnu.org, Dirk Mueller , Laurent Desnogues , Christoffer Dall , Richard Henderson Hi Alex, On 09/27/13 02:48, Alexander Graf wrote: > This adds handling for the b and bl instructions. > > Signed-off-by: Alexander Graf > --- > target-arm/translate-a64.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 61 insertions(+) > > diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c > index 73ccade..267fd4d 100644 > --- a/target-arm/translate-a64.c > +++ b/target-arm/translate-a64.c > @@ -133,6 +133,58 @@ static void real_unallocated_encoding(DisasContext *s) > real_unallocated_encoding(s); \ > } while (0) > > +static int get_bits(uint32_t inst, int start, int len) > +{ > + return (inst >> start) & ((1 << len) - 1); > +} > + do you think it makes sense to reuse extract32 from bitops here? > +static int get_sbits(uint32_t inst, int start, int len) > +{ > + int r = get_bits(inst, start, len); > + if (r & (1 << (len - 1))) { > + /* Extend the MSB 1 to the higher bits */ > + r |= -1 & ~((1ULL << len) - 1); > + } > + return r; > +} > + sextract32? > +static TCGv_i64 cpu_reg(int reg) > +{ > + if (reg == 31) { > + /* XXX leaks temps */ > + return tcg_const_i64(0); ... > + } else { > + return cpu_X[reg]; > + } > +} > + > +static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) > +{ > + TranslationBlock *tb; > + > + tb = s->tb; > + if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) { > + tcg_gen_goto_tb(n); > + gen_a64_set_pc_im(dest); > + tcg_gen_exit_tb((tcg_target_long)tb + n); > + } else { > + gen_a64_set_pc_im(dest); > + tcg_gen_exit_tb(0); > + } > +} > + > +static void handle_b(DisasContext *s, uint32_t insn) > +{ > + uint64_t addr = s->pc - 4 + (get_sbits(insn, 0, 26) << 2); > + > + if (get_bits(insn, 31, 1)) { > + /* BL */ > + tcg_gen_movi_i64(cpu_reg(30), s->pc); > + } > + gen_goto_tb(s, 0, addr); > + s->is_jmp = DISAS_TB_JUMP; > +} > + > void disas_a64_insn(CPUARMState *env, DisasContext *s) > { > uint32_t insn; > @@ -141,12 +193,21 @@ void disas_a64_insn(CPUARMState *env, DisasContext *s) > s->insn = insn; > s->pc += 4; > > + /* One-off branch instruction layout */ > + switch (insn >> 26) { > + case 0x25: > + case 0x5: > + handle_b(s, insn); > + goto insn_done; > + } > + > switch ((insn >> 24) & 0x1f) { > default: > unallocated_encoding(s); > break; > } > > +insn_done: > if (unlikely(s->singlestep_enabled) && (s->is_jmp == DISAS_TB_JUMP)) { > /* go through the main loop for single step */ > s->is_jmp = DISAS_JUMP; > Ciao, Claudio