From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com,
Alistair Francis <alistair.francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH v10 06/61] target/riscv: add vector stride load and store instructions
Date: Wed, 24 Jun 2020 05:32:39 +0800 [thread overview]
Message-ID: <52471447-9a3c-b4df-f45c-788e52ea5409@c-sky.com> (raw)
In-Reply-To: <CAKmqyKMN_PMJrwT3HvWryWaaWHhbQZkhO3y-NVk_OyEfgT8H4g@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 12759 bytes --]
On 2020/6/24 0:52, Alistair Francis wrote:
> On Fri, Jun 19, 2020 at 9:49 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>> Vector strided operations access the first memory element at the base address,
>> and then access subsequent elements at address increments given by the byte
>> offset contained in the x register specified by rs2.
>>
>> Vector unit-stride operations access elements stored contiguously in memory
>> starting from the base effective address. It can been seen as a special
>> case of strided operations.
>>
>> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
>> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>> ---
>> target/riscv/helper.h | 105 ++++++
>> target/riscv/insn32.decode | 32 ++
>> target/riscv/insn_trans/trans_rvv.inc.c | 355 ++++++++++++++++++++
>> target/riscv/internals.h | 5 +
>> target/riscv/translate.c | 7 +
>> target/riscv/vector_helper.c | 410 ++++++++++++++++++++++++
>> 6 files changed, 914 insertions(+)
>>
>> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
>> index 8e81ff440b..f03b3d52f5 100644
>> --- a/target/riscv/helper.h
>> +++ b/target/riscv/helper.h
>> @@ -84,3 +84,108 @@ DEF_HELPER_1(hyp_tlb_flush, void, env)
>>
>> /* Vector functions */
>> DEF_HELPER_3(vsetvl, tl, env, tl, tl)
>> +DEF_HELPER_5(vlb_v_b, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlb_v_b_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlb_v_h, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlb_v_h_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlb_v_w, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlb_v_w_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlb_v_d, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlb_v_d_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlh_v_h, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlh_v_h_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlh_v_w, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlh_v_w_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlh_v_d, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlh_v_d_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlw_v_w, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlw_v_w_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlw_v_d, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlw_v_d_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vle_v_b, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vle_v_b_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vle_v_h, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vle_v_h_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vle_v_w, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vle_v_w_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vle_v_d, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vle_v_d_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlbu_v_b, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlbu_v_b_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlbu_v_h, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlbu_v_h_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlbu_v_w, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlbu_v_w_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlbu_v_d, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlbu_v_d_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlhu_v_h, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlhu_v_h_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlhu_v_w, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlhu_v_w_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlhu_v_d, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlhu_v_d_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlwu_v_w, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlwu_v_w_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlwu_v_d, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vlwu_v_d_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vsb_v_b, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vsb_v_b_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vsb_v_h, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vsb_v_h_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vsb_v_w, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vsb_v_w_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vsb_v_d, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vsb_v_d_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vsh_v_h, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vsh_v_h_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vsh_v_w, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vsh_v_w_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vsh_v_d, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vsh_v_d_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vsw_v_w, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vsw_v_w_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vsw_v_d, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vsw_v_d_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vse_v_b, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vse_v_b_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vse_v_h, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vse_v_h_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vse_v_w, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vse_v_w_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vse_v_d, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_5(vse_v_d_mask, void, ptr, ptr, tl, env, i32)
>> +DEF_HELPER_6(vlsb_v_b, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlsb_v_h, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlsb_v_w, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlsb_v_d, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlsh_v_h, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlsh_v_w, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlsh_v_d, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlsw_v_w, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlsw_v_d, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlse_v_b, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlse_v_h, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlse_v_w, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlse_v_d, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlsbu_v_b, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlsbu_v_h, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlsbu_v_w, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlsbu_v_d, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlshu_v_h, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlshu_v_w, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlshu_v_d, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlswu_v_w, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vlswu_v_d, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vssb_v_b, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vssb_v_h, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vssb_v_w, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vssb_v_d, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vssh_v_h, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vssh_v_w, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vssh_v_d, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vssw_v_w, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vssw_v_d, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vsse_v_b, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vsse_v_h, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vsse_v_w, void, ptr, ptr, tl, tl, env, i32)
>> +DEF_HELPER_6(vsse_v_d, void, ptr, ptr, tl, tl, env, i32)
>> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
>> index 1916cf331d..58b95792e6 100644
>> --- a/target/riscv/insn32.decode
>> +++ b/target/riscv/insn32.decode
>> @@ -25,6 +25,7 @@
>> %sh10 20:10
>> %csr 20:12
>> %rm 12:3
>> +%nf 29:3 !function=ex_plus_1
>>
>> # immediates:
>> %imm_i 20:s12
>> @@ -43,6 +44,8 @@
>> &u imm rd
>> &shift shamt rs1 rd
>> &atomic aq rl rs2 rs1 rd
>> +&r2nfvm vm rd rs1 nf
>> +&rnfvm vm rd rs1 rs2 nf
>>
>> # Formats 32:
>> @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
>> @@ -62,6 +65,8 @@
>> @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
>> @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
>> @r2 ....... ..... ..... ... ..... ....... %rs1 %rd
>> +@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
>> +@r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd
>> @r2_zimm . zimm:11 ..... ... ..... ....... %rs1 %rd
>>
>> @hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
>> @@ -212,5 +217,32 @@ hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
>> hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
>>
>> # *** RV32V Extension ***
>> +
>> +# *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
>> +vlb_v ... 100 . 00000 ..... 000 ..... 0000111 @r2_nfvm
>> +vlh_v ... 100 . 00000 ..... 101 ..... 0000111 @r2_nfvm
>> +vlw_v ... 100 . 00000 ..... 110 ..... 0000111 @r2_nfvm
>> +vle_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
>> +vlbu_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
>> +vlhu_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
>> +vlwu_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
>> +vsb_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
>> +vsh_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
>> +vsw_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
>> +vse_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
>> +
>> +vlsb_v ... 110 . ..... ..... 000 ..... 0000111 @r_nfvm
>> +vlsh_v ... 110 . ..... ..... 101 ..... 0000111 @r_nfvm
>> +vlsw_v ... 110 . ..... ..... 110 ..... 0000111 @r_nfvm
>> +vlse_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
>> +vlsbu_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
>> +vlshu_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
>> +vlswu_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
>> +vssb_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
>> +vssh_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
>> +vssw_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
>> +vsse_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
>> +
>> +# *** new major opcode OP-V ***
>> vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
>> vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
>> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
>> index c82fdf013e..f9950ad5a0 100644
>> --- a/target/riscv/insn_trans/trans_rvv.inc.c
>> +++ b/target/riscv/insn_trans/trans_rvv.inc.c
>> @@ -15,6 +15,9 @@
>> * You should have received a copy of the GNU General Public License along with
>> * this program. If not, see <http://www.gnu.org/licenses/>.
>> */
>> +#include "tcg/tcg-op-gvec.h"
>> +#include "tcg/tcg-gvec-desc.h"
>> +#include "internals.h"
>>
>> static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
>> {
>> @@ -77,3 +80,355 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
>> tcg_temp_free(dst);
>> return true;
>> }
>> +
>> +/* vector register offset from env */
>> +static uint32_t vreg_ofs(DisasContext *s, int reg)
>> +{
>> + return offsetof(CPURISCVState, vreg) + reg * s->vlen / 8;
>> +}
>> +
>> +/* check functions */
>> +
>> +/*
>> + * In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
>> + * So RVV is also be checked in this function.
>> + */
>> +static bool vext_check_isa_ill(DisasContext *s)
>> +{
>> + return !s->vill;
>> +}
>> +
>> +/*
>> + * There are two rules check here.
>> + *
>> + * 1. Vector register numbers are multiples of LMUL. (Section 3.2)
>> + *
>> + * 2. For all widening instructions, the destination LMUL value must also be
>> + * a supported LMUL value. (Section 11.2）
> There is some strange UTF encoding on this line according to
> checkpatch. Do you mind running checkpatch on the patches and fix any
> issues?
Hi Alistair,
Yes, it's a non-ASCII character here and in comments.
I once used the checkpatch.pl to check the whole patch set, but it can't
detect the encoding problems.
If I use a "--8bit-encoding" option in the git send-email, it will
encodes the non-ASCII in UTF-8. So that you can git am the email.
But I will try to find and fix all the non-ASCII characters.
Zhiwei
> checkpatch seems to have some false positives (it confusing pointer *
> and multiply *) they don't need to be fixed.
>
> Alistair
>
>
[-- Attachment #2: Type: text/html, Size: 13819 bytes --]
next prev parent reply other threads:[~2020-06-23 21:34 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-20 4:36 [PATCH v10 00/61] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 01/61] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 02/61] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 03/61] target/riscv: support vector extension csr LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 04/61] target/riscv: add vector configure instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 05/61] target/riscv: add an internals.h header LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 06/61] target/riscv: add vector stride load and store instructions LIU Zhiwei
2020-06-23 16:52 ` Alistair Francis
2020-06-23 21:32 ` LIU Zhiwei [this message]
2020-06-20 4:36 ` [PATCH v10 07/61] target/riscv: add vector index " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 08/61] target/riscv: add fault-only-first unit stride load LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 09/61] target/riscv: add vector amo operations LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 10/61] target/riscv: vector single-width integer add and subtract LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 11/61] target/riscv: vector widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 13/61] target/riscv: vector bitwise logical instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 14/61] target/riscv: vector single-width bit shift instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 15/61] target/riscv: vector narrowing integer right " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 16/61] target/riscv: vector integer comparison instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 17/61] target/riscv: vector integer min/max instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 18/61] target/riscv: vector single-width integer multiply instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 19/61] target/riscv: vector integer divide instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 20/61] target/riscv: vector widening integer multiply instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 21/61] target/riscv: vector single-width integer multiply-add instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 22/61] target/riscv: vector widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 23/61] target/riscv: vector integer merge and move instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 24/61] target/riscv: vector single-width saturating add and subtract LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 25/61] target/riscv: vector single-width averaging " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 27/61] target/riscv: vector widening saturating scaled multiply-add LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 28/61] target/riscv: vector single-width scaling shift instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 29/61] target/riscv: vector narrowing fixed-point clip instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 30/61] target/riscv: vector single-width floating-point add/subtract instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 31/61] target/riscv: vector widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 32/61] target/riscv: vector single-width floating-point multiply/divide instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 33/61] target/riscv: vector widening floating-point multiply LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 35/61] target/riscv: vector widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 36/61] target/riscv: vector floating-point square-root instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 37/61] target/riscv: vector floating-point min/max instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 38/61] target/riscv: vector floating-point sign-injection instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 39/61] target/riscv: vector floating-point compare instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 40/61] target/riscv: vector floating-point classify instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 41/61] target/riscv: vector floating-point merge instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 42/61] target/riscv: vector floating-point/integer type-convert instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 43/61] target/riscv: widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 44/61] target/riscv: narrowing " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 45/61] target/riscv: vector single-width integer reduction instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 46/61] target/riscv: vector wideing " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 47/61] target/riscv: vector single-width floating-point " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 48/61] target/riscv: vector widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 49/61] target/riscv: vector mask-register logical instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 50/61] target/riscv: vector mask population count vmpopc LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 51/61] target/riscv: vmfirst find-first-set mask bit LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 52/61] target/riscv: set-X-first " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 53/61] target/riscv: vector iota instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 54/61] target/riscv: vector element index instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 55/61] target/riscv: integer extract instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 56/61] target/riscv: integer scalar move instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 57/61] target/riscv: floating-point scalar move instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 58/61] target/riscv: vector slide instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 59/61] target/riscv: vector register gather instruction LIU Zhiwei
2020-06-20 4:37 ` [PATCH v10 60/61] target/riscv: vector compress instruction LIU Zhiwei
2020-06-20 4:37 ` [PATCH v10 61/61] target/riscv: configure and turn on vector extension from command line LIU Zhiwei
-- strict thread matches above, loose matches on Subject: below --
2020-06-20 2:54 [PATCH v10 00/61] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-06-20 2:54 ` [PATCH v10 06/61] target/riscv: add vector stride load and store instructions LIU Zhiwei
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=52471447-9a3c-b4df-f45c-788e52ea5409@c-sky.com \
--to=zhiwei_liu@c-sky.com \
--cc=alistair.francis@wdc.com \
--cc=alistair23@gmail.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=wenmeng_zhang@c-sky.com \
--cc=wxy194768@alibaba-inc.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).