From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54717) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VT7o4-0000S5-9C for qemu-devel@nongnu.org; Mon, 07 Oct 2013 06:12:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VT7ny-0005kf-A9 for qemu-devel@nongnu.org; Mon, 07 Oct 2013 06:12:52 -0400 Received: from mel.act-europe.fr ([194.98.77.210]:48816 helo=smtp.eu.adacore.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VT7ny-0005kZ-3s for qemu-devel@nongnu.org; Mon, 07 Oct 2013 06:12:46 -0400 Message-ID: <5252891D.7050200@adacore.com> Date: Mon, 07 Oct 2013 12:12:45 +0200 From: Fabien Chouteau MIME-Version: 1.0 References: <1380905823-3981-1-git-send-email-chouteau@adacore.com> <1380905823-3981-5-git-send-email-chouteau@adacore.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 4/4] Add ARM registers definitions for Monitor commands List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: QEMU Developers , =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= , Luiz Capitulino On 10/04/2013 07:52 PM, Peter Maydell wrote: >> +#include "monitor/monitor_def.h" >> + >> +const MonitorDef arm_monitor_defs[] = { >> + { "r0", offsetof(CPUARMState, regs[0]) }, >> + { "r1", offsetof(CPUARMState, regs[1]) }, > > These fields are all 32 bits, not target_long, > so they need to be marked as MD_I32. (If you build an > aarch64-softmmu target then it will have target_long be > 64 bit but still support all the 32 bit CPUs, so it does > make a difference.) > OK, I'll mark them MD_I32. -- Fabien Chouteau