From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49834) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VU0EM-0000g3-0L for qemu-devel@nongnu.org; Wed, 09 Oct 2013 16:19:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VU0EL-0004TY-5B for qemu-devel@nongnu.org; Wed, 09 Oct 2013 16:19:37 -0400 Sender: Richard Henderson Message-ID: <5255BA43.4080605@twiddle.net> Date: Wed, 09 Oct 2013 13:19:15 -0700 From: Richard Henderson MIME-Version: 1.0 References: <524EBE04.8050207@gmail.com> <524EC1ED.3040201@gmail.com> In-Reply-To: <524EC1ED.3040201@gmail.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 12/13] Add xxspltw List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Tom Musta Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org On 10/04/2013 06:26 AM, Tom Musta wrote: > + case 0: { > + tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode))); > + tcg_gen_andi_i64(b, b, 0xFFFFFFFF00000000ul); > + tcg_gen_shri_i64(b, b, 32); > + break; ... > + case 2: { > + tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode))); > + tcg_gen_andi_i64(b, b, 0xFFFFFFFF00000000ul); > + tcg_gen_shri_i64(b, b, 32); > + break; No need for the and. Perhaps better as TCGv_i64 vsr = (uim & 2 ? cpu_vrsl(xb) : cpu_vrsh(xb)); if (uim & 1) { tcg_gen_ext32u_i64(b, vsr); } else { tcg_gen_shri_i32(b, vsr, 32); } > + tcg_gen_shli_i64(b2, b, 32); > + tcg_gen_or_i64(b, b, b2); deposit. r~