[Qemu-devel] [PATCH_v2 0/9] target-openrisc: Corrections and speed improvements

[Qemu-devel] [PATCH_v2 0/9] target-openrisc: Corrections and speed improvements

[Sebastian Macke]

This series is the first part to make the OpenRISC target more
reliable and faster.
It corrects several severe problems which prevented the OpenRISC emulation
for being useful in the past.

The patchset was tested with
  - the tests/tcg/openrisc tests 
  - booting Linux 3.11
  - run configure + make + gcc of a simple terminal graphic demo called cmatrix
  - run benchmark tool nbench in qemu-user mode and in the softmmu mode

The speed improvement is less than 10% because the overhead is still to high
as the openrisc target does not support translation block chaining.
This will be included in one of the future patches.

Only the patch which removes the npc and ppc variables removes a little feature 
from the OpenRISC target but which does not break the specification and will lead to 
a significant speed improvement.


Sebastian Macke (9):
  target-openrisc: Speed up move instruction
  target-openrisc: Remove unnecessary code generated by jump
    instructions
  target-openrisc: Remove executable flag for every page
  target-openrisc: Correct wrong epcr register in interrupt handler
  openrisc-timer: Reduce overhead, Separate clock update functions
  target-openrisc: Correct memory bounds checking for the tlb buffers
  target-openrisc: Separate branch flag from Supervision register
  target-openrisc: Complete remove of npc and ppc variables
  target-openrisc: Correct carry flag check of l.addc and l.addic test
    cases

 hw/openrisc/cputimer.c             |  29 ++++--
 target-openrisc/cpu.c              |   1 +
 target-openrisc/cpu.h              |  16 ++-
 target-openrisc/gdbstub.c          |  20 +---
 target-openrisc/interrupt.c        |  27 ++---
 target-openrisc/interrupt_helper.c |   3 +-
 target-openrisc/machine.c          |   3 +-
 target-openrisc/mmu.c              |   4 +-
 target-openrisc/sys_helper.c       |  74 ++++++--------
 target-openrisc/translate.c        | 201 ++++++++++++++++---------------------
 tests/tcg/openrisc/test_addc.c     |   8 +-
 tests/tcg/openrisc/test_addic.c    |  10 +-
 12 files changed, 175 insertions(+), 221 deletions(-)

-- 
1.8.4.1

[Qemu-devel] [PATCH_v2 1/9] target-openrisc: Speed up move instruction

[Sebastian Macke]

The OpenRISC architecture does not have its own move register
instruction. Instead it uses either "l.addi rd, r0, x" or
"l.ori rd, rs, 0" or "l.or rd, rx, r0"

The l.ori instruction is automatically optimized but not the l.addi instruction.
This patch optimizes for this special case.

Signed-off-by: Sebastian Macke <sebastian@macke.de>
---
 target-openrisc/translate.c | 50 ++++++++++++++++++++++++---------------------
 1 file changed, 27 insertions(+), 23 deletions(-)

diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 8908a2e..8276ce7 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -904,29 +904,33 @@ static void dec_misc(DisasContext *dc, uint32_t insn)
     case 0x27:    /* l.addi */
         LOG_DIS("l.addi r%d, r%d, %d\n", rd, ra, I16);
         {
-            int lab = gen_new_label();
-            TCGv_i64 ta = tcg_temp_new_i64();
-            TCGv_i64 td = tcg_temp_local_new_i64();
-            TCGv_i32 res = tcg_temp_local_new_i32();
-            TCGv_i32 sr_ove = tcg_temp_local_new_i32();
-            tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
-            tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
-            tcg_gen_trunc_i64_i32(res, td);
-            tcg_gen_shri_i64(td, td, 32);
-            tcg_gen_andi_i64(td, td, 0x3);
-            /* Jump to lab when no overflow.  */
-            tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
-            tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
-            tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
-            tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
-            tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
-            gen_exception(dc, EXCP_RANGE);
-            gen_set_label(lab);
-            tcg_gen_mov_i32(cpu_R[rd], res);
-            tcg_temp_free_i64(ta);
-            tcg_temp_free_i64(td);
-            tcg_temp_free_i32(res);
-            tcg_temp_free_i32(sr_ove);
+            if (I16 == 0) {
+                tcg_gen_mov_tl(cpu_R[rd], cpu_R[ra]);
+            } else {
+                int lab = gen_new_label();
+                TCGv_i64 ta = tcg_temp_new_i64();
+                TCGv_i64 td = tcg_temp_local_new_i64();
+                TCGv_i32 res = tcg_temp_local_new_i32();
+                TCGv_i32 sr_ove = tcg_temp_local_new_i32();
+                tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
+                tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
+                tcg_gen_trunc_i64_i32(res, td);
+                tcg_gen_shri_i64(td, td, 32);
+                tcg_gen_andi_i64(td, td, 0x3);
+                /* Jump to lab when no overflow.  */
+                tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
+                tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
+                tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
+                tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
+                tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
+                gen_exception(dc, EXCP_RANGE);
+                gen_set_label(lab);
+                tcg_gen_mov_i32(cpu_R[rd], res);
+                tcg_temp_free_i64(ta);
+                tcg_temp_free_i64(td);
+                tcg_temp_free_i32(res);
+                tcg_temp_free_i32(sr_ove);
+            }
         }
         break;
 
-- 
1.8.4.1

[Qemu-devel] [PATCH_v2 2/9] target-openrisc: Remove unnecessary code generated by jump instructions

[Sebastian Macke]

The sr_f variable is only used for the l.bf and l.bnf instructions.
For clarity the code is also rewritten using a switch statement instead
of if chaining.

Signed-off-by: Sebastian Macke <sebastian@macke.de>
---
 target-openrisc/translate.c | 45 ++++++++++++++++++++++++++-------------------
 1 file changed, 26 insertions(+), 19 deletions(-)

diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 8276ce7..91c60eb 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -209,42 +209,49 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
 static void gen_jump(DisasContext *dc, uint32_t imm, uint32_t reg, uint32_t op0)
 {
     target_ulong tmp_pc;
-    int lab = gen_new_label();
-    TCGv sr_f = tcg_temp_new();
     /* N26, 26bits imm */
     tmp_pc = sign_extend((imm<<2), 26) + dc->pc;
-    tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
 
-    if (op0 == 0x00) {    /* l.j */
+    switch (op0) {
+    case 0x00:     /* l.j */
         tcg_gen_movi_tl(jmp_pc, tmp_pc);
-    } else if (op0 == 0x01) {    /* l.jal */
+        break;
+    case 0x01:     /* l.jal */
         tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
         tcg_gen_movi_tl(jmp_pc, tmp_pc);
-    } else if (op0 == 0x03) {    /* l.bnf */
-        tcg_gen_movi_tl(jmp_pc, dc->pc+8);
-        tcg_gen_brcondi_i32(TCG_COND_EQ, sr_f, SR_F, lab);
-        tcg_gen_movi_tl(jmp_pc, tmp_pc);
-        gen_set_label(lab);
-    } else if (op0 == 0x04) {    /* l.bf */
-        tcg_gen_movi_tl(jmp_pc, dc->pc+8);
-        tcg_gen_brcondi_i32(TCG_COND_NE, sr_f, SR_F, lab);
-        tcg_gen_movi_tl(jmp_pc, tmp_pc);
-        gen_set_label(lab);
-    } else if (op0 == 0x11) {    /* l.jr */
+        break;
+    case 0x03:     /* l.bnf */
+    case 0x04:     /* l.bf  */
+        {
+            int lab = gen_new_label();
+            TCGv sr_f = tcg_temp_new();
+            tcg_gen_movi_tl(jmp_pc, dc->pc+8);
+            tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
+            tcg_gen_brcondi_i32(op0 == 0x03 ? TCG_COND_EQ : TCG_COND_NE,
+                                sr_f, SR_F, lab);
+            tcg_gen_movi_tl(jmp_pc, tmp_pc);
+            gen_set_label(lab);
+            tcg_temp_free(sr_f);
+        }
+        break;
+    case 0x11:     /* l.jr */
         tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
-    } else if (op0 == 0x12) {    /* l.jalr */
+        break;
+    case 0x12:     /* l.jalr */
         tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
         tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
-    } else {
+        break;
+    default:
         gen_illegal_exception(dc);
+        break;
     }
 
-    tcg_temp_free(sr_f);
     dc->delayed_branch = 2;
     dc->tb_flags |= D_FLAG;
     gen_sync_flags(dc);
 }
 
+
 static void dec_calc(DisasContext *dc, uint32_t insn)
 {
     uint32_t op0, op1, op2;
-- 
1.8.4.1

[Qemu-devel] [PATCH_v2 3/9] target-openrisc: Remove executable flag for every page

[Sebastian Macke]

Pages should be flagged executable only if the tlb executable flag is
set or the mmu is off.

Signed-off-by: Sebastian Macke <sebastian@macke.de>
---
 target-openrisc/mmu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target-openrisc/mmu.c b/target-openrisc/mmu.c
index 22d7cbe..dd487bd 100644
--- a/target-openrisc/mmu.c
+++ b/target-openrisc/mmu.c
@@ -32,7 +32,7 @@ int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
                                 int *prot, target_ulong address, int rw)
 {
     *physical = address;
-    *prot = PAGE_READ | PAGE_WRITE;
+    *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
     return TLBRET_MATCH;
 }
 
@@ -187,7 +187,7 @@ int cpu_openrisc_handle_mmu_fault(CPUOpenRISCState *env,
 
     if (ret == TLBRET_MATCH) {
         tlb_set_page(env, address & TARGET_PAGE_MASK,
-                     physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
+                     physical & TARGET_PAGE_MASK, prot,
                      mmu_idx, TARGET_PAGE_SIZE);
         ret = 0;
     } else if (ret < 0) {
-- 
1.8.4.1

[Qemu-devel] [PATCH_v2 4/9] target-openrisc: Correct wrong epcr register in interrupt handler

[Sebastian Macke]

This patch corrects several misbehaviors during an interrupt process.
Most of the time the pc is already correct and therefore no special treatment
of the exceptions is necessary.

Tested by checking crashing programs which otherwise work in or1ksim.

Signed-off-by: Sebastian Macke <sebastian@macke.de>
---
 target-openrisc/interrupt.c | 25 +++++++------------------
 1 file changed, 7 insertions(+), 18 deletions(-)

diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
index 16ef4b3..2153e7e 100644
--- a/target-openrisc/interrupt.c
+++ b/target-openrisc/interrupt.c
@@ -30,26 +30,15 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
     OpenRISCCPU *cpu = OPENRISC_CPU(cs);
     CPUOpenRISCState *env = &cpu->env;
 #ifndef CONFIG_USER_ONLY
-    if (env->flags & D_FLAG) { /* Delay Slot insn */
+
+    env->epcr = env->pc;
+    if (env->flags & D_FLAG) {
         env->flags &= ~D_FLAG;
         env->sr |= SR_DSX;
-        if (env->exception_index == EXCP_TICK    ||
-            env->exception_index == EXCP_INT     ||
-            env->exception_index == EXCP_SYSCALL ||
-            env->exception_index == EXCP_FPE) {
-            env->epcr = env->jmp_pc;
-        } else {
-            env->epcr = env->pc - 4;
-        }
-    } else {
-        if (env->exception_index == EXCP_TICK    ||
-            env->exception_index == EXCP_INT     ||
-            env->exception_index == EXCP_SYSCALL ||
-            env->exception_index == EXCP_FPE) {
-            env->epcr = env->npc;
-        } else {
-            env->epcr = env->pc;
-        }
+        env->epcr -= 4;
+    }
+    if (env->exception_index == EXCP_SYSCALL) {
+        env->epcr += 4;
     }
 
     /* For machine-state changed between user-mode and supervisor mode,
-- 
1.8.4.1

[Qemu-devel] [PATCH_v2 5/9] openrisc-timer: Reduce overhead, Separate clock update functions

[Sebastian Macke]

The clock value is only evaluated when really necessary reducing
the overhead of the timer handling.

This also solves a problem in the way the Linux kernel
handles the timer and the expected accuracy.
The old version could lead to inaccurate timings.

Signed-off-by: Sebastian Macke <sebastian@macke.de>
---
 hw/openrisc/cputimer.c       | 29 +++++++++++++++++++----------
 target-openrisc/cpu.h        |  1 +
 target-openrisc/sys_helper.c | 38 ++++++++++++++++++--------------------
 3 files changed, 38 insertions(+), 30 deletions(-)

diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c
index 988ca20..9c54945 100644
--- a/hw/openrisc/cputimer.c
+++ b/hw/openrisc/cputimer.c
@@ -30,19 +30,28 @@ static int is_counting;
 
 void cpu_openrisc_count_update(OpenRISCCPU *cpu)
 {
-    uint64_t now, next;
-    uint32_t wait;
+    uint64_t now;
 
-    now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
     if (!is_counting) {
-        timer_del(cpu->env.timer);
-        last_clk = now;
         return;
     }
-
+    now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
     cpu->env.ttcr += (uint32_t)muldiv64(now - last_clk, TIMER_FREQ,
                                         get_ticks_per_sec());
     last_clk = now;
+}
+
+void cpu_openrisc_timer_update(OpenRISCCPU *cpu)
+{
+    uint32_t wait;
+    uint64_t now, next;
+
+    if (!is_counting) {
+        return;
+    }
+
+    cpu_openrisc_count_update(cpu);
+    now = last_clk;
 
     if ((cpu->env.ttmr & TTMR_TP) <= (cpu->env.ttcr & TTMR_TP)) {
         wait = TTMR_TP - (cpu->env.ttcr & TTMR_TP) + 1;
@@ -50,7 +59,6 @@ void cpu_openrisc_count_update(OpenRISCCPU *cpu)
     } else {
         wait = (cpu->env.ttmr & TTMR_TP) - (cpu->env.ttcr & TTMR_TP);
     }
-
     next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ);
     timer_mod(cpu->env.timer, next);
 }
@@ -63,8 +71,9 @@ void cpu_openrisc_count_start(OpenRISCCPU *cpu)
 
 void cpu_openrisc_count_stop(OpenRISCCPU *cpu)
 {
-    is_counting = 0;
+    timer_del(cpu->env.timer);
     cpu_openrisc_count_update(cpu);
+    is_counting = 0;
 }
 
 static void openrisc_timer_cb(void *opaque)
@@ -84,15 +93,15 @@ static void openrisc_timer_cb(void *opaque)
         break;
     case TIMER_INTR:
         cpu->env.ttcr = 0;
-        cpu_openrisc_count_start(cpu);
         break;
     case TIMER_SHOT:
         cpu_openrisc_count_stop(cpu);
         break;
     case TIMER_CONT:
-        cpu_openrisc_count_start(cpu);
         break;
     }
+
+    cpu_openrisc_timer_update(cpu);
 }
 
 void cpu_openrisc_clock_init(OpenRISCCPU *cpu)
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 8fd0bc0..0f9efdf 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -373,6 +373,7 @@ void cpu_openrisc_pic_init(OpenRISCCPU *cpu);
 /* hw/openrisc_timer.c */
 void cpu_openrisc_clock_init(OpenRISCCPU *cpu);
 void cpu_openrisc_count_update(OpenRISCCPU *cpu);
+void cpu_openrisc_timer_update(OpenRISCCPU *cpu);
 void cpu_openrisc_count_start(OpenRISCCPU *cpu);
 void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
 
diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c
index cccbc0e..f116588 100644
--- a/target-openrisc/sys_helper.c
+++ b/target-openrisc/sys_helper.c
@@ -127,33 +127,31 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
         break;
     case TO_SPR(10, 0): /* TTMR */
         {
+            if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
+                switch (rb & TTMR_M) {
+                case TIMER_NONE:
+                    cpu_openrisc_count_stop(cpu);
+                    break;
+                case TIMER_INTR:
+                case TIMER_SHOT:
+                case TIMER_CONT:
+                    cpu_openrisc_count_start(cpu);
+                    break;
+                default:
+                    break;
+                }
+            }
+
             int ip = env->ttmr & TTMR_IP;
 
             if (rb & TTMR_IP) {    /* Keep IP bit.  */
-                env->ttmr = (rb & ~TTMR_IP) + ip;
+                env->ttmr = (rb & ~TTMR_IP) | ip;
             } else {    /* Clear IP bit.  */
                 env->ttmr = rb & ~TTMR_IP;
                 cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
             }
 
-            cpu_openrisc_count_update(cpu);
-
-            switch (env->ttmr & TTMR_M) {
-            case TIMER_NONE:
-                cpu_openrisc_count_stop(cpu);
-                break;
-            case TIMER_INTR:
-                cpu_openrisc_count_start(cpu);
-                break;
-            case TIMER_SHOT:
-                cpu_openrisc_count_start(cpu);
-                break;
-            case TIMER_CONT:
-                cpu_openrisc_count_start(cpu);
-                break;
-            default:
-                break;
-            }
+            cpu_openrisc_timer_update(cpu);
         }
         break;
 
@@ -162,7 +160,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
         if (env->ttmr & TIMER_NONE) {
             return;
         }
-        cpu_openrisc_count_start(cpu);
+        cpu_openrisc_timer_update(cpu);
         break;
     default:
 
-- 
1.8.4.1

[Qemu-devel] [PATCH_v2 6/9] target-openrisc: Correct memory bounds checking for the tlb buffers

[Sebastian Macke]

The mtspr and mfspr routines didn't check for the correct memory boundaries.
This fixes a segmentation fault while booting Linux.

Signed-off-by: Sebastian Macke <sebastian@macke.de>
---
 target-openrisc/sys_helper.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c
index f116588..be06c45 100644
--- a/target-openrisc/sys_helper.c
+++ b/target-openrisc/sys_helper.c
@@ -81,7 +81,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
     case TO_SPR(0, 64): /* ESR */
         env->esr = rb;
         break;
-    case TO_SPR(1, 512) ... TO_SPR(1, 639): /* DTLBW0MR 0-127 */
+    case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
         idx = spr - TO_SPR(1, 512);
         if (!(rb & 1)) {
             tlb_flush_page(env, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
@@ -89,7 +89,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
         env->tlb->dtlb[0][idx].mr = rb;
         break;
 
-    case TO_SPR(1, 640) ... TO_SPR(1, 767): /* DTLBW0TR 0-127 */
+    case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
         idx = spr - TO_SPR(1, 640);
         env->tlb->dtlb[0][idx].tr = rb;
         break;
@@ -100,7 +100,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
     case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
     case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
         break;
-    case TO_SPR(2, 512) ... TO_SPR(2, 639):   /* ITLBW0MR 0-127 */
+    case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1):   /* ITLBW0MR 0-127 */
         idx = spr - TO_SPR(2, 512);
         if (!(rb & 1)) {
             tlb_flush_page(env, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
@@ -108,7 +108,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
         env->tlb->itlb[0][idx].mr = rb;
         break;
 
-    case TO_SPR(2, 640) ... TO_SPR(2, 767): /* ITLBW0TR 0-127 */
+    case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
         idx = spr - TO_SPR(2, 640);
         env->tlb->itlb[0][idx].tr = rb;
         break;
@@ -212,11 +212,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
     case TO_SPR(0, 64): /* ESR */
         return env->esr;
 
-    case TO_SPR(1, 512) ... TO_SPR(1, 639): /* DTLBW0MR 0-127 */
+    case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
         idx = spr - TO_SPR(1, 512);
         return env->tlb->dtlb[0][idx].mr;
 
-    case TO_SPR(1, 640) ... TO_SPR(1, 767): /* DTLBW0TR 0-127 */
+    case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
         idx = spr - TO_SPR(1, 640);
         return env->tlb->dtlb[0][idx].tr;
 
@@ -228,11 +228,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
     case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
         break;
 
-    case TO_SPR(2, 512) ... TO_SPR(2, 639): /* ITLBW0MR 0-127 */
+    case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
         idx = spr - TO_SPR(2, 512);
         return env->tlb->itlb[0][idx].mr;
 
-    case TO_SPR(2, 640) ... TO_SPR(2, 767): /* ITLBW0TR 0-127 */
+    case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
         idx = spr - TO_SPR(2, 640);
         return env->tlb->itlb[0][idx].tr;
 
-- 
1.8.4.1

[Qemu-devel] [PATCH_v2 7/9] target-openrisc: Separate branch flag from Supervision register

[Sebastian Macke]

The branch flag is very often used. To increase the speed
the flag is separated. This patch removes several
ands and ors and branches from the generated code.
The additional flag btaken is no longer necessary.

Signed-off-by: Sebastian Macke <sebastian@macke.de>
---
 target-openrisc/cpu.c              |  1 +
 target-openrisc/cpu.h              | 13 +++--
 target-openrisc/gdbstub.c          |  4 +-
 target-openrisc/interrupt.c        |  2 +-
 target-openrisc/interrupt_helper.c |  2 +-
 target-openrisc/machine.c          |  1 +
 target-openrisc/sys_helper.c       |  6 +--
 target-openrisc/translate.c        | 99 +++++++++++++++-----------------------
 8 files changed, 57 insertions(+), 71 deletions(-)

diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 8137943..09ba728 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -42,6 +42,7 @@ static void openrisc_cpu_reset(CPUState *s)
 
     cpu->env.pc = 0x100;
     cpu->env.sr = SR_FO | SR_SM;
+    cpu->env.srf = 0;
     cpu->env.exception_index = -1;
 
     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 0f9efdf..ab87cd2 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -272,6 +272,14 @@ typedef struct CPUOpenRISCTLBContext {
 } CPUOpenRISCTLBContext;
 #endif
 
+/* Helper for the supervision register */
+#define ENV_GET_SR(env) (((env)->sr&~SR_F) | ((env)->srf ? SR_F : 0))
+
+#define ENV_SET_SR(env, srtemp)   do {\
+                                      (env)->sr = ((srtemp) & ~SR_F) | SR_FO;\
+                                      (env)->srf = (srtemp) & SR_F;\
+                                  } while (0)
+
 typedef struct CPUOpenRISCState {
     target_ulong gpr[32];     /* General registers */
     target_ulong pc;          /* Program counter */
@@ -288,7 +296,8 @@ typedef struct CPUOpenRISCState {
     target_ulong epcr;        /* Exception PC register */
     target_ulong eear;        /* Exception EA register */
 
-    uint32_t sr;              /* Supervisor register */
+    uint32_t sr;              /* Supervision register */
+    uint32_t srf;             /* separated branch flag of Supervision register*/
     uint32_t vr;              /* Version register */
     uint32_t upr;             /* Unit presence register */
     uint32_t cpucfgr;         /* CPU configure register */
@@ -300,8 +309,6 @@ typedef struct CPUOpenRISCState {
 
     uint32_t flags;           /* cpu_flags, we only use it for exception
                                  in solt so far.  */
-    uint32_t btaken;          /* the SR_F bit */
-
     CPU_COMMON
 
 #ifndef CONFIG_USER_ONLY
diff --git a/target-openrisc/gdbstub.c b/target-openrisc/gdbstub.c
index 18bcc46..81acf2d 100644
--- a/target-openrisc/gdbstub.c
+++ b/target-openrisc/gdbstub.c
@@ -37,7 +37,7 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
             return gdb_get_reg32(mem_buf, env->npc);
 
         case 34:    /* SR */
-            return gdb_get_reg32(mem_buf, env->sr);
+            return gdb_get_reg32(mem_buf, ENV_GET_SR(env));
 
         default:
             break;
@@ -72,7 +72,7 @@ int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
             break;
 
         case 34: /* SR */
-            env->sr = tmp;
+            ENV_SET_SR(env, tmp);
             break;
 
         default:
diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
index 2153e7e..d1d6ae2 100644
--- a/target-openrisc/interrupt.c
+++ b/target-openrisc/interrupt.c
@@ -45,7 +45,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
        we need flush TLB when we enter&exit EXCP.  */
     tlb_flush(env, 1);
 
-    env->esr = env->sr;
+    env->esr = ENV_GET_SR(env);
     env->sr &= ~SR_DME;
     env->sr &= ~SR_IME;
     env->sr |= SR_SM;
diff --git a/target-openrisc/interrupt_helper.c b/target-openrisc/interrupt_helper.c
index 844648f..8a07b09 100644
--- a/target-openrisc/interrupt_helper.c
+++ b/target-openrisc/interrupt_helper.c
@@ -31,7 +31,7 @@ void HELPER(rfe)(CPUOpenRISCState *env)
 #endif
     cpu->env.pc = cpu->env.epcr;
     cpu->env.npc = cpu->env.epcr;
-    cpu->env.sr = cpu->env.esr;
+    ENV_SET_SR(&(cpu->env), cpu->env.esr);
 
 #ifndef CONFIG_USER_ONLY
     if (cpu->env.sr & SR_DME) {
diff --git a/target-openrisc/machine.c b/target-openrisc/machine.c
index 6f864fe..2bdd40f 100644
--- a/target-openrisc/machine.c
+++ b/target-openrisc/machine.c
@@ -28,6 +28,7 @@ static const VMStateDescription vmstate_env = {
     .fields = (VMStateField[]) {
         VMSTATE_UINT32_ARRAY(gpr, CPUOpenRISCState, 32),
         VMSTATE_UINT32(sr, CPUOpenRISCState),
+        VMSTATE_UINT32(srf, CPUOpenRISCState),
         VMSTATE_UINT32(epcr, CPUOpenRISCState),
         VMSTATE_UINT32(eear, CPUOpenRISCState),
         VMSTATE_UINT32(esr, CPUOpenRISCState),
diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c
index be06c45..1d0651a 100644
--- a/target-openrisc/sys_helper.c
+++ b/target-openrisc/sys_helper.c
@@ -47,8 +47,8 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
             (rb & (SR_IME | SR_DME | SR_SM))) {
             tlb_flush(env, 1);
         }
-        env->sr = rb;
-        env->sr |= SR_FO;      /* FO is const equal to 1 */
+        ENV_SET_SR(env, rb);
+
         if (env->sr & SR_DME) {
             env->tlb->cpu_openrisc_map_address_data =
                 &cpu_openrisc_get_phys_data;
@@ -198,7 +198,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
         return env->npc;
 
     case TO_SPR(0, 17): /* SR */
-        return env->sr;
+        return ENV_GET_SR(env);
 
     case TO_SPR(0, 18): /* PPC */
         return env->ppc;
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 91c60eb..1ae807f 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -51,12 +51,12 @@ typedef struct DisasContext {
 
 static TCGv_ptr cpu_env;
 static TCGv cpu_sr;
+static TCGv cpu_srf;
 static TCGv cpu_R[32];
 static TCGv cpu_pc;
 static TCGv jmp_pc;            /* l.jr/l.jalr temp pc */
 static TCGv cpu_npc;
 static TCGv cpu_ppc;
-static TCGv_i32 env_btaken;    /* bf/bnf , F flag taken */
 static TCGv_i32 fpcsr;
 static TCGv machi, maclo;
 static TCGv fpmaddhi, fpmaddlo;
@@ -76,6 +76,8 @@ void openrisc_translate_init(void)
     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
     cpu_sr = tcg_global_mem_new(TCG_AREG0,
                                 offsetof(CPUOpenRISCState, sr), "sr");
+    cpu_srf = tcg_global_mem_new(TCG_AREG0,
+                                offsetof(CPUOpenRISCState, srf), "srf");
     env_flags = tcg_global_mem_new_i32(TCG_AREG0,
                                        offsetof(CPUOpenRISCState, flags),
                                        "flags");
@@ -87,9 +89,6 @@ void openrisc_translate_init(void)
                                  offsetof(CPUOpenRISCState, ppc), "ppc");
     jmp_pc = tcg_global_mem_new(TCG_AREG0,
                                 offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc");
-    env_btaken = tcg_global_mem_new_i32(TCG_AREG0,
-                                        offsetof(CPUOpenRISCState, btaken),
-                                        "btaken");
     fpcsr = tcg_global_mem_new_i32(TCG_AREG0,
                                    offsetof(CPUOpenRISCState, fpcsr),
                                    "fpcsr");
@@ -112,17 +111,6 @@ void openrisc_translate_init(void)
     }
 }
 
-/* Writeback SR_F transaltion-space to execution-space.  */
-static inline void wb_SR_F(void)
-{
-    int label;
-
-    label = gen_new_label();
-    tcg_gen_andi_tl(cpu_sr, cpu_sr, ~SR_F);
-    tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, label);
-    tcg_gen_ori_tl(cpu_sr, cpu_sr, SR_F);
-    gen_set_label(label);
-}
 
 static inline int zero_extend(unsigned int val, int width)
 {
@@ -224,14 +212,11 @@ static void gen_jump(DisasContext *dc, uint32_t imm, uint32_t reg, uint32_t op0)
     case 0x04:     /* l.bf  */
         {
             int lab = gen_new_label();
-            TCGv sr_f = tcg_temp_new();
             tcg_gen_movi_tl(jmp_pc, dc->pc+8);
-            tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
-            tcg_gen_brcondi_i32(op0 == 0x03 ? TCG_COND_EQ : TCG_COND_NE,
-                                sr_f, SR_F, lab);
+            tcg_gen_brcondi_i32(op0 == 0x03 ? TCG_COND_NE : TCG_COND_EQ,
+                                cpu_srf, 0, lab);
             tcg_gen_movi_tl(jmp_pc, tmp_pc);
             gen_set_label(lab);
-            tcg_temp_free(sr_f);
         }
         break;
     case 0x11:     /* l.jr */
@@ -567,14 +552,11 @@ static void dec_calc(DisasContext *dc, uint32_t insn)
             {
                 int lab = gen_new_label();
                 TCGv res = tcg_temp_local_new();
-                TCGv sr_f = tcg_temp_new();
-                tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
                 tcg_gen_mov_tl(res, cpu_R[rb]);
-                tcg_gen_brcondi_tl(TCG_COND_NE, sr_f, SR_F, lab);
+                tcg_gen_brcondi_tl(TCG_COND_NE, cpu_srf, SR_F, lab);
                 tcg_gen_mov_tl(res, cpu_R[ra]);
                 gen_set_label(lab);
                 tcg_gen_mov_tl(cpu_R[rd], res);
-                tcg_temp_free(sr_f);
                 tcg_temp_free(res);
             }
             break;
@@ -1213,7 +1195,6 @@ static void dec_comp(DisasContext *dc, uint32_t insn)
     ra = extract32(insn, 16, 5);
     rb = extract32(insn, 11, 5);
 
-    tcg_gen_movi_i32(env_btaken, 0x0);
     /* unsigned integers  */
     tcg_gen_ext32u_tl(cpu_R[ra], cpu_R[ra]);
     tcg_gen_ext32u_tl(cpu_R[rb], cpu_R[rb]);
@@ -1221,59 +1202,58 @@ static void dec_comp(DisasContext *dc, uint32_t insn)
     switch (op0) {
     case 0x0:    /* l.sfeq */
         LOG_DIS("l.sfeq  r%d, r%d\n", ra, rb);
-        tcg_gen_setcond_tl(TCG_COND_EQ, env_btaken, cpu_R[ra], cpu_R[rb]);
+        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_srf, cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0x1:    /* l.sfne */
         LOG_DIS("l.sfne  r%d, r%d\n", ra, rb);
-        tcg_gen_setcond_tl(TCG_COND_NE, env_btaken, cpu_R[ra], cpu_R[rb]);
+        tcg_gen_setcond_tl(TCG_COND_NE, cpu_srf, cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0x2:    /* l.sfgtu */
         LOG_DIS("l.sfgtu  r%d, r%d\n", ra, rb);
-        tcg_gen_setcond_tl(TCG_COND_GTU, env_btaken, cpu_R[ra], cpu_R[rb]);
+        tcg_gen_setcond_tl(TCG_COND_GTU, cpu_srf, cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0x3:    /* l.sfgeu */
         LOG_DIS("l.sfgeu  r%d, r%d\n", ra, rb);
-        tcg_gen_setcond_tl(TCG_COND_GEU, env_btaken, cpu_R[ra], cpu_R[rb]);
+        tcg_gen_setcond_tl(TCG_COND_GEU, cpu_srf, cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0x4:    /* l.sfltu */
         LOG_DIS("l.sfltu  r%d, r%d\n", ra, rb);
-        tcg_gen_setcond_tl(TCG_COND_LTU, env_btaken, cpu_R[ra], cpu_R[rb]);
+        tcg_gen_setcond_tl(TCG_COND_LTU, cpu_srf, cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0x5:    /* l.sfleu */
         LOG_DIS("l.sfleu  r%d, r%d\n", ra, rb);
-        tcg_gen_setcond_tl(TCG_COND_LEU, env_btaken, cpu_R[ra], cpu_R[rb]);
+        tcg_gen_setcond_tl(TCG_COND_LEU, cpu_srf, cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0xa:    /* l.sfgts */
         LOG_DIS("l.sfgts  r%d, r%d\n", ra, rb);
-        tcg_gen_setcond_tl(TCG_COND_GT, env_btaken, cpu_R[ra], cpu_R[rb]);
+        tcg_gen_setcond_tl(TCG_COND_GT, cpu_srf, cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0xb:    /* l.sfges */
         LOG_DIS("l.sfges  r%d, r%d\n", ra, rb);
-        tcg_gen_setcond_tl(TCG_COND_GE, env_btaken, cpu_R[ra], cpu_R[rb]);
+        tcg_gen_setcond_tl(TCG_COND_GE, cpu_srf, cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0xc:    /* l.sflts */
         LOG_DIS("l.sflts  r%d, r%d\n", ra, rb);
-        tcg_gen_setcond_tl(TCG_COND_LT, env_btaken, cpu_R[ra], cpu_R[rb]);
+        tcg_gen_setcond_tl(TCG_COND_LT, cpu_srf, cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0xd:    /* l.sfles */
         LOG_DIS("l.sfles  r%d, r%d\n", ra, rb);
-        tcg_gen_setcond_tl(TCG_COND_LE, env_btaken, cpu_R[ra], cpu_R[rb]);
+        tcg_gen_setcond_tl(TCG_COND_LE, cpu_srf, cpu_R[ra], cpu_R[rb]);
         break;
 
     default:
         gen_illegal_exception(dc);
         break;
     }
-    wb_SR_F();
 }
 
 static void dec_compi(DisasContext *dc, uint32_t insn)
@@ -1285,65 +1265,63 @@ static void dec_compi(DisasContext *dc, uint32_t insn)
     ra = extract32(insn, 16, 5);
     I16 = extract32(insn, 0, 16);
 
-    tcg_gen_movi_i32(env_btaken, 0x0);
     I16 = sign_extend(I16, 16);
 
     switch (op0) {
     case 0x0:    /* l.sfeqi */
         LOG_DIS("l.sfeqi  r%d, %d\n", ra, I16);
-        tcg_gen_setcondi_tl(TCG_COND_EQ, env_btaken, cpu_R[ra], I16);
+        tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_srf, cpu_R[ra], I16);
         break;
 
     case 0x1:    /* l.sfnei */
         LOG_DIS("l.sfnei  r%d, %d\n", ra, I16);
-        tcg_gen_setcondi_tl(TCG_COND_NE, env_btaken, cpu_R[ra], I16);
+        tcg_gen_setcondi_tl(TCG_COND_NE, cpu_srf, cpu_R[ra], I16);
         break;
 
     case 0x2:    /* l.sfgtui */
         LOG_DIS("l.sfgtui  r%d, %d\n", ra, I16);
-        tcg_gen_setcondi_tl(TCG_COND_GTU, env_btaken, cpu_R[ra], I16);
+        tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_srf, cpu_R[ra], I16);
         break;
 
     case 0x3:    /* l.sfgeui */
         LOG_DIS("l.sfgeui  r%d, %d\n", ra, I16);
-        tcg_gen_setcondi_tl(TCG_COND_GEU, env_btaken, cpu_R[ra], I16);
+        tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_srf, cpu_R[ra], I16);
         break;
 
     case 0x4:    /* l.sfltui */
         LOG_DIS("l.sfltui  r%d, %d\n", ra, I16);
-        tcg_gen_setcondi_tl(TCG_COND_LTU, env_btaken, cpu_R[ra], I16);
+        tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_srf, cpu_R[ra], I16);
         break;
 
     case 0x5:    /* l.sfleui */
         LOG_DIS("l.sfleui  r%d, %d\n", ra, I16);
-        tcg_gen_setcondi_tl(TCG_COND_LEU, env_btaken, cpu_R[ra], I16);
+        tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_srf, cpu_R[ra], I16);
         break;
 
     case 0xa:    /* l.sfgtsi */
         LOG_DIS("l.sfgtsi  r%d, %d\n", ra, I16);
-        tcg_gen_setcondi_tl(TCG_COND_GT, env_btaken, cpu_R[ra], I16);
+        tcg_gen_setcondi_tl(TCG_COND_GT, cpu_srf, cpu_R[ra], I16);
         break;
 
     case 0xb:    /* l.sfgesi */
         LOG_DIS("l.sfgesi  r%d, %d\n", ra, I16);
-        tcg_gen_setcondi_tl(TCG_COND_GE, env_btaken, cpu_R[ra], I16);
+        tcg_gen_setcondi_tl(TCG_COND_GE, cpu_srf, cpu_R[ra], I16);
         break;
 
     case 0xc:    /* l.sfltsi */
         LOG_DIS("l.sfltsi  r%d, %d\n", ra, I16);
-        tcg_gen_setcondi_tl(TCG_COND_LT, env_btaken, cpu_R[ra], I16);
+        tcg_gen_setcondi_tl(TCG_COND_LT, cpu_srf, cpu_R[ra], I16);
         break;
 
     case 0xd:    /* l.sflesi */
         LOG_DIS("l.sflesi  r%d, %d\n", ra, I16);
-        tcg_gen_setcondi_tl(TCG_COND_LE, env_btaken, cpu_R[ra], I16);
+        tcg_gen_setcondi_tl(TCG_COND_LE, cpu_srf, cpu_R[ra], I16);
         break;
 
     default:
         gen_illegal_exception(dc);
         break;
     }
-    wb_SR_F();
 }
 
 static void dec_sys(DisasContext *dc, uint32_t insn)
@@ -1479,32 +1457,32 @@ static void dec_float(DisasContext *dc, uint32_t insn)
 
     case 0x08:    /* lf.sfeq.s */
         LOG_DIS("lf.sfeq.s r%d, r%d\n", ra, rb);
-        gen_helper_float_eq_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+        gen_helper_float_eq_s(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0x09:    /* lf.sfne.s */
         LOG_DIS("lf.sfne.s r%d, r%d\n", ra, rb);
-        gen_helper_float_ne_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+        gen_helper_float_ne_s(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0x0a:    /* lf.sfgt.s */
         LOG_DIS("lf.sfgt.s r%d, r%d\n", ra, rb);
-        gen_helper_float_gt_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+        gen_helper_float_gt_s(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0x0b:    /* lf.sfge.s */
         LOG_DIS("lf.sfge.s r%d, r%d\n", ra, rb);
-        gen_helper_float_ge_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+        gen_helper_float_ge_s(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0x0c:    /* lf.sflt.s */
         LOG_DIS("lf.sflt.s r%d, r%d\n", ra, rb);
-        gen_helper_float_lt_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+        gen_helper_float_lt_s(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0x0d:    /* lf.sfle.s */
         LOG_DIS("lf.sfle.s r%d, r%d\n", ra, rb);
-        gen_helper_float_le_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+        gen_helper_float_le_s(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
         break;
 
 /* not used yet, open it when we need or64.  */
@@ -1565,37 +1543,37 @@ static void dec_float(DisasContext *dc, uint32_t insn)
     case 0x18:     lf.sfeq.d
         LOG_DIS("lf.sfeq.d r%d, r%d\n", ra, rb);
         check_of64s(dc);
-        gen_helper_float_eq_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+        gen_helper_float_eq_d(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0x1a:     lf.sfgt.d
         LOG_DIS("lf.sfgt.d r%d, r%d\n", ra, rb);
         check_of64s(dc);
-        gen_helper_float_gt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+        gen_helper_float_gt_d(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0x1b:     lf.sfge.d
         LOG_DIS("lf.sfge.d r%d, r%d\n", ra, rb);
         check_of64s(dc);
-        gen_helper_float_ge_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+        gen_helper_float_ge_d(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0x19:     lf.sfne.d
         LOG_DIS("lf.sfne.d r%d, r%d\n", ra, rb);
         check_of64s(dc);
-        gen_helper_float_ne_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+        gen_helper_float_ne_d(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0x1c:     lf.sflt.d
         LOG_DIS("lf.sflt.d r%d, r%d\n", ra, rb);
         check_of64s(dc);
-        gen_helper_float_lt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+        gen_helper_float_lt_d(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
         break;
 
     case 0x1d:     lf.sfle.d
         LOG_DIS("lf.sfle.d r%d, r%d\n", ra, rb);
         check_of64s(dc);
-        gen_helper_float_le_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+        gen_helper_float_le_d(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
         break;
 #endif*/
 
@@ -1603,7 +1581,6 @@ static void dec_float(DisasContext *dc, uint32_t insn)
         gen_illegal_exception(dc);
         break;
     }
-    wb_SR_F();
 }
 
 static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
-- 
1.8.4.1

[Qemu-devel] [PATCH_v2 8/9] target-openrisc: Complete remove of npc and ppc variables

[Sebastian Macke]

According to the specification the registers "npc" (next pc) and
ppc (previous pc) are only meant for external debuggers.
They have undefined behavior when you read and especially write to it.

Additionally in the current implementation they show different behavior
when in singlestep mode.

Because they are no longer needed and decrease the performance by using
two tcg instructions per opcode they are removed.

Signed-off-by: Sebastian Macke <sebastian@macke.de>
---
 target-openrisc/cpu.h              |  2 --
 target-openrisc/gdbstub.c          | 16 ++--------------
 target-openrisc/interrupt_helper.c |  1 -
 target-openrisc/machine.c          |  2 --
 target-openrisc/sys_helper.c       | 14 --------------
 target-openrisc/translate.c        | 17 ++---------------
 6 files changed, 4 insertions(+), 48 deletions(-)

diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index ab87cd2..24afe6f 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -283,8 +283,6 @@ typedef struct CPUOpenRISCTLBContext {
 typedef struct CPUOpenRISCState {
     target_ulong gpr[32];     /* General registers */
     target_ulong pc;          /* Program counter */
-    target_ulong npc;         /* Next PC */
-    target_ulong ppc;         /* Prev PC */
     target_ulong jmp_pc;      /* Jump PC */
 
     target_ulong machi;       /* Multiply register MACHI */
diff --git a/target-openrisc/gdbstub.c b/target-openrisc/gdbstub.c
index 81acf2d..c1f9561 100644
--- a/target-openrisc/gdbstub.c
+++ b/target-openrisc/gdbstub.c
@@ -30,13 +30,8 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
         return gdb_get_reg32(mem_buf, env->gpr[n]);
     } else {
         switch (n) {
-        case 32:    /* PPC */
-            return gdb_get_reg32(mem_buf, env->ppc);
 
-        case 33:    /* NPC */
-            return gdb_get_reg32(mem_buf, env->npc);
-
-        case 34:    /* SR */
+        case 32:    /* SR */
             return gdb_get_reg32(mem_buf, ENV_GET_SR(env));
 
         default:
@@ -63,15 +58,8 @@ int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
         env->gpr[n] = tmp;
     } else {
         switch (n) {
-        case 32: /* PPC */
-            env->ppc = tmp;
-            break;
-
-        case 33: /* NPC */
-            env->npc = tmp;
-            break;
 
-        case 34: /* SR */
+        case 32: /* SR */
             ENV_SET_SR(env, tmp);
             break;
 
diff --git a/target-openrisc/interrupt_helper.c b/target-openrisc/interrupt_helper.c
index 8a07b09..ae187f5 100644
--- a/target-openrisc/interrupt_helper.c
+++ b/target-openrisc/interrupt_helper.c
@@ -30,7 +30,6 @@ void HELPER(rfe)(CPUOpenRISCState *env)
                          (cpu->env.esr & (SR_SM | SR_IME | SR_DME));
 #endif
     cpu->env.pc = cpu->env.epcr;
-    cpu->env.npc = cpu->env.epcr;
     ENV_SET_SR(&(cpu->env), cpu->env.esr);
 
 #ifndef CONFIG_USER_ONLY
diff --git a/target-openrisc/machine.c b/target-openrisc/machine.c
index 2bdd40f..6846e14 100644
--- a/target-openrisc/machine.c
+++ b/target-openrisc/machine.c
@@ -34,8 +34,6 @@ static const VMStateDescription vmstate_env = {
         VMSTATE_UINT32(esr, CPUOpenRISCState),
         VMSTATE_UINT32(fpcsr, CPUOpenRISCState),
         VMSTATE_UINT32(pc, CPUOpenRISCState),
-        VMSTATE_UINT32(npc, CPUOpenRISCState),
-        VMSTATE_UINT32(ppc, CPUOpenRISCState),
         VMSTATE_END_OF_LIST()
     }
 };
diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c
index 1d0651a..3eda0e1 100644
--- a/target-openrisc/sys_helper.c
+++ b/target-openrisc/sys_helper.c
@@ -38,10 +38,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
         env->vr = rb;
         break;
 
-    case TO_SPR(0, 16): /* NPC */
-        env->npc = rb;
-        break;
-
     case TO_SPR(0, 17): /* SR */
         if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
             (rb & (SR_IME | SR_DME | SR_SM))) {
@@ -66,10 +62,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
         }
         break;
 
-    case TO_SPR(0, 18): /* PPC */
-        env->ppc = rb;
-        break;
-
     case TO_SPR(0, 32): /* EPCR */
         env->epcr = rb;
         break;
@@ -194,15 +186,9 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
     case TO_SPR(0, 4): /* IMMUCFGR */
         return env->immucfgr;
 
-    case TO_SPR(0, 16): /* NPC */
-        return env->npc;
-
     case TO_SPR(0, 17): /* SR */
         return ENV_GET_SR(env);
 
-    case TO_SPR(0, 18): /* PPC */
-        return env->ppc;
-
     case TO_SPR(0, 32): /* EPCR */
         return env->epcr;
 
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 1ae807f..8fc679b 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -41,7 +41,7 @@
 
 typedef struct DisasContext {
     TranslationBlock *tb;
-    target_ulong pc, ppc, npc;
+    target_ulong pc;
     uint32_t tb_flags, synced_flags, flags;
     uint32_t is_jmp;
     uint32_t mem_idx;
@@ -55,8 +55,6 @@ static TCGv cpu_srf;
 static TCGv cpu_R[32];
 static TCGv cpu_pc;
 static TCGv jmp_pc;            /* l.jr/l.jalr temp pc */
-static TCGv cpu_npc;
-static TCGv cpu_ppc;
 static TCGv_i32 fpcsr;
 static TCGv machi, maclo;
 static TCGv fpmaddhi, fpmaddlo;
@@ -83,10 +81,6 @@ void openrisc_translate_init(void)
                                        "flags");
     cpu_pc = tcg_global_mem_new(TCG_AREG0,
                                 offsetof(CPUOpenRISCState, pc), "pc");
-    cpu_npc = tcg_global_mem_new(TCG_AREG0,
-                                 offsetof(CPUOpenRISCState, npc), "npc");
-    cpu_ppc = tcg_global_mem_new(TCG_AREG0,
-                                 offsetof(CPUOpenRISCState, ppc), "ppc");
     jmp_pc = tcg_global_mem_new(TCG_AREG0,
                                 offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc");
     fpcsr = tcg_global_mem_new_i32(TCG_AREG0,
@@ -1662,7 +1656,6 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
 
     gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
     dc->is_jmp = DISAS_NEXT;
-    dc->ppc = pc_start;
     dc->pc = pc_start;
     dc->flags = cpu->env.cpucfgr;
     dc->mem_idx = cpu_mmu_index(&cpu->env);
@@ -1707,12 +1700,8 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
         if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
             gen_io_start();
         }
-        dc->ppc = dc->pc - 4;
-        dc->npc = dc->pc + 4;
-        tcg_gen_movi_tl(cpu_ppc, dc->ppc);
-        tcg_gen_movi_tl(cpu_npc, dc->npc);
         disas_openrisc_insn(dc, cpu);
-        dc->pc = dc->npc;
+        dc->pc += 4;
         num_insns++;
         /* delay slot */
         if (dc->delayed_branch) {
@@ -1721,8 +1710,6 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
                 dc->tb_flags &= ~D_FLAG;
                 gen_sync_flags(dc);
                 tcg_gen_mov_tl(cpu_pc, jmp_pc);
-                tcg_gen_mov_tl(cpu_npc, jmp_pc);
-                tcg_gen_movi_tl(jmp_pc, 0);
                 tcg_gen_exit_tb(0);
                 dc->is_jmp = DISAS_JUMP;
                 break;
-- 
1.8.4.1

[Qemu-devel] [PATCH_v2 9/9] target-openrisc: Correct carry flag check of l.addc and l.addic test cases

[Sebastian Macke]

The test cases did not correctly test for the carry flag.

Signed-off-by: Sebastian Macke <sebastian@macke.de>
---
 tests/tcg/openrisc/test_addc.c  |  8 +++++---
 tests/tcg/openrisc/test_addic.c | 10 ++++++----
 2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/tests/tcg/openrisc/test_addc.c b/tests/tcg/openrisc/test_addc.c
index 05d18f8..a8f756a 100644
--- a/tests/tcg/openrisc/test_addc.c
+++ b/tests/tcg/openrisc/test_addc.c
@@ -7,9 +7,10 @@ int main(void)
 
     b = 0x01;
     c = 0xffffffff;
-    result = 1;
+    result = 0;
     __asm
-    ("l.addc   %0, %1, %2\n\t"
+    ("l.add r1, r1, r0\n\t" /* clear carry */
+     "l.addc   %0, %1, %2\n\t"
      : "=r"(a)
      : "r"(b), "r"(c)
     );
@@ -22,7 +23,8 @@ int main(void)
     c = 0xffffffff;
     result = 0x80000001;
     __asm
-    ("l.addc   %0, %1, %2\n\t"
+    ("l.add r1, r1, r0\n\t" /* clear carry */
+     "l.addc   %0, %1, %2\n\t"
      "l.movhi  %2, 0x7fff\n\t"
      "l.ori    %2, %2, 0xffff\n\t"
      "l.addc   %0, %1, %2\n\t"
diff --git a/tests/tcg/openrisc/test_addic.c b/tests/tcg/openrisc/test_addic.c
index 4ba7432..857aaa1 100644
--- a/tests/tcg/openrisc/test_addic.c
+++ b/tests/tcg/openrisc/test_addic.c
@@ -6,9 +6,10 @@ int main(void)
     int result;
 
     a = 1;
-    result = 0x1;
+    result = 0x0;
     __asm
-    ("l.addic %0, %0, 0xffff\n\t"
+    ("l.add r1, r1, r0\n\t" /* clear carry */
+     "l.addic %0, %0, 0xffff\n\t"
      : "+r"(a)
     );
     if (a != result) {
@@ -16,10 +17,11 @@ int main(void)
         return -1;
    }
 
-    a = 0x1;
+    a = -1;
     result = 0x201;
     __asm
-    ("l.addic %0, %0, 0xffff\n\t"
+    ("l.add r1, r1, r0\n\t"  /* clear carry */
+     "l.addic %0, %0, 0x1\n\t"
      "l.ori   %0, r0, 0x100\n\t"
      "l.addic %0, %0, 0x100\n\t"
      : "+r"(a)
-- 
1.8.4.1

Re: [Qemu-devel] [PATCH_v2 9/9] target-openrisc: Correct carry flagcheck of l.addc and l.addic test casess

[Alex Bennée]

sebastian@macke.de writes:

> The test cases did not correctly test for the carry flag.

Out of interest how are you building your test cases, cross-compiling or
from within the emulated environment?

I want to clean-up and resurrect the TCG tests but one of the challenges
is all the non-x86 targets need to be built somehow.

Cheers,

-- 
Alex Bennée

Re: [Qemu-devel] [PATCH_v2 9/9] target-openrisc: Correct carry flagcheck of l.addc and l.addic test casess

[Sebastian Macke]

Hi Alex,

I am using a cross-compiling toolchain. It's the easiest way as I have 
to compile the image for QEMU anyhow.
http://opencores.org/or1k/OpenRISC_GNU_tool_chain

Then it's just an "make && make test" in the corresponding 
tests/tcg/openrisc folder.

Inside the virtual machine it would be a little bit more complicated. 
You have to compile Linux with the initramfs containing the QEMU test 
sources. Another storage device is currently not supported by the 
OpenRISC QEMU emulator.

Sebastian


On 22/10/2013 1:35 AM, Alex Bennée wrote:
> sebastian@macke.de writes:
>
>> The test cases did not correctly test for the carry flag.
> Out of interest how are you building your test cases, cross-compiling or
> from within the emulated environment?
>
> I want to clean-up and resurrect the TCG tests but one of the challenges
> is all the non-x86 targets need to be built somehow.
>
> Cheers,
>

Re: [Qemu-devel] [PATCH_v2 9/9] target-openrisc: Correct carry flagcheck of l.addc and l.addic test casess

[Max Filippov]

On Tue, Oct 22, 2013 at 7:45 PM, Sebastian Macke <sebastian@macke.de> wrote:
> Hi Alex,
>
> I am using a cross-compiling toolchain. It's the easiest way as I have to
> compile the image for QEMU anyhow.
> http://opencores.org/or1k/OpenRISC_GNU_tool_chain
>
> Then it's just an "make && make test" in the corresponding
> tests/tcg/openrisc folder.
>
> Inside the virtual machine it would be a little bit more complicated. You
> have to compile Linux with the initramfs containing the QEMU test sources.
> Another storage device is currently not supported by the OpenRISC QEMU
> emulator.

It should be possible to use network, I did a quick check at the time of
openrisc port submission, it used to work.

-- 
Thanks.
-- Max

Re: [Qemu-devel] [PATCH_v2 9/9] target-openrisc: Correct carry flagcheck of l.addc and l.addic test casess

[Alex Bennée]

jcmvbkbc@gmail.com writes:

> On Tue, Oct 22, 2013 at 7:45 PM, Sebastian Macke <sebastian@macke.de> wrote:
>> Hi Alex,
>>
>> I am using a cross-compiling toolchain. It's the easiest way as I have to
>> compile the image for QEMU anyhow.
>> http://opencores.org/or1k/OpenRISC_GNU_tool_chain
<snip>

I shall have a look.

>
> It should be possible to use network, I did a quick check at the time of
> openrisc port submission, it used to work.

Nah cross-compiling makes more sense. I was thinking of making configure
detect the various cross compilers at configure time and then optionally
enable each set of tcg tests depending on Cross Compile support.

-- 
Alex Bennée

Re: [Qemu-devel] [PATCH_v2 9/9] target-openrisc: Correct carry flagcheck of l.addc and l.addic test casess

[Sebastian Macke]

On 22/10/2013 9:01 AM, Max Filippov wrote:
> On Tue, Oct 22, 2013 at 7:45 PM, Sebastian Macke <sebastian@macke.de> wrote:
>> Hi Alex,
>>
>> I am using a cross-compiling toolchain. It's the easiest way as I have to
>> compile the image for QEMU anyhow.
>> http://opencores.org/or1k/OpenRISC_GNU_tool_chain
>>
>> Then it's just an "make && make test" in the corresponding
>> tests/tcg/openrisc folder.
>>
>> Inside the virtual machine it would be a little bit more complicated. You
>> have to compile Linux with the initramfs containing the QEMU test sources.
>> Another storage device is currently not supported by the OpenRISC QEMU
>> emulator.
> It should be possible to use network, I did a quick check at the time of
> openrisc port submission, it used to work.
>

This is true. Via a network file system it should be no problem. But 
this is a very complicated way to test the QEMU tcg part.
The image containing gcc I am currently using you can download under 
www.simulationcorner.net/vmlinux
Run it with "qemu-system-or32 -m 128 -kernel vmlinux -nographic"

Re: [Qemu-devel] [PATCH_v2 0/9] target-openrisc: Corrections and speed improvements

[Jia Liu]

Hi Sebastian,

On Tue, Oct 22, 2013 at 8:12 AM, Sebastian Macke <sebastian@macke.de> wrote:
>
> This series is the first part to make the OpenRISC target more
> reliable and faster.
> It corrects several severe problems which prevented the OpenRISC emulation
> for being useful in the past.
>
> The patchset was tested with
>   - the tests/tcg/openrisc tests
>   - booting Linux 3.11
>   - run configure + make + gcc of a simple terminal graphic demo called cmatrix
>   - run benchmark tool nbench in qemu-user mode and in the softmmu mode
>
> The speed improvement is less than 10% because the overhead is still to high
> as the openrisc target does not support translation block chaining.
> This will be included in one of the future patches.
>
> Only the patch which removes the npc and ppc variables removes a little feature
> from the OpenRISC target but which does not break the specification and will lead to
> a significant speed improvement.

For v2 0/9 - 9/9
Acked-by: Jia Liu <proljc@gmail.com>

I'll add some comment into the code to explain why we separate flags from sr
and send a pull request if nobody raise a rejection.

>
>
> Sebastian Macke (9):
>   target-openrisc: Speed up move instruction
>   target-openrisc: Remove unnecessary code generated by jump
>     instructions
>   target-openrisc: Remove executable flag for every page
>   target-openrisc: Correct wrong epcr register in interrupt handler
>   openrisc-timer: Reduce overhead, Separate clock update functions
>   target-openrisc: Correct memory bounds checking for the tlb buffers
>   target-openrisc: Separate branch flag from Supervision register
>   target-openrisc: Complete remove of npc and ppc variables
>   target-openrisc: Correct carry flag check of l.addc and l.addic test
>     cases
>
>  hw/openrisc/cputimer.c             |  29 ++++--
>  target-openrisc/cpu.c              |   1 +
>  target-openrisc/cpu.h              |  16 ++-
>  target-openrisc/gdbstub.c          |  20 +---
>  target-openrisc/interrupt.c        |  27 ++---
>  target-openrisc/interrupt_helper.c |   3 +-
>  target-openrisc/machine.c          |   3 +-
>  target-openrisc/mmu.c              |   4 +-
>  target-openrisc/sys_helper.c       |  74 ++++++--------
>  target-openrisc/translate.c        | 201 ++++++++++++++++---------------------
>  tests/tcg/openrisc/test_addc.c     |   8 +-
>  tests/tcg/openrisc/test_addic.c    |  10 +-
>  12 files changed, 175 insertions(+), 221 deletions(-)
>
> --
> 1.8.4.1
>

Regards,
Jia

Re: [Qemu-devel] [PATCH_v2 9/9] target-openrisc: Correct carry flagcheck of l.addc and l.addic test casess

[Max Filippov]

On Tue, Oct 22, 2013 at 8:15 PM, Sebastian Macke <sebastian@macke.de> wrote:
> On 22/10/2013 9:01 AM, Max Filippov wrote:
>>
>> On Tue, Oct 22, 2013 at 7:45 PM, Sebastian Macke <sebastian@macke.de>
>> wrote:
>>>
>>> Hi Alex,
>>>
>>> I am using a cross-compiling toolchain. It's the easiest way as I have to
>>> compile the image for QEMU anyhow.
>>> http://opencores.org/or1k/OpenRISC_GNU_tool_chain
>>>
>>> Then it's just an "make && make test" in the corresponding
>>> tests/tcg/openrisc folder.
>>>
>>> Inside the virtual machine it would be a little bit more complicated. You
>>> have to compile Linux with the initramfs containing the QEMU test
>>> sources.
>>> Another storage device is currently not supported by the OpenRISC QEMU
>>> emulator.
>>
>> It should be possible to use network, I did a quick check at the time of
>> openrisc port submission, it used to work.
>>
>
> This is true. Via a network file system it should be no problem. But this is
> a very complicated way to test the QEMU tcg part.
> The image containing gcc I am currently using you can download under
> www.simulationcorner.net/vmlinux
> Run it with "qemu-system-or32 -m 128 -kernel vmlinux -nographic"

I can think of an easier way: try using linux user emulation instead of
system emulation, it should make mostly little difference wrt TCG.
It should be "qemu-or32 linux-elf-file-to-run".

-- 
Thanks.
-- Max

Re: [Qemu-devel] [PATCH_v2 0/9] target-openrisc: Corrections and speed improvements

[Sebastian Macke]

On 22/10/2013 8:47 PM, Jia Liu wrote:
> Hi Sebastian,
>
> On Tue, Oct 22, 2013 at 8:12 AM, Sebastian Macke <sebastian@macke.de> wrote:
>> This series is the first part to make the OpenRISC target more
>> reliable and faster.
>> It corrects several severe problems which prevented the OpenRISC emulation
>> for being useful in the past.
>>
>> The patchset was tested with
>>    - the tests/tcg/openrisc tests
>>    - booting Linux 3.11
>>    - run configure + make + gcc of a simple terminal graphic demo called cmatrix
>>    - run benchmark tool nbench in qemu-user mode and in the softmmu mode
>>
>> The speed improvement is less than 10% because the overhead is still to high
>> as the openrisc target does not support translation block chaining.
>> This will be included in one of the future patches.
>>
>> Only the patch which removes the npc and ppc variables removes a little feature
>> from the OpenRISC target but which does not break the specification and will lead to
>> a significant speed improvement.
> For v2 0/9 - 9/9
> Acked-by: Jia Liu <proljc@gmail.com>
>
> I'll add some comment into the code to explain why we separate flags from sr
> and send a pull request if nobody raise a rejection.

Ok great, the next bunch of patches is already in development.

>>
>> Sebastian Macke (9):
>>    target-openrisc: Speed up move instruction
>>    target-openrisc: Remove unnecessary code generated by jump
>>      instructions
>>    target-openrisc: Remove executable flag for every page
>>    target-openrisc: Correct wrong epcr register in interrupt handler
>>    openrisc-timer: Reduce overhead, Separate clock update functions
>>    target-openrisc: Correct memory bounds checking for the tlb buffers
>>    target-openrisc: Separate branch flag from Supervision register
>>    target-openrisc: Complete remove of npc and ppc variables
>>    target-openrisc: Correct carry flag check of l.addc and l.addic test
>>      cases
>>
>>   hw/openrisc/cputimer.c             |  29 ++++--
>>   target-openrisc/cpu.c              |   1 +
>>   target-openrisc/cpu.h              |  16 ++-
>>   target-openrisc/gdbstub.c          |  20 +---
>>   target-openrisc/interrupt.c        |  27 ++---
>>   target-openrisc/interrupt_helper.c |   3 +-
>>   target-openrisc/machine.c          |   3 +-
>>   target-openrisc/mmu.c              |   4 +-
>>   target-openrisc/sys_helper.c       |  74 ++++++--------
>>   target-openrisc/translate.c        | 201 ++++++++++++++++---------------------
>>   tests/tcg/openrisc/test_addc.c     |   8 +-
>>   tests/tcg/openrisc/test_addic.c    |  10 +-
>>   12 files changed, 175 insertions(+), 221 deletions(-)
>>
>> --
>> 1.8.4.1
>>
> Regards,
> Jia

Re: [Qemu-devel] [PATCH_v2 0/9] target-openrisc: Corrections and speed improvements

[Jia Liu]

On Fri, Oct 25, 2013 at 7:23 AM, Sebastian Macke <sebastian@macke.de> wrote:
> On 22/10/2013 8:47 PM, Jia Liu wrote:
>>
>> Hi Sebastian,
>>
>> On Tue, Oct 22, 2013 at 8:12 AM, Sebastian Macke <sebastian@macke.de>
>> wrote:
>>>
>>> This series is the first part to make the OpenRISC target more
>>> reliable and faster.
>>> It corrects several severe problems which prevented the OpenRISC
>>> emulation
>>> for being useful in the past.
>>>
>>> The patchset was tested with
>>>    - the tests/tcg/openrisc tests
>>>    - booting Linux 3.11
>>>    - run configure + make + gcc of a simple terminal graphic demo called
>>> cmatrix
>>>    - run benchmark tool nbench in qemu-user mode and in the softmmu mode
>>>
>>> The speed improvement is less than 10% because the overhead is still to
>>> high
>>> as the openrisc target does not support translation block chaining.
>>> This will be included in one of the future patches.
>>>
>>> Only the patch which removes the npc and ppc variables removes a little
>>> feature
>>> from the OpenRISC target but which does not break the specification and
>>> will lead to
>>> a significant speed improvement.
>>
>> For v2 0/9 - 9/9
>> Acked-by: Jia Liu <proljc@gmail.com>
>>
>> I'll add some comment into the code to explain why we separate flags from
>> sr
>> and send a pull request if nobody raise a rejection.
>
>
> Ok great, the next bunch of patches is already in development.

Then, I'll make one pull request when you finish all you jobs,
please let me know when you finish your last work, is it OK?

>
>
>>>
>>> Sebastian Macke (9):
>>>    target-openrisc: Speed up move instruction
>>>    target-openrisc: Remove unnecessary code generated by jump
>>>      instructions
>>>    target-openrisc: Remove executable flag for every page
>>>    target-openrisc: Correct wrong epcr register in interrupt handler
>>>    openrisc-timer: Reduce overhead, Separate clock update functions
>>>    target-openrisc: Correct memory bounds checking for the tlb buffers
>>>    target-openrisc: Separate branch flag from Supervision register
>>>    target-openrisc: Complete remove of npc and ppc variables
>>>    target-openrisc: Correct carry flag check of l.addc and l.addic test
>>>      cases
>>>
>>>   hw/openrisc/cputimer.c             |  29 ++++--
>>>   target-openrisc/cpu.c              |   1 +
>>>   target-openrisc/cpu.h              |  16 ++-
>>>   target-openrisc/gdbstub.c          |  20 +---
>>>   target-openrisc/interrupt.c        |  27 ++---
>>>   target-openrisc/interrupt_helper.c |   3 +-
>>>   target-openrisc/machine.c          |   3 +-
>>>   target-openrisc/mmu.c              |   4 +-
>>>   target-openrisc/sys_helper.c       |  74 ++++++--------
>>>   target-openrisc/translate.c        | 201
>>> ++++++++++++++++---------------------
>>>   tests/tcg/openrisc/test_addc.c     |   8 +-
>>>   tests/tcg/openrisc/test_addic.c    |  10 +-
>>>   12 files changed, 175 insertions(+), 221 deletions(-)
>>>
>>> --
>>> 1.8.4.1
>>>
>> Regards,
>> Jia
>
>

Re: [Qemu-devel] [PATCH_v2 0/9] target-openrisc: Corrections and speed improvements

[Sebastian Macke]

On 25/10/2013 5:21 PM, Jia Liu wrote:
> On Fri, Oct 25, 2013 at 7:23 AM, Sebastian Macke <sebastian@macke.de> wrote:
>> On 22/10/2013 8:47 PM, Jia Liu wrote:
>>> Hi Sebastian,
>>>
>>> On Tue, Oct 22, 2013 at 8:12 AM, Sebastian Macke <sebastian@macke.de>
>>> wrote:
>>>> This series is the first part to make the OpenRISC target more
>>>> reliable and faster.
>>>> It corrects several severe problems which prevented the OpenRISC
>>>> emulation
>>>> for being useful in the past.
>>>>
>>>> The patchset was tested with
>>>>     - the tests/tcg/openrisc tests
>>>>     - booting Linux 3.11
>>>>     - run configure + make + gcc of a simple terminal graphic demo called
>>>> cmatrix
>>>>     - run benchmark tool nbench in qemu-user mode and in the softmmu mode
>>>>
>>>> The speed improvement is less than 10% because the overhead is still to
>>>> high
>>>> as the openrisc target does not support translation block chaining.
>>>> This will be included in one of the future patches.
>>>>
>>>> Only the patch which removes the npc and ppc variables removes a little
>>>> feature
>>>> from the OpenRISC target but which does not break the specification and
>>>> will lead to
>>>> a significant speed improvement.
>>> For v2 0/9 - 9/9
>>> Acked-by: Jia Liu <proljc@gmail.com>
>>>
>>> I'll add some comment into the code to explain why we separate flags from
>>> sr
>>> and send a pull request if nobody raise a rejection.
>>
>> Ok great, the next bunch of patches is already in development.
> Then, I'll make one pull request when you finish all you jobs,
> please let me know when you finish your last work, is it OK?

Ok, do you want me to send then all patches including the old ones 
together in one patchset? At the moment this are 19 patches.
Keep in mind that the new patches will change much more. And maybe there 
will be discussions of some decisions I made.

But I promise also a speed increase of a factor of 7-10 :)


>>
>>>> Sebastian Macke (9):
>>>>     target-openrisc: Speed up move instruction
>>>>     target-openrisc: Remove unnecessary code generated by jump
>>>>       instructions
>>>>     target-openrisc: Remove executable flag for every page
>>>>     target-openrisc: Correct wrong epcr register in interrupt handler
>>>>     openrisc-timer: Reduce overhead, Separate clock update functions
>>>>     target-openrisc: Correct memory bounds checking for the tlb buffers
>>>>     target-openrisc: Separate branch flag from Supervision register
>>>>     target-openrisc: Complete remove of npc and ppc variables
>>>>     target-openrisc: Correct carry flag check of l.addc and l.addic test
>>>>       cases
>>>>
>>>>    hw/openrisc/cputimer.c             |  29 ++++--
>>>>    target-openrisc/cpu.c              |   1 +
>>>>    target-openrisc/cpu.h              |  16 ++-
>>>>    target-openrisc/gdbstub.c          |  20 +---
>>>>    target-openrisc/interrupt.c        |  27 ++---
>>>>    target-openrisc/interrupt_helper.c |   3 +-
>>>>    target-openrisc/machine.c          |   3 +-
>>>>    target-openrisc/mmu.c              |   4 +-
>>>>    target-openrisc/sys_helper.c       |  74 ++++++--------
>>>>    target-openrisc/translate.c        | 201
>>>> ++++++++++++++++---------------------
>>>>    tests/tcg/openrisc/test_addc.c     |   8 +-
>>>>    tests/tcg/openrisc/test_addic.c    |  10 +-
>>>>    12 files changed, 175 insertions(+), 221 deletions(-)
>>>>
>>>> --
>>>> 1.8.4.1
>>>>
>>> Regards,
>>> Jia
>>

Re: [Qemu-devel] [PATCH_v2 0/9] target-openrisc: Corrections and speed improvements

[Jia Liu]

Hi Sebastian,

On Mon, Oct 28, 2013 at 9:56 AM, Sebastian Macke <sebastian@macke.de> wrote:
> On 25/10/2013 5:21 PM, Jia Liu wrote:
>>
>> On Fri, Oct 25, 2013 at 7:23 AM, Sebastian Macke <sebastian@macke.de>
>> wrote:
>>>
>>> On 22/10/2013 8:47 PM, Jia Liu wrote:
>>>>
>>>> Hi Sebastian,
>>>>
>>>> On Tue, Oct 22, 2013 at 8:12 AM, Sebastian Macke <sebastian@macke.de>
>>>> wrote:
>>>>>
>>>>> This series is the first part to make the OpenRISC target more
>>>>> reliable and faster.
>>>>> It corrects several severe problems which prevented the OpenRISC
>>>>> emulation
>>>>> for being useful in the past.
>>>>>
>>>>> The patchset was tested with
>>>>>     - the tests/tcg/openrisc tests
>>>>>     - booting Linux 3.11
>>>>>     - run configure + make + gcc of a simple terminal graphic demo
>>>>> called
>>>>> cmatrix
>>>>>     - run benchmark tool nbench in qemu-user mode and in the softmmu
>>>>> mode
>>>>>
>>>>> The speed improvement is less than 10% because the overhead is still to
>>>>> high
>>>>> as the openrisc target does not support translation block chaining.
>>>>> This will be included in one of the future patches.
>>>>>
>>>>> Only the patch which removes the npc and ppc variables removes a little
>>>>> feature
>>>>> from the OpenRISC target but which does not break the specification and
>>>>> will lead to
>>>>> a significant speed improvement.
>>>>
>>>> For v2 0/9 - 9/9
>>>> Acked-by: Jia Liu <proljc@gmail.com>
>>>>
>>>> I'll add some comment into the code to explain why we separate flags
>>>> from
>>>> sr
>>>> and send a pull request if nobody raise a rejection.
>>>
>>>
>>> Ok great, the next bunch of patches is already in development.
>>
>> Then, I'll make one pull request when you finish all you jobs,
>> please let me know when you finish your last work, is it OK?
>
>
> Ok, do you want me to send then all patches including the old ones together
> in one patchset? At the moment this are 19 patches.

Your call.

> Keep in mind that the new patches will change much more. And maybe there
> will be discussions of some decisions I made.
>
> But I promise also a speed increase of a factor of 7-10 :)

When you summit a patch, I'll be always there :)

>
>
>
>>>
>>>>> Sebastian Macke (9):
>>>>>     target-openrisc: Speed up move instruction
>>>>>     target-openrisc: Remove unnecessary code generated by jump
>>>>>       instructions
>>>>>     target-openrisc: Remove executable flag for every page
>>>>>     target-openrisc: Correct wrong epcr register in interrupt handler
>>>>>     openrisc-timer: Reduce overhead, Separate clock update functions
>>>>>     target-openrisc: Correct memory bounds checking for the tlb buffers
>>>>>     target-openrisc: Separate branch flag from Supervision register
>>>>>     target-openrisc: Complete remove of npc and ppc variables
>>>>>     target-openrisc: Correct carry flag check of l.addc and l.addic
>>>>> test
>>>>>       cases
>>>>>
>>>>>    hw/openrisc/cputimer.c             |  29 ++++--
>>>>>    target-openrisc/cpu.c              |   1 +
>>>>>    target-openrisc/cpu.h              |  16 ++-
>>>>>    target-openrisc/gdbstub.c          |  20 +---
>>>>>    target-openrisc/interrupt.c        |  27 ++---
>>>>>    target-openrisc/interrupt_helper.c |   3 +-
>>>>>    target-openrisc/machine.c          |   3 +-
>>>>>    target-openrisc/mmu.c              |   4 +-
>>>>>    target-openrisc/sys_helper.c       |  74 ++++++--------
>>>>>    target-openrisc/translate.c        | 201
>>>>> ++++++++++++++++---------------------
>>>>>    tests/tcg/openrisc/test_addc.c     |   8 +-
>>>>>    tests/tcg/openrisc/test_addic.c    |  10 +-
>>>>>    12 files changed, 175 insertions(+), 221 deletions(-)
>>>>>
>>>>> --
>>>>> 1.8.4.1
>>>>>
>>>> Regards,
>>>> Jia
>>>
>>>
>