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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	Jia Liu <proljc@gmail.com>, Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [PATCH] target/mips: Raise exception when DINSV opcode used with DSP disabled
Date: Sat, 19 Jun 2021 20:01:28 +0200	[thread overview]
Message-ID: <526fce82-b5fb-8f93-9469-3a0b64edf53b@amsat.org> (raw)
In-Reply-To: <20210529165443.1114402-1-f4bug@amsat.org>

On 5/29/21 6:54 PM, Philippe Mathieu-Daudé wrote:
> Per the "MIPS® DSP Module for MIPS64 Architecture" manual, rev. 3.02,
> Table 5.3 "SPECIAL3 Encoding of Function Field for DSP Module":
> 
>   If the Module/ASE is not implemented, executing such an instruction
>   must cause a Reserved Instruction Exception.
> 
> The DINSV instruction lists the following exceptions:
> - Reserved Instruction
> - DSP Disabled
> 
> If the MIPS core doesn't support the DSP module, or the DSP is
> disabled, do not handle the '$rt = $0' case as a no-op but raise
> the proper exception instead.
> 
> Cc: Jia Liu <proljc@gmail.com>
> Fixes: 1cb6686cf92 ("target-mips: Add ASE DSP bit/manipulation instructions")
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/tcg/translate.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

Thanks, applied to mips-next.


      parent reply	other threads:[~2021-06-19 18:03 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-29 16:54 [PATCH] target/mips: Raise exception when DINSV opcode used with DSP disabled Philippe Mathieu-Daudé
2021-05-30  0:54 ` Richard Henderson
2021-06-19 18:01 ` Philippe Mathieu-Daudé [this message]

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