From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40237) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VbbLJ-0002L8-Mp for qemu-devel@nongnu.org; Wed, 30 Oct 2013 15:22:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VbbLB-0006QJ-3K for qemu-devel@nongnu.org; Wed, 30 Oct 2013 15:22:13 -0400 Received: from www11.your-server.de ([213.133.104.11]:46133) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VbbLA-0006Pv-Sl for qemu-devel@nongnu.org; Wed, 30 Oct 2013 15:22:05 -0400 Message-ID: <52715C59.2080109@macke.de> Date: Wed, 30 Oct 2013 12:22:01 -0700 From: Sebastian Macke MIME-Version: 1.0 References: <1383073495-5332-1-git-send-email-sebastian@macke.de> <1383073495-5332-10-git-send-email-sebastian@macke.de> <52714C69.5030806@twiddle.net> In-Reply-To: <52714C69.5030806@twiddle.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 09/13] target-openrisc: Add CPU which neglects Carry and Overflow Flag List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org, proljc@gmail.com On 30/10/2013 11:14 AM, Richard Henderson wrote: > On 10/29/2013 12:04 PM, Sebastian Macke wrote: >> The carry and overflag and the instructions l.addc and l.addic >> are never used in the toolchain. Linux and gcc compiled software >> don't need them. > Really? That's quite surprising. Yes, Really. :) >> To speed up the emulation a cpu was added which >> neglects the flags for l.addi, l.add, l.sub and >> generates an illegal instruction error for l.addic and l.addc > I'm somewhat shocked that l.addc is never used. To me that points > to a missed opportunity in the compiler. Yes > It would be much better to simply improve handling of these bits. > In a previous patch set you broke out SR[F] to its own variable; > I suggest that you do the same for SR[CY] and SR[OV]. > > If you can implement add et al without branches, the TCG optimizer > will be able to do a good job eliminating shadowed computation. > > A good example to follow here is the ARM implementation. Have a > look at the gen_add_CC and gen_sub_CC functions especially. Note > that the overflow bit is stored in bit 31 of cpu_VF and the other > bits of cpu_VF are ignored. > > > r~ I would like to implement lazy flags or at least change the big bunch of code which is there right now. But for this patchset I want to keep it that way and change the whole flag handling in one of the next patches. There is almost nothing available to test the flags right now. And I have to keep an eye on the delayed slot. So this is more work than you might expect.