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Subject: Re: [Qemu-devel] [PATCH 05/13] target-openrisc: Remove TLB flush on
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To: Sebastian Macke <sebastian@macke.de>, Peter Maydell <peter.maydell@linaro.org>
Cc: openrisc@openrisc.net, openrisc@lists.opencores.org, QEMU Developers <qemu-devel@nongnu.org>, Ethan Hunt <proljc@gmail.com>

On 10/29/2013 03:41 PM, Sebastian Macke wrote:
> 
> What is included in the tb hash? The virtual pc + physical page + the tb_flags?
> Not the mmu_index?

What's included is everything you return from cpu_get_tb_cpu_state.

Note that cs_base is an interesting case.  On i386 real mode, it's
what the name implies -- the code segment base.  On sparc, we (ab)use
it to handle an insn beginning from a delay slot.

(On Sparc, pc is the current insn, and npc is the next insn.  For
straight-line code, npc = pc + 4.  After a branch, npc is the branch
target.  After every insn, the cpu copies pc = npc.)

See my response to Peter for info re mmu_index.


r~