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Wed, 26 Nov 2025 05:12:31 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SN1PEPF0002BA4E.mail.protection.outlook.com (10.167.242.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9366.7 via Frontend Transport; Wed, 26 Nov 2025 05:12:32 +0000 Received: from [10.85.40.187] (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 25 Nov 2025 23:12:29 -0600 Message-ID: <5275a84e-5d83-491b-9c0b-a97c9c345ba1@amd.com> Date: Wed, 26 Nov 2025 10:42:27 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] amd_iommu: Turn on XT support only when guest has enabled it Content-Language: en-US To: Alejandro Jimenez , CC: , , , , , "Vasant Hegde" References: <20251118082403.3455-1-sarunkod@amd.com> <20251118082403.3455-3-sarunkod@amd.com> <40b36c5f-5e47-48a4-bd39-667040f53a05@oracle.com> From: Sairaj Kodilkar In-Reply-To: <40b36c5f-5e47-48a4-bd39-667040f53a05@oracle.com> Content-Type: text/plain; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:satlexmb07.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(1800799024)(82310400026)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Nov 2025 05:12:32.3936 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 60e37c45-5135-4d57-a25c-08de2caa676e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6601 Received-SPF: permerror client-ip=40.107.200.51; envelope-from=Sairaj.ArunKodilkar@amd.com; helo=CH5PR02CU005.outbound.protection.outlook.com X-Spam_score_int: -22 X-Spam_score: -2.3 X-Spam_bar: -- X-Spam_report: (-2.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.152, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/26/2025 4:34 AM, Alejandro Jimenez wrote: > Hi Sairaj, > > I have a couple of suggestions, and one addition I believe is needed > in the code, but overall looks good. > > On 11/18/25 3:24 AM, Sairaj Kodilkar wrote: >> Current code uses 32 bit cpu destination irrespective of the fact that > > s/"32 bit cpu destination"/"32-bit destination ID" > > I think it fits the language used by the spec slightly better. > >> guest has enabled xt support through control register[XTEn] and > > a guest has enabled x2APIC support ... > > I think it is better to replace "xt" above with "x2APIC", which > describes what the XT feature is/does. > >> completely depends on command line parameter xtsup=on. This is not a >> correct hardware behaviour and can cause problems in the guest which has >> not enabled XT mode. >> >> Introduce new flag "xten", which is enabled when guest writes 1 to the >> control register bit 50 (XTEn). >> >> Signed-off-by: Sairaj Kodilkar >> --- >>   hw/i386/amd_iommu.c | 3 ++- >>   hw/i386/amd_iommu.h | 4 +++- >>   2 files changed, 5 insertions(+), 2 deletions(-) >> >> diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c >> index a9ee7150ef17..7f08fc31111a 100644 >> --- a/hw/i386/amd_iommu.c >> +++ b/hw/i386/amd_iommu.c >> @@ -1548,6 +1548,7 @@ static void >> amdvi_handle_control_write(AMDVIState *s) >>       s->cmdbuf_enabled = s->enabled && !!(control & >>                           AMDVI_MMIO_CONTROL_CMDBUFLEN); >>       s->ga_enabled = !!(control & AMDVI_MMIO_CONTROL_GAEN); >> +    s->xten = !!(control & AMDVI_MMIO_CONTROL_XTEN) && s->xtsup; > > I think we should also include a new xten field in > vmstate_amdvi_sysbus_migratable, to ensure the remapping behavior > stays consistent after migration. i.e. Right I completely missed this > > diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c > index 9bf36ef608..5940011ef1 100644 > --- a/hw/i386/amd_iommu.c > +++ b/hw/i386/amd_iommu.c > @@ -2452,6 +2452,7 @@ static const VMStateDescription > vmstate_amdvi_sysbus_migratable = { >        /* Updated in  amdvi_handle_control_write() */ >        VMSTATE_BOOL(enabled, AMDVIState), >        VMSTATE_BOOL(ga_enabled, AMDVIState), > +      VMSTATE_BOOL(xten, AMDVIState), >        /* bool ats_enabled is obsolete */ >        VMSTATE_UNUSED(1), /* was ats_enabled */ >        VMSTATE_BOOL(cmdbuf_enabled, AMDVIState), > > There is more work to do there, but this seems straightforward. > >>       /* update the flags depending on the control register */ >>       if (s->cmdbuf_enabled) { >> @@ -2020,7 +2021,7 @@ static int amdvi_int_remap_ga(AMDVIState *iommu, >>       irq->vector = irte.hi.fields.vector; >>       irq->dest_mode = irte.lo.fields_remap.dm; >>       irq->redir_hint = irte.lo.fields_remap.rq_eoi; >> -    if (iommu->xtsup) { >> +    if (iommu->xten) { >>           irq->dest = irte.lo.fields_remap.destination | >>                       (irte.hi.fields.destination_hi << 24); >>       } else { >> diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h >> index 302ccca5121f..32467d0bc241 100644 >> --- a/hw/i386/amd_iommu.h >> +++ b/hw/i386/amd_iommu.h >> @@ -106,6 +106,7 @@ >>   #define AMDVI_MMIO_CONTROL_COMWAITINTEN   (1ULL << 4) >>   #define AMDVI_MMIO_CONTROL_CMDBUFLEN      (1ULL << 12) >>   #define AMDVI_MMIO_CONTROL_GAEN           (1ULL << 17) >> +#define AMDVI_MMIO_CONTROL_XTEN           (1ULL << 50) >>     /* MMIO status register bits */ >>   #define AMDVI_MMIO_STATUS_CMDBUF_RUN  (1 << 4) >> @@ -418,7 +419,8 @@ struct AMDVIState { >>         /* Interrupt remapping */ >>       bool ga_enabled; >> -    bool xtsup; >> +    bool xtsup;     /* xtsup=on command line */ >> +    bool xten;      /* Enable x2apic */ > > I'd reword the comment to indicate this what the guest toggles for > enabling x2apic. e.g. > > bool xten;      /* guest controlled, x2apic mode enabled */ > > I am aware that other fields that are also "guest controlled" don't > have similar comments. My idea is to highlight that the xten is > "toggled" at runtime, and is different from xtsup, which is a > capability inherent to the hardware being emulated and set during > initialization. Yep that makes sense Thanks Sairaj