From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54435) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VdBj0-0002jj-Vk for qemu-devel@nongnu.org; Sun, 03 Nov 2013 23:25:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VdBis-0003UR-Gf for qemu-devel@nongnu.org; Sun, 03 Nov 2013 23:25:14 -0500 Received: from mail-pb0-x233.google.com ([2607:f8b0:400e:c01::233]:36803) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VdBis-0003Ti-8q for qemu-devel@nongnu.org; Sun, 03 Nov 2013 23:25:06 -0500 Received: by mail-pb0-f51.google.com with SMTP id xa7so790551pbc.10 for ; Sun, 03 Nov 2013 20:25:05 -0800 (PST) Sender: Richard Henderson Message-ID: <5277219B.4010809@twiddle.net> Date: Mon, 04 Nov 2013 14:24:59 +1000 From: Richard Henderson MIME-Version: 1.0 References: <1383250929-10288-1-git-send-email-rth@twiddle.net> <1383250929-10288-5-git-send-email-rth@twiddle.net> <20131103225615.GA2712@ohm.rr44.fr> <5276DD74.4030801@twiddle.net> In-Reply-To: <5276DD74.4030801@twiddle.net> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 04/20] tcg-ia64: Simplify brcond List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno Cc: qemu-devel@nongnu.org, aliguori@amazon.com On 11/04/2013 09:34 AM, Richard Henderson wrote: > On 11/03/2013 12:56 PM, Aurelien Jarno wrote: >> That said the implementation is likely wrong as with this patch applied, >> qemu-system-x86_64 is not even able to execute seabios to the first >> printed message. Please do at least basic testing. > > Really? I'll look into it. > > I do basic testing -- arm, sparc, alpha. Those are the ones that can > usefully boot via serial console instead of having to set up a tunnel > for a vnc viewer. Yes indeed, there's a bug. This additional patch is required: diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c index 2fdc38a..e0413d9 100644 --- a/tcg/ia64/tcg-target.c +++ b/tcg/ia64/tcg-target.c @@ -2359,7 +2359,7 @@ static const TCGTargetOpDef ia64_op_defs[] = { { INDEX_op_bswap32_i64, { "r", "rZ" } }, { INDEX_op_bswap64_i64, { "r", "rZ" } }, - { INDEX_op_brcond_i64, { "rI", "rI" } }, + { INDEX_op_brcond_i64, { "rZ", "rZ" } }, { INDEX_op_setcond_i64, { "r", "rZ", "rZ" } }, { INDEX_op_movcond_i64, { "r", "rZ", "rZ", "rI", "rI" } }, I managed to change the constraints for brcond_i32 but forget its brother. Naturally, arm and sparc don't excercise brcond_i64, and as it happens alpha would have only generated brcond_i64 vs zero and not seen the problem. Will be fixed in v3. Do you see anything else in the patch set? r~