From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34880) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VghpF-0002Fz-3w for qemu-devel@nongnu.org; Wed, 13 Nov 2013 16:18:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Vghp9-0007BP-GK for qemu-devel@nongnu.org; Wed, 13 Nov 2013 16:18:13 -0500 Received: from smtp3-g21.free.fr ([2a01:e0c:1:1599::12]:44418) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Vghp8-00077z-SN for qemu-devel@nongnu.org; Wed, 13 Nov 2013 16:18:07 -0500 Message-ID: <5283EC80.7000604@reactos.org> Date: Wed, 13 Nov 2013 22:17:52 +0100 From: =?UTF-8?B?SGVydsOpIFBvdXNzaW5lYXU=?= MIME-Version: 1.0 References: <1383603977-7003-1-git-send-email-hpoussin@reactos.org> <527A15B4.9070702@redhat.com> In-Reply-To: <527A15B4.9070702@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 1.7] mips jazz: do not raise data bus exception when accessing invalid addresses List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , aliguori@amazon.com, Aurelien Jarno Ping for 1.7 Paolo Bonzini a =C3=A9crit : > Il 04/11/2013 23:26, Herv=C3=A9 Poussineau ha scritto: >> MIPS Jazz chipset doesn't seem to raise data bus exceptions on invalid= accesses. >> However, there is no easy way to prevent them. Creating a big memory r= egion >> for the whole address space doesn't prevent memory core to directly ca= ll >> unassigned_mem_read/write which in turn call cpu->do_unassigned_access= , >> which (for MIPS CPU) raise an data bus exception. >=20 > Creating a big MMIO region would work, but it wouldn't let you trap > execution accesses. >=20 >> This fixes a MIPS Jazz regression introduced in c658b94f6e8c206c59d02a= a6fbac285b86b53d2c. >> >> Signed-off-by: Herv=C3=A9 Poussineau >> --- >> This fixes a known regression in QEMU 1.6. Let it be fixed as soon as = possible. >> >> hw/mips/mips_jazz.c | 24 ++++++++++++++++++++++++ >> 1 file changed, 24 insertions(+) >> >> diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c >> index 49bdd02..5f6dd9f 100644 >> --- a/hw/mips/mips_jazz.c >> +++ b/hw/mips/mips_jazz.c >> @@ -108,6 +108,18 @@ static void cpu_request_exit(void *opaque, int ir= q, int level) >> } >> } >> =20 >> +static CPUUnassignedAccess real_do_unassigned_access; >> +static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr= , >> + bool is_write, bool is_exe= c, >> + int opaque, unsigned size) >> +{ >> + if (!is_exec) { >> + /* ignore invalid access (ie do not raise exception) */ >> + return; >> + } >> + (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque= , size); >> +} >> + >> static void mips_jazz_init(MemoryRegion *address_space, >> MemoryRegion *address_space_io, >> ram_addr_t ram_size, >> @@ -117,6 +129,7 @@ static void mips_jazz_init(MemoryRegion *address_s= pace, >> char *filename; >> int bios_size, n; >> MIPSCPU *cpu; >> + CPUClass *cc; >> CPUMIPSState *env; >> qemu_irq *rc4030, *i8259; >> rc4030_dma *dmas; >> @@ -154,6 +167,17 @@ static void mips_jazz_init(MemoryRegion *address_= space, >> env =3D &cpu->env; >> qemu_register_reset(main_cpu_reset, cpu); >> =20 >> + /* Chipset returns 0 in invalid reads and do not raise data excep= tions. >> + * However, we can't simply add a global memory region to catch >> + * everything, as memory core directly call unassigned_mem_read/w= rite >> + * on some invalid accesses, which call do_unassigned_access on t= he >> + * CPU, which raise an exception. >> + * Handle that case by hijacking the do_unassigned_access method = on >> + * the CPU, and do not raise exceptions for data access. */ >> + cc =3D CPU_GET_CLASS(cpu); >> + real_do_unassigned_access =3D cc->do_unassigned_access; >> + cc->do_unassigned_access =3D mips_jazz_do_unassigned_access; >> + >> /* allocate RAM */ >> memory_region_init_ram(ram, NULL, "mips_jazz.ram", ram_size); >> vmstate_register_ram_global(ram); >> >=20 > Reviewed-by: Paolo Bonzini >=20 > Please remember to add 1.7 in the subject at this time. >=20 > Paolo >=20