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Date: Mon, 18 Nov 2013 14:24:09 +0100
From: Claudio Fontana <claudio.fontana@linaro.org>
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Subject: Re: [Qemu-devel] [PATCH 14/60] AArch64: Add orr instruction
	emulation
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: Michael Matz <matz@suse.de>, QEMU Developers <qemu-devel@nongnu.org>, Alexander Graf <agraf@suse.de>, Dirk Mueller <dmueller@suse.de>, Laurent Desnogues <laurent.desnogues@gmail.com>, Christoffer Dall <christoffer.dall@linaro.org>, Richard Henderson <rth@twiddle.net>

On 11/18/2013 02:15 PM, Peter Maydell wrote:
> On 18 November 2013 13:12, Michael Matz <matz@suse.de> wrote:
>> Hi,
>>
>> On Mon, 18 Nov 2013, Claudio Fontana wrote:
>>
>>>>> +    case 3:
>>>>> +        tcg_gen_rotr_i64(r, cpu_reg(reg), tcg_shift);
>>>>> +        break;
>>>>
>>>> Incorrect rotate for 32bit?
>>
>> 32bit rotates and shifts were fixed in a patch later than the 60er series
>> Alex posted.  See attached.  (Generally there are many fixes to emulated
>> instructions in that branch)
> 
> I think we're going to need to look through and fold in those
> fixes, otherwise we'll end up reduplicating that work in the
> course of code review :-(
> 
> -- PMM
> 

Thanks all.

Regarding the access to registers in 32 bit mode, and the consequent write to registers in 32 bit mode,
I am investigating how to do it a little bit more general, in the sense that generally when we access registers in 32bit mode
we will (often) need to ignore the upper bits of the source register, and write zero to the destination register.
Not always but often. This could be done once for all to reduce the chances of mistakes.

C.