Re: [Qemu-devel] [PULL 11/13] target-i386: forward CPUID cache leaves when -cpu host is used

[Peter Lieven <lieven-lists@dlhnet.de>]

I do not know, but this patch might introduce a regression.

If I specify: -smp 2,sockets=1,cores=2,threads=1 to a Windows 2012 R2 Server it crashes
at boot time. -smp 2 works.

git bisect start
# good: [62ecc3a0e3c77a4944c92a02dd7fae2ab1f2290d] Update VERSION for 1.6.1 release
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# bad: [964668b03d26f0b5baa5e5aff0c966f4fcb76e9e] Update version for 1.7.0-rc0 release
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# good: [1ee2daeb6448312d6d0e22175f5c1b9b01f8974c] Update version for 1.6.0
git bisect good 1ee2daeb6448312d6d0e22175f5c1b9b01f8974c
# bad: [03cfd8faa7ffb7201e2949b99c2f35b1fef7078b] linux-user: add support of binfmt_misc 'O' flag
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# good: [5a93d5c2abc719bd44f6c9fbeed88d3cae712606] Merge remote-tracking branch 'mjt/trivial-patches' into staging
git bisect good 5a93d5c2abc719bd44f6c9fbeed88d3cae712606
# good: [a27292b5d7545509bfa171922516d2033c570205] virtio-scsi: Make type virtio-scsi-common abstract
git bisect good a27292b5d7545509bfa171922516d2033c570205
# good: [469936ae0a9891b2de7e46743f683535b0819bee] target-i386: Fix segment cache dump
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# bad: [3e4be9c29784df09c364b52a55e826a0b05b950e] Merge remote-tracking branch 'qemu-kvm/uq/master' into staging
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# good: [2571f8f5fbaea5dc3bdcd84737f109b459576e90] Merge remote-tracking branch 'spice/spice.v74' into staging
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# good: [c5daeae1b4ddff97d605bd954a7c2a2b2cf6040f] linux-headers: update to 3.11
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# good: [ceae18bd74e8940ff79935a257c72e665b084bcc] lsi: add 53C810 variant
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# bad: [f010bc643a2759e87e989c3e4e85f15ec71ae98f] target-i386: add feature kvm_pv_unhalt
git bisect bad f010bc643a2759e87e989c3e4e85f15ec71ae98f
# bad: [4f2656079f903efcd0d8224cbc79170ad3ee5b70] linux-headers: update to 3.12-rc1
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# bad: [787aaf5703a702094f395db6795e74230282cd62] target-i386: forward CPUID cache leaves when -cpu host is used
git bisect bad 787aaf5703a702094f395db6795e74230282cd62

Peter

On 20.09.2013 18:24, Paolo Bonzini wrote:
> From: Benoît Canet <benoit@irqsave.net>
>
> Some users running cpu intensive tasks checking the cache CPUID leaves at
> startup and making decisions based on the result reported that the guest was
> not reflecting the host CPUID leaves when -cpu host is used.
>
> This patch fix this.
>
> Signed-off-by: Benoît Canet <benoit@irqsave.net>
> [Rename new field to cache_info_passthrough - Paolo]
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>   target-i386/cpu-qom.h |  3 +++
>   target-i386/cpu.c     | 19 +++++++++++++++++++
>   2 files changed, 22 insertions(+)
>
> diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h
> index c4447c2..f4fab15 100644
> --- a/target-i386/cpu-qom.h
> +++ b/target-i386/cpu-qom.h
> @@ -70,6 +70,9 @@ typedef struct X86CPU {
>       bool hyperv_relaxed_timing;
>       int hyperv_spinlock_attempts;
>   
> +    /* if true the CPUID code directly forward host cache leaves to the guest */
> +    bool cache_info_passthrough;
> +
>       /* Features that were filtered out because of missing host capabilities */
>       uint32_t filtered_features[FEATURE_WORDS];
>   
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index c36345e..46edd75 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -486,6 +486,7 @@ typedef struct x86_def_t {
>       int stepping;
>       FeatureWordArray features;
>       char model_id[48];
> +    bool cache_info_passthrough;
>   } x86_def_t;
>   
>   #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
> @@ -1139,6 +1140,7 @@ static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
>       assert(kvm_enabled());
>   
>       x86_cpu_def->name = "host";
> +    x86_cpu_def->cache_info_passthrough = true;
>       host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
>       x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
>   
> @@ -1888,6 +1890,7 @@ static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp)
>       env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
>       env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
>       env->cpuid_xlevel2 = def->xlevel2;
> +    cpu->cache_info_passthrough = def->cache_info_passthrough;
>   
>       object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
>   }
> @@ -2062,6 +2065,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
>           break;
>       case 2:
>           /* cache info: needed for Pentium Pro compatibility */
> +        if (cpu->cache_info_passthrough) {
> +            host_cpuid(index, 0, eax, ebx, ecx, edx);
> +            break;
> +        }
>           *eax = 1; /* Number of CPUID[EAX=2] calls required */
>           *ebx = 0;
>           *ecx = 0;
> @@ -2071,6 +2078,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
>           break;
>       case 4:
>           /* cache info: needed for Core compatibility */
> +        if (cpu->cache_info_passthrough) {
> +            host_cpuid(index, count, eax, ebx, ecx, edx);
> +            break;
> +        }
>           if (cs->nr_cores > 1) {
>               *eax = (cs->nr_cores - 1) << 26;
>           } else {
> @@ -2228,6 +2239,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
>           break;
>       case 0x80000005:
>           /* cache info (L1 cache) */
> +        if (cpu->cache_info_passthrough) {
> +            host_cpuid(index, 0, eax, ebx, ecx, edx);
> +            break;
> +        }
>           *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
>                  (L1_ITLB_2M_ASSOC <<  8) | (L1_ITLB_2M_ENTRIES);
>           *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
> @@ -2239,6 +2254,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
>           break;
>       case 0x80000006:
>           /* cache info (L2 cache) */
> +        if (cpu->cache_info_passthrough) {
> +            host_cpuid(index, 0, eax, ebx, ecx, edx);
> +            break;
> +        }
>           *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
>                  (L2_DTLB_2M_ENTRIES << 16) | \
>                  (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \