From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44327) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VikCc-0002yu-PF for qemu-devel@nongnu.org; Tue, 19 Nov 2013 07:14:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VikCW-0006AC-Ln for qemu-devel@nongnu.org; Tue, 19 Nov 2013 07:14:46 -0500 Received: from mx1.redhat.com ([209.132.183.28]:15341) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VikCW-0006A8-CZ for qemu-devel@nongnu.org; Tue, 19 Nov 2013 07:14:40 -0500 Message-ID: <528B561C.9070200@redhat.com> Date: Tue, 19 Nov 2013 13:14:20 +0100 From: Paolo Bonzini MIME-Version: 1.0 References: <1379694292-1601-1-git-send-email-pbonzini@redhat.com> <1379694292-1601-12-git-send-email-pbonzini@redhat.com> <528A310A.60607@dlhnet.de> <528A3422.1030701@kamp.de> <528A3C4A.4090001@redhat.com> <528B3C86.3030309@kamp.de> <528B41A5.1080504@redhat.com> <528B53A6.3030204@kamp.de> In-Reply-To: <528B53A6.3030204@kamp.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PULL 11/13] target-i386: forward CPUID cache leaves when -cpu host is used List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Lieven Cc: qemu-devel@nongnu.org, Anthony Liguori , =?UTF-8?B?QmVub8OudCBDYW5ldA==?= Il 19/11/2013 13:03, Peter Lieven ha scritto: >> >> Can you test which of these two work? But I agree it's best to disable >> cache-leaf forwarding. > The first does make windows boot again and it calculates a > correct combination of cpus, threads, cores and sockets. But > I think the reason it boots is because cores=threads=1. > > As its more intuitive (I think) I would prefer your "cores over threads > over socket ". > The last thing I would think of is emulating more than 1 socket. -smp N > would then mean, N cores, no hyper-threading, 1 socket. After looking more at the docs, I think I found the bug. Can you test this? diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 864c80e..16d4db1 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2086,14 +2086,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, /* cache info: needed for Core compatibility */ if (cpu->cache_info_passthrough) { host_cpuid(index, count, eax, ebx, ecx, edx); - break; - } - if (cs->nr_cores > 1) { - *eax = (cs->nr_cores - 1) << 26; + *eax &= ~0xFC000000; } else { *eax = 0; - } - switch (count) { + switch (count) { case 0: /* L1 dcache info */ *eax |= CPUID_4_TYPE_DCACHE | \ CPUID_4_LEVEL(1) | \ @@ -2118,9 +2114,6 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *eax |= CPUID_4_TYPE_UNIFIED | \ CPUID_4_LEVEL(2) | \ CPUID_4_SELF_INIT_LEVEL; - if (cs->nr_threads > 1) { - *eax |= (cs->nr_threads - 1) << 14; - } *ebx = (L2_LINE_SIZE - 1) | \ ((L2_PARTITIONS - 1) << 12) | \ ((L2_ASSOCIATIVITY - 1) << 22); @@ -2133,6 +2126,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *ecx = 0; *edx = 0; break; + } + } + + /* We give out APIC IDs ourselves, so force bits 31..26 even for "-cpu host". */ + if (cs->nr_cores > 1) { + *eax |= (cs->nr_cores - 1) << 26; } break; case 5: Paolo