From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44891) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ViouJ-0001mB-3Q for qemu-devel@nongnu.org; Tue, 19 Nov 2013 12:16:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ViouD-0005Ta-1X for qemu-devel@nongnu.org; Tue, 19 Nov 2013 12:16:10 -0500 Received: from mail-ee0-f48.google.com ([74.125.83.48]:40320) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ViouC-0005TL-Kw for qemu-devel@nongnu.org; Tue, 19 Nov 2013 12:16:04 -0500 Received: by mail-ee0-f48.google.com with SMTP id e49so3360865eek.7 for ; Tue, 19 Nov 2013 09:16:03 -0800 (PST) Message-ID: <528B9D0E.2060107@linaro.org> Date: Tue, 19 Nov 2013 18:17:02 +0100 From: Claudio Fontana MIME-Version: 1.0 References: <1380242934-20953-1-git-send-email-agraf@suse.de> <1380242934-20953-27-git-send-email-agraf@suse.de> In-Reply-To: <1380242934-20953-27-git-send-email-agraf@suse.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 26/60] AArch64: Add ADR instruction emulation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: Peter Maydell , Michael Matz , qemu-devel@nongnu.org, Dirk Mueller , Laurent Desnogues , Christoffer Dall , Richard Henderson Hello all, On 09/27/2013 02:48 AM, Alexander Graf wrote: > This patch adds emulation support for the adr instruction. > > Signed-off-by: Alexander Graf > --- > target-arm/translate-a64.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c > index bc91324..00eda0f 100644 > --- a/target-arm/translate-a64.c > +++ b/target-arm/translate-a64.c > @@ -943,6 +943,27 @@ static void handle_insg(DisasContext *s, uint32_t insn) > simd_st(cpu_reg(rn), freg_offs_d + idx, size); > } > > +/* PC relative address calculation */ > +static void handle_adr(DisasContext *s, uint32_t insn) > +{ > + int reg = get_reg(insn); > + int is_page = get_bits(insn, 31, 1); > + uint64_t imm; > + uint64_t base; > + > + imm = get_sbits(insn, 5, 19) << 2; > + imm |= get_bits(insn, 29, 2); > + > + base = s->pc - 4; > + if (is_page) { > + /* ADRP (page based) */ > + base &= ~0xFFFULL; > + imm <<= 12; > + } > + > + tcg_gen_movi_i64(cpu_reg(reg), base + imm); > +} > + does this work with negative values? The spec says to SignExtend: if page then imm = SignExtend(immhi:immlo:Zeros(12), 64); else imm = SignExtend(immhi:immlo, 64); /*...*/ maybe Michael you know if this is an issue in practice? If I want to get a negative PC relative offset, how does this work? Claudio > /* SIMD ORR */ > static void handle_simdorr(DisasContext *s, uint32_t insn) > { > @@ -1365,6 +1386,9 @@ void disas_a64_insn(CPUARMState *env, DisasContext *s) > unallocated_encoding(s); > } > break; > + case 0x10: > + handle_adr(s, insn); > + break; > default: > unallocated_encoding(s); > break; >