From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44256) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VjE9B-0005mo-BR for qemu-devel@nongnu.org; Wed, 20 Nov 2013 15:13:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VjE96-0000dN-3O for qemu-devel@nongnu.org; Wed, 20 Nov 2013 15:13:13 -0500 Received: from smtp1-g21.free.fr ([212.27.42.1]:41273) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VjE95-0000cm-FI for qemu-devel@nongnu.org; Wed, 20 Nov 2013 15:13:08 -0500 Message-ID: <528D179C.4030808@reactos.org> Date: Wed, 20 Nov 2013 21:12:12 +0100 From: =?UTF-8?B?SGVydsOpIFBvdXNzaW5lYXU=?= MIME-Version: 1.0 References: <1383603977-7003-1-git-send-email-hpoussin@reactos.org> <527A15B4.9070702@redhat.com> <5283EC80.7000604@reactos.org> In-Reply-To: <5283EC80.7000604@reactos.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH for-1.7] mips jazz: do not raise data bus exception when accessing invalid addresses List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?B?SGVydsOpIFBvdXNzaW5lYXU=?= , qemu-devel@nongnu.org, Aurelien Jarno , aliguori@amazon.com Cc: Paolo Bonzini Ping again for 1.7. This fixes a regression introduced in 1.6.0, reported by some people on=20 mailing list ([1] Herv=C3=A9 [1] http://lists.gnu.org/archive/html/qemu-devel/2013-11/msg02055.html Herv=C3=A9 Poussineau a =C3=A9crit : > Ping for 1.7 > > Paolo Bonzini a =C3=A9crit : >> Il 04/11/2013 23:26, Herv=C3=A9 Poussineau ha scritto: >>> MIPS Jazz chipset doesn't seem to raise data bus exceptions on=20 >>> invalid accesses. >>> However, there is no easy way to prevent them. Creating a big memory=20 >>> region >>> for the whole address space doesn't prevent memory core to directly=20 >>> call >>> unassigned_mem_read/write which in turn call cpu->do_unassigned_acces= s, >>> which (for MIPS CPU) raise an data bus exception. >> >> Creating a big MMIO region would work, but it wouldn't let you trap >> execution accesses. >> >>> This fixes a MIPS Jazz regression introduced in=20 >>> c658b94f6e8c206c59d02aa6fbac285b86b53d2c. >>> >>> Signed-off-by: Herv=C3=A9 Poussineau >>> --- >>> This fixes a known regression in QEMU 1.6. Let it be fixed as soon=20 >>> as possible. >>> >>> hw/mips/mips_jazz.c | 24 ++++++++++++++++++++++++ >>> 1 file changed, 24 insertions(+) >>> >>> diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c >>> index 49bdd02..5f6dd9f 100644 >>> --- a/hw/mips/mips_jazz.c >>> +++ b/hw/mips/mips_jazz.c >>> @@ -108,6 +108,18 @@ static void cpu_request_exit(void *opaque, int=20 >>> irq, int level) >>> } >>> } >>> =20 >>> +static CPUUnassignedAccess real_do_unassigned_access; >>> +static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr add= r, >>> + bool is_write, bool=20 >>> is_exec, >>> + int opaque, unsigned size= ) >>> +{ >>> + if (!is_exec) { >>> + /* ignore invalid access (ie do not raise exception) */ >>> + return; >>> + } >>> + (*real_do_unassigned_access)(cpu, addr, is_write, is_exec,=20 >>> opaque, size); >>> +} >>> + >>> static void mips_jazz_init(MemoryRegion *address_space, >>> MemoryRegion *address_space_io, >>> ram_addr_t ram_size, >>> @@ -117,6 +129,7 @@ static void mips_jazz_init(MemoryRegion=20 >>> *address_space, >>> char *filename; >>> int bios_size, n; >>> MIPSCPU *cpu; >>> + CPUClass *cc; >>> CPUMIPSState *env; >>> qemu_irq *rc4030, *i8259; >>> rc4030_dma *dmas; >>> @@ -154,6 +167,17 @@ static void mips_jazz_init(MemoryRegion=20 >>> *address_space, >>> env =3D &cpu->env; >>> qemu_register_reset(main_cpu_reset, cpu); >>> =20 >>> + /* Chipset returns 0 in invalid reads and do not raise data=20 >>> exceptions. >>> + * However, we can't simply add a global memory region to catch >>> + * everything, as memory core directly call=20 >>> unassigned_mem_read/write >>> + * on some invalid accesses, which call do_unassigned_access on=20 >>> the >>> + * CPU, which raise an exception. >>> + * Handle that case by hijacking the do_unassigned_access=20 >>> method on >>> + * the CPU, and do not raise exceptions for data access. */ >>> + cc =3D CPU_GET_CLASS(cpu); >>> + real_do_unassigned_access =3D cc->do_unassigned_access; >>> + cc->do_unassigned_access =3D mips_jazz_do_unassigned_access; >>> + >>> /* allocate RAM */ >>> memory_region_init_ram(ram, NULL, "mips_jazz.ram", ram_size); >>> vmstate_register_ram_global(ram); >>> >> >> Reviewed-by: Paolo Bonzini >> >> Please remember to add 1.7 in the subject at this time. >> >> Paolo >> > >