From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40122) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VksOd-0003xM-2b for qemu-devel@nongnu.org; Mon, 25 Nov 2013 04:24:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VksOX-0004Cr-02 for qemu-devel@nongnu.org; Mon, 25 Nov 2013 04:23:58 -0500 Received: from mx1.redhat.com ([209.132.183.28]:46257) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VksOW-0004Cl-O9 for qemu-devel@nongnu.org; Mon, 25 Nov 2013 04:23:52 -0500 Received: from int-mx12.intmail.prod.int.phx2.redhat.com (int-mx12.intmail.prod.int.phx2.redhat.com [10.5.11.25]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id rAP9Npxj009513 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Mon, 25 Nov 2013 04:23:51 -0500 Message-ID: <52931714.6040402@redhat.com> Date: Mon, 25 Nov 2013 17:23:32 +0800 From: Jason Wang MIME-Version: 1.0 References: <1385064260-20962-1-git-send-email-vyasevic@redhat.com> <1385064260-20962-2-git-send-email-vyasevic@redhat.com> <528F2836.8010800@redhat.com> <528F6C46.8070405@redhat.com> In-Reply-To: <528F6C46.8070405@redhat.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC PATCH 1/2] e1000: Use Address_Available bit as HW latch List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: vyasevic@redhat.com, qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, akong@redhat.com, stefanha@redhat.com, mst@redhat.com On 11/22/2013 10:37 PM, Vlad Yasevich wrote: > On 11/22/2013 04:47 AM, Jason Wang wrote: >> > On 11/22/2013 04:04 AM, Vlad Yasevich wrote: >>> >> e1000 provides a E1000_RAH_AV bit on every complete write >>> >> to the Receive Address Register. We can use this bit >>> >> 2 ways: >>> >> 1) To trigger HMP notifications. When the bit is set the >>> >> mac address is fully set and we can update the HMP. >>> >> >>> >> 2) We can turn off he bit on the write to low order bits of >>> >> the Receive Address Register, so that we would not try >>> >> to match received traffic to this address when it is >>> >> not completely set. >>> >> >>> >> Signed-off-by: Vlad Yasevich >>> >> --- >>> >> hw/net/e1000.c | 11 ++++++++++- >>> >> 1 file changed, 10 insertions(+), 1 deletion(-) >>> >> >>> >> diff --git a/hw/net/e1000.c b/hw/net/e1000.c >>> >> index ae63591..82978ea 100644 >>> >> --- a/hw/net/e1000.c >>> >> +++ b/hw/net/e1000.c >>> >> @@ -1106,10 +1106,19 @@ mac_writereg(E1000State *s, int index, uint32_t val) >>> >> >>> >> s->mac_reg[index] = val; >>> >> >>> >> - if (index == RA || index == RA + 1) { >>> >> + switch (index) { >>> >> + case RA: >>> >> + /* Mask off AV bit on the write of the low dword. The write of >>> >> + * the high dword will set the bit. This way a half-written >>> >> + * mac address will not be used to filter on rx. >>> >> + */ >>> >> + s->mac_reg[RA+1] &= ~E1000_RAH_AV; >> > >> > If a stupid driver write high dword first, it won't receive any packets. > I need to ping Intel guys again. I asked them what happens when only > the low register is set, but haven't heard back. > They probably don't have the willing to share the internals of card. I hacked the e1000 driver to check the subtle and undocumented behaviour in the past. Maybe we can do the same.