* [Qemu-devel] [PATCH v6 0/5] add sunxi machine type
@ 2013-11-27 8:23 liguang
2013-11-27 8:23 ` [Qemu-devel] [PATCH v6 1/5] hw/ptimer: add VMSTATE_PTIMER_ARRAY liguang
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: liguang @ 2013-11-27 8:23 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Peter Crosthwaite, liguang
this patch-set implemented a device-reduced
machine type for Allwinner's sunxi series SoC,
like sunxi-4i/5i/7i ...
now, It can support sunxi-4i with a cortex-a8 processor.
and will support more later, like sunxi-7i with cortex-a7,
and will add more devices.
v2: split timer and interrupt controller emulation into
their corresponding files.
v3:
1. change loader_start address
2. add 64-bit counter
3. fixup fail to clear interrup status issue
v4:
1. add VMSD
2. use defines of magic number for readability
3. code cleanup
v5:
1. add VMSTATE_PTIMER_ARRAY
2. code cleanup
v6:
1. fix a fiq lost issue pointed out by Peter Crosthwaite
2. code cleanup
TODO:
1. add BROM support
2. add more devices
3. add sunxi-7i support
test:
can boot-up officially released linux kernel.
reference:
http://linux-sunxi.org/Main_Page
Li Guang (5)
hw/ptimer: add VMSTATE_PTIMER_ARRAY
hw/timer: add sunxi timer device
hw/intc: add sunxi interrupt controller device
hw/arm: add sunxi machine type
MAINTAINERS: add myself to maintain sunxi machine
MAINTAINERS | 9 +++++++++
default-configs/arm-softmmu.mak | 3 +
hw/arm/Makefile.objs | 1 +
hw/arm/sunxi-soc.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++++++
hw/intc/Makefile.objs | 1 +
hw/intc/sunxi-pic.c | 244 +++++++++++++++++++++++++++++++++++++++
hw/timer/Makefile.objs | 1 +
hw/timer/sunxi-pit.c | 276 +++++++++++++++++++++++++++++++++++++++
include/hw/intc/sunxi-pic.h | 20 +++
include/hw/ptimer.h | 3 +++
include/hw/timer/sunxi-pit.h | 37 +++++
11 files changed, 693 insertions(+), 0 deletions(-)
create mode 100644 hw/timer/sunxi-pit.c
create mode 100644 include/hw/timer/sunxi-pit.h
create mode 100644 hw/intc/sunxi-pic.c
create mode 100644 include/hw/intc/sunxi-pic.h
create mode 100644 hw/arm/sunxi-soc.c
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH v6 1/5] hw/ptimer: add VMSTATE_PTIMER_ARRAY
2013-11-27 8:23 [Qemu-devel] [PATCH v6 0/5] add sunxi machine type liguang
@ 2013-11-27 8:23 ` liguang
2013-11-29 11:01 ` Peter Maydell
2013-11-27 8:23 ` [Qemu-devel] [PATCH v6 2/5] hw/timer: add sunxi timer device liguang
` (4 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: liguang @ 2013-11-27 8:23 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Peter Crosthwaite, liguang
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
---
include/hw/ptimer.h | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h
index 28fcaf1..a9b8f1d 100644
--- a/include/hw/ptimer.h
+++ b/include/hw/ptimer.h
@@ -27,6 +27,9 @@ void ptimer_stop(ptimer_state *s);
extern const VMStateDescription vmstate_ptimer;
+#define VMSTATE_PTIMER_ARRAY(_f, _s, _n) \
+ VMSTATE_STRUCT_ARRAY(_f, _s, _n, 0, vmstate_ptimer, ptimer_state*)
+
#define VMSTATE_PTIMER(_field, _state) { \
.name = (stringify(_field)), \
.version_id = (1), \
--
1.7.2.5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH v6 2/5] hw/timer: add sunxi timer device
2013-11-27 8:23 [Qemu-devel] [PATCH v6 0/5] add sunxi machine type liguang
2013-11-27 8:23 ` [Qemu-devel] [PATCH v6 1/5] hw/ptimer: add VMSTATE_PTIMER_ARRAY liguang
@ 2013-11-27 8:23 ` liguang
2013-11-27 8:23 ` [Qemu-devel] [PATCH v6 3/5] hw/intc: add sunxi interrupt controller device liguang
` (3 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: liguang @ 2013-11-27 8:23 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Peter Crosthwaite, liguang
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
---
default-configs/arm-softmmu.mak | 2 +
hw/timer/Makefile.objs | 1 +
hw/timer/sunxi-pit.c | 252 +++++++++++++++++++++++++++++++++++++++
include/hw/timer/sunxi-pit.h | 56 +++++++++
4 files changed, 311 insertions(+), 0 deletions(-)
create mode 100644 hw/timer/sunxi-pit.c
create mode 100644 include/hw/timer/sunxi-pit.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index a555eef..7bf5ad0 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -81,3 +81,5 @@ CONFIG_VERSATILE_I2C=y
CONFIG_SDHCI=y
CONFIG_INTEGRATOR_DEBUG=y
+
+CONFIG_SUNXI_PIT=y
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index eca5905..f7888e9 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -27,3 +27,4 @@ obj-$(CONFIG_SH4) += sh_timer.o
obj-$(CONFIG_TUSB6010) += tusb6010.o
obj-$(CONFIG_MC146818RTC) += mc146818rtc.o
+obj-$(CONFIG_SUNXI_PIT) += sunxi-pit.o
diff --git a/hw/timer/sunxi-pit.c b/hw/timer/sunxi-pit.c
new file mode 100644
index 0000000..2847ab7
--- /dev/null
+++ b/hw/timer/sunxi-pit.c
@@ -0,0 +1,252 @@
+/*
+ * Allwinner sunxi timer device emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang <lig.fnst@cn.fujitsu.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/ptimer.h"
+#include "sysemu/sysemu.h"
+#include "hw/timer/sunxi-pit.h"
+
+
+static uint64_t sunxi_pit_read(void *opaque, hwaddr offset, unsigned size)
+{
+ SunxiPITState *s = SUNXI_PIT(opaque);
+ uint8_t index;
+
+ switch (offset) {
+ case SUNXI_TIMER_IRQ_EN:
+ return s->irq_enable;
+ case SUNXI_TIMER_IRQ_ST:
+ return s->irq_status;
+ case SUNXI_TIMER_BASE ... SUNXI_TIMER_BASE * 6 + SUNXI_TIMER_COUNT:
+ index = offset & 0xf0;
+ index >>= 4;
+ index -= 1;
+ switch (offset & 0x0f) {
+ case SUNXI_TIMER_CONTROL:
+ return s->control[index];
+ case SUNXI_TIMER_INTERVAL:
+ return s->interval[index];
+ case SUNXI_TIMER_COUNT:
+ s->count[index] = ptimer_get_count(s->timer[index]);
+ return s->count[index];
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%x\n", __func__, (int)offset);
+ break;
+ }
+ case SUNXI_WDOG_CONTROL:
+ break;
+ case SUNXI_WDOG_MODE:
+ break;
+ case SUNXI_COUNT_LO:
+ return s->count_lo;
+ break;
+ case SUNXI_COUNT_HI:
+ return s->count_hi;
+ break;
+ case SUNXI_COUNT_CTL:
+ return s->count_ctl;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%x\n", __func__, (int)offset);
+ break;
+ }
+
+ return 0;
+}
+
+static void sunxi_pit_write(void *opaque, hwaddr offset, uint64_t value,
+ unsigned size)
+{
+ SunxiPITState *s = SUNXI_PIT(opaque);
+ uint8_t index;
+
+ switch (offset) {
+ case SUNXI_TIMER_IRQ_EN:
+ s->irq_enable = value;
+ break;
+ case SUNXI_TIMER_IRQ_ST:
+ s->irq_status &= ~value;
+ break;
+ case SUNXI_TIMER_BASE ... SUNXI_TIMER_BASE * 6 + SUNXI_TIMER_COUNT:
+ index = offset & 0xf0;
+ index >>= 4;
+ index -= 1;
+ switch (offset & 0x0f) {
+ case SUNXI_TIMER_CONTROL:
+ s->control[index] = value;
+ if (s->control[index] & SUNXI_TIMER_RELOAD) {
+ ptimer_set_count(s->timer[index], s->interval[index]);
+ }
+ if (s->control[index] & SUNXI_TIMER_EN) {
+ ptimer_run(s->timer[index], 1);
+ } else {
+ ptimer_stop(s->timer[index]);
+ }
+ break;
+ case SUNXI_TIMER_INTERVAL:
+ s->interval[index] = value;
+ ptimer_set_count(s->timer[index], s->interval[index]);
+ break;
+ case SUNXI_TIMER_COUNT:
+ s->count[index] = value;
+ default:
+ break;
+ }
+ break;
+ case SUNXI_WDOG_CONTROL:
+ s->watch_dog_control = value;
+ break;
+ case SUNXI_WDOG_MODE:
+ s->watch_dog_mode = value;
+ break;
+ case SUNXI_COUNT_LO:
+ s->count_lo = value;
+ break;
+ case SUNXI_COUNT_HI:
+ s->count_hi = value;
+ break;
+ case SUNXI_COUNT_CTL:
+ s->count_ctl = value;
+ if (s->count_ctl & SUNXI_COUNT_RL_EN) {
+ s->count_lo = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ s->count_hi = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >> 32;
+ s->count_ctl &= ~SUNXI_COUNT_RL_EN;
+ }
+ if (s->count_ctl & SUNXI_COUNT_CLR_EN) {
+ s->count_lo =0;
+ s->count_hi =0;
+ s->count_ctl &= ~SUNXI_COUNT_CLR_EN;
+ }
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%x\n", __func__, (int)offset);
+ break;
+ }
+}
+
+static const MemoryRegionOps sunxi_pit_ops = {
+ .read = sunxi_pit_read,
+ .write = sunxi_pit_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription vmstate_sunxi_pit = {
+ .name = "sunxi.pit",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(irq_enable, SunxiPITState),
+ VMSTATE_UINT32(irq_status, SunxiPITState),
+ VMSTATE_UINT32_ARRAY(control, SunxiPITState, SUNXI_TIMER_NR),
+ VMSTATE_UINT32_ARRAY(interval, SunxiPITState, SUNXI_TIMER_NR),
+ VMSTATE_UINT32_ARRAY(count, SunxiPITState, SUNXI_TIMER_NR),
+ VMSTATE_UINT32(watch_dog_mode, SunxiPITState),
+ VMSTATE_UINT32(watch_dog_control, SunxiPITState),
+ VMSTATE_UINT32(count_lo, SunxiPITState),
+ VMSTATE_UINT32(count_hi, SunxiPITState),
+ VMSTATE_UINT32(count_ctl, SunxiPITState),
+ VMSTATE_PTIMER_ARRAY(timer, SunxiPITState, SUNXI_TIMER_NR),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void sunxi_pit_reset(DeviceState *dev)
+{
+ SunxiPITState *s = SUNXI_PIT(dev);
+ uint8_t i;
+
+ s->irq_enable = 0;
+ s->irq_status = 0;
+ for (i = 0; i < 6; i++) {
+ s->control[i] = SUNXI_DEFAULT_CLOCK;
+ s->interval[i] = 0;
+ s->count[i] = 0;
+ ptimer_stop(s->timer[i]);
+ }
+ s->watch_dog_mode = 0;
+ s->watch_dog_control = 0;
+ s->count_lo = 0;
+ s->count_hi = 0;
+ s->count_ctl = 0;
+}
+
+static void sunxi_pit_timer_cb(void *opaque)
+{
+ SunxiPITState *s = SUNXI_PIT(opaque);
+ uint8_t i;
+
+ for (i = 0; i < SUNXI_TIMER_NR; i++) {
+ if (s->control[i] & SUNXI_TIMER_EN &&
+ ptimer_get_count(s->timer[i]) == 0) {
+ s->irq_status |= 1 << i;
+ if (!(s->control[i] & SUNXI_TIMER_MODE)) {
+ ptimer_set_count(s->timer[i], s->interval[i]);
+ ptimer_run(s->timer[i], 1);
+ }
+ qemu_irq_raise(s->irq[i]);
+ }
+ qemu_irq_lower(s->irq[i]);
+ }
+}
+
+static void sunxi_pit_realize(DeviceState *dev, Error **errp)
+{
+ SunxiPITState *s = SUNXI_PIT(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ QEMUBH *bh[SUNXI_TIMER_NR];
+ uint8_t i;
+
+ for (i = 0; i < SUNXI_TIMER_NR; i++) {
+ sysbus_init_irq(sbd, &s->irq[i]);
+ }
+ memory_region_init_io(&s->iomem, OBJECT(s), &sunxi_pit_ops, s,
+ TYPE_SUNXI_PIT, 0x400);
+ sysbus_init_mmio(sbd, &s->iomem);
+
+ for (i = 0; i < SUNXI_TIMER_NR; i++) {
+ bh[i] = qemu_bh_new(sunxi_pit_timer_cb, s);
+ s->timer[i] = ptimer_init(bh[i]);
+ ptimer_set_freq(s->timer[i], 240000);
+ }
+}
+
+static void sunxi_pit_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = sunxi_pit_realize;
+ dc->reset = sunxi_pit_reset;
+ dc->desc = "sunxi timer";
+ dc->vmsd = &vmstate_sunxi_pit;
+}
+
+static const TypeInfo sunxi_pit_info = {
+ .name = TYPE_SUNXI_PIT,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(SunxiPITState),
+ .class_init = sunxi_pit_class_init,
+};
+
+static void sunxi_register_types(void)
+{
+ type_register_static(&sunxi_pit_info);
+}
+
+type_init(sunxi_register_types);
diff --git a/include/hw/timer/sunxi-pit.h b/include/hw/timer/sunxi-pit.h
new file mode 100644
index 0000000..7c84946
--- /dev/null
+++ b/include/hw/timer/sunxi-pit.h
@@ -0,0 +1,56 @@
+#ifndef SUNXI_PIT_H
+#define SUNXI_PIT_H
+
+
+#define TYPE_SUNXI_PIT "sunxi-timer"
+#define SUNXI_PIT(obj) OBJECT_CHECK(SunxiPITState, (obj), TYPE_SUNXI_PIT)
+
+#define SUNXI_TIMER_NR 6
+#define SUNXI_TIMER_IRQ 0x1
+#define SUNXI_WDOG_IRQ 0x100
+
+#define SUNXI_TIMER_IRQ_EN 0
+#define SUNXI_TIMER_IRQ_ST 0x4
+
+#define SUNXI_TIMER_CONTROL 0x0
+#define SUNXI_TIMER_EN 0x1
+#define SUNXI_TIMER_RELOAD 0x2
+#define SUNXI_TIMER_MODE 0x80
+
+#define SUNXI_TIMER_INTERVAL 0x4
+#define SUNXI_TIMER_COUNT 0x8
+#define SUNXI_WDOG_CONTROL 0x90
+#define SUNXI_WDOG_MODE 0x94
+
+#define SUNXI_COUNT_CTL 0xa0
+#define SUNXI_COUNT_RL_EN 0x2
+#define SUNXI_COUNT_CLR_EN 0x1
+#define SUNXI_COUNT_LO 0xa4
+#define SUNXI_COUNT_HI 0xa8
+
+#define SUNXI_TIMER_BASE 0x10
+
+#define SUNXI_DEFAULT_CLOCK 0x4
+
+typedef struct SunxiPITState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+ qemu_irq irq[SUNXI_TIMER_NR];
+ ptimer_state *timer[SUNXI_TIMER_NR];
+ MemoryRegion iomem;
+
+ uint32_t irq_enable;
+ uint32_t irq_status;
+ uint32_t control[SUNXI_TIMER_NR];
+ uint32_t interval[SUNXI_TIMER_NR];
+ uint32_t count[SUNXI_TIMER_NR];
+ uint32_t watch_dog_mode;
+ uint32_t watch_dog_control;
+ uint32_t count_lo;
+ uint32_t count_hi;
+ uint32_t count_ctl;
+} SunxiPITState;
+
+#endif
+
--
1.7.2.5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH v6 3/5] hw/intc: add sunxi interrupt controller device
2013-11-27 8:23 [Qemu-devel] [PATCH v6 0/5] add sunxi machine type liguang
2013-11-27 8:23 ` [Qemu-devel] [PATCH v6 1/5] hw/ptimer: add VMSTATE_PTIMER_ARRAY liguang
2013-11-27 8:23 ` [Qemu-devel] [PATCH v6 2/5] hw/timer: add sunxi timer device liguang
@ 2013-11-27 8:23 ` liguang
2013-11-27 8:23 ` [Qemu-devel] [PATCH v6 4/5] hw/arm: add sunxi machine type liguang
` (2 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: liguang @ 2013-11-27 8:23 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Peter Crosthwaite, liguang
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
---
default-configs/arm-softmmu.mak | 1 +
hw/intc/Makefile.objs | 1 +
hw/intc/sunxi-pic.c | 218 +++++++++++++++++++++++++++++++++++++++
include/hw/intc/sunxi-pic.h | 40 +++++++
4 files changed, 260 insertions(+), 0 deletions(-)
create mode 100644 hw/intc/sunxi-pic.c
create mode 100644 include/hw/intc/sunxi-pic.h
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 7bf5ad0..bbe00e4 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -83,3 +83,4 @@ CONFIG_SDHCI=y
CONFIG_INTEGRATOR_DEBUG=y
CONFIG_SUNXI_PIT=y
+CONFIG_SUNXI_PIC=y
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 47ac442..dad8c43 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -12,6 +12,7 @@ common-obj-$(CONFIG_IOAPIC) += ioapic_common.o
common-obj-$(CONFIG_ARM_GIC) += arm_gic_common.o
common-obj-$(CONFIG_ARM_GIC) += arm_gic.o
common-obj-$(CONFIG_OPENPIC) += openpic.o
+common-obj-$(CONFIG_SUNXI_PIC) += sunxi-pic.o
obj-$(CONFIG_APIC) += apic.o apic_common.o
obj-$(CONFIG_ARM_GIC_KVM) += arm_gic_kvm.o
diff --git a/hw/intc/sunxi-pic.c b/hw/intc/sunxi-pic.c
new file mode 100644
index 0000000..9e64895
--- /dev/null
+++ b/hw/intc/sunxi-pic.c
@@ -0,0 +1,218 @@
+/*
+ * Allwinner sunxi interrupt controller device emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang <lig.fnst@cn.fujitsu.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/devices.h"
+#include "sysemu/sysemu.h"
+#include "hw/intc/sunxi-pic.h"
+
+
+static void sunxi_pic_update(SunxiPICState *s)
+{
+ uint8_t i, j;
+ bool irq = false, fiq = false;
+
+ for (i = 0, j = 0; i < SUNXI_PIC_REG_NUM; i++) {
+ if (s->irq_pending[i] == 0 && s->fiq_pending[i] == 0) {
+ continue;
+ }
+ for (j = 0; j < 32; j++) {
+ if (test_bit(j, (void *)&s->mask[i])) {
+ continue;
+ }
+ if (test_bit(j, (void *)&s->irq_pending[i])) {
+ irq = true;
+ }
+ if (test_bit(j, (void *)&s->fiq_pending[i]) &&
+ test_bit(j, (void *)&s->select[i])) {
+ fiq = true;
+ }
+ if (irq && fiq) {
+ goto out;
+ }
+ }
+ }
+
+out:
+ qemu_set_irq(s->parent_irq, irq);
+ qemu_set_irq(s->parent_fiq, fiq);
+}
+
+static void sunxi_pic_set_irq(void *opaque, int irq, int level)
+{
+ SunxiPICState *s = opaque;
+
+ if (level) {
+ set_bit(irq%32, (void *)&s->irq_pending[irq/32]);
+ }
+ sunxi_pic_update(s);
+}
+
+static uint64_t sunxi_pic_read(void *opaque, hwaddr offset, unsigned size)
+{
+ SunxiPICState *s = opaque;
+ uint8_t index = (offset & 0xc)/4;
+
+ switch (offset) {
+ case SUNXI_PIC_VECTOR:
+ return s->vector;
+ case SUNXI_PIC_BASE_ADDR:
+ return s->base_addr;
+ case SUNXI_PIC_PROTECT:
+ return s->protect;
+ case SUNXI_PIC_NMI:
+ return s->nmi;
+ case SUNXI_PIC_IRQ_PENDING ... SUNXI_PIC_IRQ_PENDING + 8:
+ return s->irq_pending[index];
+ case SUNXI_PIC_FIQ_PENDING ... SUNXI_PIC_FIQ_PENDING + 8:
+ return s->fiq_pending[index];
+ case SUNXI_PIC_SELECT ... SUNXI_PIC_SELECT + 8:
+ return s->select[index];
+ case SUNXI_PIC_ENABLE ... SUNXI_PIC_ENABLE + 8:
+ return s->enable[index];
+ case SUNXI_PIC_MASK ... SUNXI_PIC_MASK + 8:
+ return s->mask[index];
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%x\n", __func__, (int)offset);
+ break;
+ }
+
+ return 0;
+}
+
+static void sunxi_pic_write(void *opaque, hwaddr offset, uint64_t value,
+ unsigned size)
+{
+ SunxiPICState *s = opaque;
+ uint8_t index = (offset & 0xc)/4;
+
+ switch (offset) {
+ case SUNXI_PIC_VECTOR:
+ s->vector = value & ~0x3;
+ break;
+ case SUNXI_PIC_BASE_ADDR:
+ s->base_addr = value & ~0x3;
+ case SUNXI_PIC_PROTECT:
+ s->protect = value;
+ break;
+ case SUNXI_PIC_NMI:
+ s->nmi = value;
+ break;
+ case SUNXI_PIC_IRQ_PENDING ... SUNXI_PIC_IRQ_PENDING + 8:
+ s->irq_pending[index] &= ~value;
+ break;
+ case SUNXI_PIC_FIQ_PENDING ... SUNXI_PIC_FIQ_PENDING + 8:
+ s->fiq_pending[index] &= ~value;
+ break;
+ case SUNXI_PIC_SELECT ... SUNXI_PIC_SELECT + 8:
+ s->select[index] = value;
+ break;
+ case SUNXI_PIC_ENABLE ... SUNXI_PIC_ENABLE + 8:
+ s->enable[index] = value;
+ break;
+ case SUNXI_PIC_MASK ... SUNXI_PIC_MASK + 8:
+ s->mask[index] = value;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%x\n", __func__, (int)offset);
+ break;
+ }
+
+ sunxi_pic_update(s);
+}
+
+static const MemoryRegionOps sunxi_pic_ops = {
+ .read = sunxi_pic_read,
+ .write = sunxi_pic_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription vmstate_sunxi_pic = {
+ .name = "sunxi.pic",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(vector, SunxiPICState),
+ VMSTATE_UINT32(base_addr, SunxiPICState),
+ VMSTATE_UINT32(protect, SunxiPICState),
+ VMSTATE_UINT32(nmi, SunxiPICState),
+ VMSTATE_UINT32_ARRAY(irq_pending, SunxiPICState, SUNXI_PIC_REG_NUM),
+ VMSTATE_UINT32_ARRAY(fiq_pending, SunxiPICState, SUNXI_PIC_REG_NUM),
+ VMSTATE_UINT32_ARRAY(enable, SunxiPICState, SUNXI_PIC_REG_NUM),
+ VMSTATE_UINT32_ARRAY(select, SunxiPICState, SUNXI_PIC_REG_NUM),
+ VMSTATE_UINT32_ARRAY(mask, SunxiPICState, SUNXI_PIC_REG_NUM),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void sunxi_pic_realize(DeviceState *ds, Error **errp)
+{
+ SunxiPICState *s = SUNXI_PIC(ds);
+ SysBusDevice *dev = SYS_BUS_DEVICE(ds);
+
+ qdev_init_gpio_in(DEVICE(dev), sunxi_pic_set_irq, SUNXI_PIC_INT_NR);
+ sysbus_init_irq(dev, &s->parent_irq);
+ sysbus_init_irq(dev, &s->parent_fiq);
+ memory_region_init_io(&s->iomem, OBJECT(s), &sunxi_pic_ops, s,
+ "sunxi-pic", 0x400);
+ sysbus_init_mmio(dev, &s->iomem);
+}
+
+static void sunxi_pic_reset(DeviceState *d)
+{
+ SunxiPICState *s = SUNXI_PIC(d);
+ uint8_t i;
+
+ s->base_addr = 0;
+ s->protect = 0;
+ s->nmi = 0;
+ s->vector = 0;
+ for (i = 0; i < SUNXI_PIC_REG_NUM; i++) {
+ s->irq_pending[i] = 0;
+ s->fiq_pending[i] = 0;
+ s->select[i] = 0;
+ s->enable[i] = 0;
+ s->mask[i] = 0;
+ }
+}
+
+static void sunxi_pic_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = sunxi_pic_realize;
+ dc->reset = sunxi_pic_reset;
+ dc->desc = "sunxi pic";
+ dc->vmsd = &vmstate_sunxi_pic;
+ }
+
+static const TypeInfo sunxi_pic_info = {
+ .name = TYPE_SUNXI_PIC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(SunxiPICState),
+ .class_init = sunxi_pic_class_init,
+};
+
+static void sunxi_register_types(void)
+{
+ type_register_static(&sunxi_pic_info);
+}
+
+type_init(sunxi_register_types);
diff --git a/include/hw/intc/sunxi-pic.h b/include/hw/intc/sunxi-pic.h
new file mode 100644
index 0000000..6c32382
--- /dev/null
+++ b/include/hw/intc/sunxi-pic.h
@@ -0,0 +1,40 @@
+#ifndef SUNXI_PIC_H
+#define SUNXI_PIC_H
+
+#define TYPE_SUNXI_PIC "sunxi-pic"
+#define SUNXI_PIC(obj) OBJECT_CHECK(SunxiPICState, (obj), TYPE_SUNXI_PIC)
+
+#define SUNXI_PIC_VECTOR 0
+#define SUNXI_PIC_BASE_ADDR 4
+#define SUNXI_PIC_PROTECT 8
+#define SUNXI_PIC_NMI 0xc
+#define SUNXI_PIC_IRQ_PENDING 0x10
+#define SUNXI_PIC_FIQ_PENDING 0x20
+#define SUNXI_PIC_SELECT 0x30
+#define SUNXI_PIC_ENABLE 0x40
+#define SUNXI_PIC_MASK 0x50
+
+#define SUNXI_PIC_INT_NR 95
+#define SUNXI_PIC_REG_NUM DIV_ROUND_UP(SUNXI_PIC_INT_NR, 32)
+
+typedef struct SunxiPICState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+ MemoryRegion iomem;
+ qemu_irq parent_fiq;
+ qemu_irq parent_irq;
+
+ uint32_t vector;
+ uint32_t base_addr;
+ uint32_t protect;
+ uint32_t nmi;
+ uint32_t irq_pending[SUNXI_PIC_REG_NUM];
+ uint32_t fiq_pending[SUNXI_PIC_REG_NUM];
+ uint32_t select[SUNXI_PIC_REG_NUM];
+ uint32_t enable[SUNXI_PIC_REG_NUM];
+ uint32_t mask[SUNXI_PIC_REG_NUM];
+ /*priority setting here*/
+} SunxiPICState;
+
+#endif
--
1.7.2.5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH v6 4/5] hw/arm: add sunxi machine type
2013-11-27 8:23 [Qemu-devel] [PATCH v6 0/5] add sunxi machine type liguang
` (2 preceding siblings ...)
2013-11-27 8:23 ` [Qemu-devel] [PATCH v6 3/5] hw/intc: add sunxi interrupt controller device liguang
@ 2013-11-27 8:23 ` liguang
2013-11-27 8:23 ` [Qemu-devel] [PATCH v6 5/5] MAINTAINERS: add myself to maintain sunxi machine liguang
2013-11-27 8:28 ` [Qemu-devel] [PATCH v6 0/5] add sunxi machine type Peter Crosthwaite
5 siblings, 0 replies; 11+ messages in thread
From: liguang @ 2013-11-27 8:23 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Peter Crosthwaite, liguang
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
---
hw/arm/Makefile.objs | 1 +
hw/arm/sunxi-soc.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 99 insertions(+), 0 deletions(-)
create mode 100644 hw/arm/sunxi-soc.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 3671b42..f9f3071 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -5,3 +5,4 @@ obj-y += tosa.o versatilepb.o vexpress.o xilinx_zynq.o z2.o
obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
obj-y += omap1.o omap2.o strongarm.o
+obj-y += sunxi-soc.o
diff --git a/hw/arm/sunxi-soc.c b/hw/arm/sunxi-soc.c
new file mode 100644
index 0000000..3c9f204
--- /dev/null
+++ b/hw/arm/sunxi-soc.c
@@ -0,0 +1,98 @@
+/*
+ * Allwinner sunxi series SoC emulation
+ *
+ * Copyright (C) 2013 Li Guang
+ * Written by Li Guang <lig.fnst@cn.fujitsu.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/devices.h"
+#include "hw/boards.h"
+#include "hw/arm/arm.h"
+#include "hw/ptimer.h"
+#include "hw/char/serial.h"
+#include "hw/timer/sunxi-pit.h"
+#include "hw/intc/sunxi-pic.h"
+
+#include "sysemu/sysemu.h"
+#include "exec/address-spaces.h"
+
+
+#define SUNXI_PIC_REG_BASE 0x01c20400
+#define SUNXI_PIT_REG_BASE 0x01c20c00
+#define SUNXI_UART0_REG_BASE 0x01c28000
+
+static struct arm_boot_info sunxi_binfo = {
+ .loader_start = 0x40000000,
+ .board_id = 0x1008,
+};
+
+static void sunxi_init(QEMUMachineInitArgs *args)
+{
+ ram_addr_t ram_size = args->ram_size;
+ const char *cpu_model = args->cpu_model;
+ const char *kernel_filename = args->kernel_filename;
+ const char *kernel_cmdline = args->kernel_cmdline;
+ ARMCPU *cpu;
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
+ MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
+ qemu_irq pic[SUNXI_PIC_INT_NR];
+ DeviceState *dev;
+ uint8_t i;
+
+ /*here we currently support sunxi-4i*/
+ cpu_model = "cortex-a8";
+ cpu = cpu_arm_init(cpu_model);
+ if (!cpu) {
+ fprintf(stderr, "Unable to find CPU definition\n");
+ exit(1);
+ }
+
+ memory_region_init_ram(ram, NULL, "sunxi-soc.ram", ram_size);
+ memory_region_add_subregion(address_space_mem, 0, ram);
+ memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size);
+ memory_region_add_subregion(address_space_mem, 0x40000000, ram_alias);
+
+ dev = sysbus_create_varargs(TYPE_SUNXI_PIC, SUNXI_PIC_REG_BASE,
+ qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ),
+ qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ),
+ NULL);
+ for (i = 0; i < SUNXI_PIC_INT_NR; i++) {
+ pic[i] = qdev_get_gpio_in(dev, i);
+ }
+
+ sysbus_create_varargs(TYPE_SUNXI_PIT, SUNXI_PIT_REG_BASE, pic[22], pic[23],
+ pic[24], pic[25], pic[67], pic[68], NULL);
+
+ serial_mm_init(address_space_mem, SUNXI_UART0_REG_BASE, 2, pic[1], 115200,
+ serial_hds[0], DEVICE_NATIVE_ENDIAN);
+
+ sunxi_binfo.ram_size = ram_size;
+ sunxi_binfo.kernel_filename = kernel_filename;
+ sunxi_binfo.kernel_cmdline = kernel_cmdline;
+ arm_load_kernel(cpu, &sunxi_binfo);
+}
+
+static QEMUMachine sunxi_machine = {
+ .name = "sunxi",
+ .desc = "Allwinner's SoC (sunxi series)",
+ .init = sunxi_init,
+};
+
+static void sunxi_machine_init(void)
+{
+ qemu_register_machine(&sunxi_machine);
+}
+
+machine_init(sunxi_machine_init);
--
1.7.2.5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH v6 5/5] MAINTAINERS: add myself to maintain sunxi machine
2013-11-27 8:23 [Qemu-devel] [PATCH v6 0/5] add sunxi machine type liguang
` (3 preceding siblings ...)
2013-11-27 8:23 ` [Qemu-devel] [PATCH v6 4/5] hw/arm: add sunxi machine type liguang
@ 2013-11-27 8:23 ` liguang
2013-11-27 8:28 ` [Qemu-devel] [PATCH v6 0/5] add sunxi machine type Peter Crosthwaite
5 siblings, 0 replies; 11+ messages in thread
From: liguang @ 2013-11-27 8:23 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, Peter Crosthwaite, liguang
Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
---
MAINTAINERS | 9 +++++++++
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 77edacf..232e1a1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -284,6 +284,15 @@ M: Peter Maydell <peter.maydell@linaro.org>
S: Maintained
F: hw/*/stellaris*
+Sunxi
+M: Li Guang <lig.fnst@cn.fujitsu.com>
+S: Maintained
+F: hw/arm/sunxi-soc.c
+F: hw/intc/sunxi-pic.c
+F: hw/timer/sunxi-pit.c
+F: include/hw/intc/sunxi-pic.h
+F: include/hw/timer/sunxi-pit.h
+
Versatile PB
M: Peter Maydell <peter.maydell@linaro.org>
S: Maintained
--
1.7.2.5
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v6 0/5] add sunxi machine type
2013-11-27 8:23 [Qemu-devel] [PATCH v6 0/5] add sunxi machine type liguang
` (4 preceding siblings ...)
2013-11-27 8:23 ` [Qemu-devel] [PATCH v6 5/5] MAINTAINERS: add myself to maintain sunxi machine liguang
@ 2013-11-27 8:28 ` Peter Crosthwaite
2013-11-27 8:35 ` Li Guang
5 siblings, 1 reply; 11+ messages in thread
From: Peter Crosthwaite @ 2013-11-27 8:28 UTC (permalink / raw)
To: liguang; +Cc: Peter Maydell, qemu-devel@nongnu.org Developers
Hi Liguang,
On Wed, Nov 27, 2013 at 6:23 PM, liguang <lig.fnst@cn.fujitsu.com> wrote:
> this patch-set implemented a device-reduced
> machine type for Allwinner's sunxi series SoC,
> like sunxi-4i/5i/7i ...
>
> now, It can support sunxi-4i with a cortex-a8 processor.
> and will support more later, like sunxi-7i with cortex-a7,
> and will add more devices.
>
> v2: split timer and interrupt controller emulation into
> their corresponding files.
>
> v3:
> 1. change loader_start address
> 2. add 64-bit counter
> 3. fixup fail to clear interrup status issue
>
> v4:
> 1. add VMSD
> 2. use defines of magic number for readability
> 3. code cleanup
>
> v5:
> 1. add VMSTATE_PTIMER_ARRAY
> 2. code cleanup
>
> v6:
> 1. fix a fiq lost issue pointed out by Peter Crosthwaite
> 2. code cleanup
>
These respins are getting pretty thick and fast. You should give the
other maintainers at least overnight (if not a few days) to weigh in
as well.
Regards,
Peter
> TODO:
> 1. add BROM support
> 2. add more devices
> 3. add sunxi-7i support
>
> test:
> can boot-up officially released linux kernel.
>
> reference:
> http://linux-sunxi.org/Main_Page
>
> Li Guang (5)
> hw/ptimer: add VMSTATE_PTIMER_ARRAY
> hw/timer: add sunxi timer device
> hw/intc: add sunxi interrupt controller device
> hw/arm: add sunxi machine type
> MAINTAINERS: add myself to maintain sunxi machine
>
> MAINTAINERS | 9 +++++++++
> default-configs/arm-softmmu.mak | 3 +
> hw/arm/Makefile.objs | 1 +
> hw/arm/sunxi-soc.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++++++
> hw/intc/Makefile.objs | 1 +
> hw/intc/sunxi-pic.c | 244 +++++++++++++++++++++++++++++++++++++++
> hw/timer/Makefile.objs | 1 +
> hw/timer/sunxi-pit.c | 276 +++++++++++++++++++++++++++++++++++++++
> include/hw/intc/sunxi-pic.h | 20 +++
> include/hw/ptimer.h | 3 +++
> include/hw/timer/sunxi-pit.h | 37 +++++
> 11 files changed, 693 insertions(+), 0 deletions(-)
> create mode 100644 hw/timer/sunxi-pit.c
> create mode 100644 include/hw/timer/sunxi-pit.h
> create mode 100644 hw/intc/sunxi-pic.c
> create mode 100644 include/hw/intc/sunxi-pic.h
> create mode 100644 hw/arm/sunxi-soc.c
>
>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v6 0/5] add sunxi machine type
2013-11-27 8:28 ` [Qemu-devel] [PATCH v6 0/5] add sunxi machine type Peter Crosthwaite
@ 2013-11-27 8:35 ` Li Guang
0 siblings, 0 replies; 11+ messages in thread
From: Li Guang @ 2013-11-27 8:35 UTC (permalink / raw)
To: Peter Crosthwaite; +Cc: Peter Maydell, qemu-devel@nongnu.org Developers
Peter Crosthwaite wrote:
> Hi Liguang,
>
> On Wed, Nov 27, 2013 at 6:23 PM, liguang<lig.fnst@cn.fujitsu.com> wrote:
>
>> this patch-set implemented a device-reduced
>> machine type for Allwinner's sunxi series SoC,
>> like sunxi-4i/5i/7i ...
>>
>> now, It can support sunxi-4i with a cortex-a8 processor.
>> and will support more later, like sunxi-7i with cortex-a7,
>> and will add more devices.
>>
>> v2: split timer and interrupt controller emulation into
>> their corresponding files.
>>
>> v3:
>> 1. change loader_start address
>> 2. add 64-bit counter
>> 3. fixup fail to clear interrup status issue
>>
>> v4:
>> 1. add VMSD
>> 2. use defines of magic number for readability
>> 3. code cleanup
>>
>> v5:
>> 1. add VMSTATE_PTIMER_ARRAY
>> 2. code cleanup
>>
>> v6:
>> 1. fix a fiq lost issue pointed out by Peter Crosthwaite
>> 2. code cleanup
>>
>>
> These respins are getting pretty thick and fast. You should give the
> other maintainers at least overnight (if not a few days) to weigh in
> as well.
>
>
>
OK, thanks!
just a little busy on other jobs, :-)
>
>> TODO:
>> 1. add BROM support
>> 2. add more devices
>> 3. add sunxi-7i support
>>
>> test:
>> can boot-up officially released linux kernel.
>>
>> reference:
>> http://linux-sunxi.org/Main_Page
>>
>> Li Guang (5)
>> hw/ptimer: add VMSTATE_PTIMER_ARRAY
>> hw/timer: add sunxi timer device
>> hw/intc: add sunxi interrupt controller device
>> hw/arm: add sunxi machine type
>> MAINTAINERS: add myself to maintain sunxi machine
>>
>> MAINTAINERS | 9 +++++++++
>> default-configs/arm-softmmu.mak | 3 +
>> hw/arm/Makefile.objs | 1 +
>> hw/arm/sunxi-soc.c | 98 ++++++++++++++++++++++++++++++++++++++++++++++++++
>> hw/intc/Makefile.objs | 1 +
>> hw/intc/sunxi-pic.c | 244 +++++++++++++++++++++++++++++++++++++++
>> hw/timer/Makefile.objs | 1 +
>> hw/timer/sunxi-pit.c | 276 +++++++++++++++++++++++++++++++++++++++
>> include/hw/intc/sunxi-pic.h | 20 +++
>> include/hw/ptimer.h | 3 +++
>> include/hw/timer/sunxi-pit.h | 37 +++++
>> 11 files changed, 693 insertions(+), 0 deletions(-)
>> create mode 100644 hw/timer/sunxi-pit.c
>> create mode 100644 include/hw/timer/sunxi-pit.h
>> create mode 100644 hw/intc/sunxi-pic.c
>> create mode 100644 include/hw/intc/sunxi-pic.h
>> create mode 100644 hw/arm/sunxi-soc.c
>>
>>
>>
>>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v6 1/5] hw/ptimer: add VMSTATE_PTIMER_ARRAY
2013-11-27 8:23 ` [Qemu-devel] [PATCH v6 1/5] hw/ptimer: add VMSTATE_PTIMER_ARRAY liguang
@ 2013-11-29 11:01 ` Peter Maydell
2013-11-29 11:11 ` Peter Maydell
0 siblings, 1 reply; 11+ messages in thread
From: Peter Maydell @ 2013-11-29 11:01 UTC (permalink / raw)
To: liguang; +Cc: Peter Crosthwaite, QEMU Developers
On 27 November 2013 08:23, liguang <lig.fnst@cn.fujitsu.com> wrote:
> Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
> ---
> include/hw/ptimer.h | 3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h
> index 28fcaf1..a9b8f1d 100644
> --- a/include/hw/ptimer.h
> +++ b/include/hw/ptimer.h
> @@ -27,6 +27,9 @@ void ptimer_stop(ptimer_state *s);
>
> extern const VMStateDescription vmstate_ptimer;
>
> +#define VMSTATE_PTIMER_ARRAY(_f, _s, _n) \
> + VMSTATE_STRUCT_ARRAY(_f, _s, _n, 0, vmstate_ptimer, ptimer_state*)
The final parameter here should just be the struct type
("ptimer_state"), not a pointer-to-it.
thanks
-- PMM
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v6 1/5] hw/ptimer: add VMSTATE_PTIMER_ARRAY
2013-11-29 11:01 ` Peter Maydell
@ 2013-11-29 11:11 ` Peter Maydell
2013-12-02 4:28 ` Li Guang
0 siblings, 1 reply; 11+ messages in thread
From: Peter Maydell @ 2013-11-29 11:11 UTC (permalink / raw)
To: liguang; +Cc: Peter Crosthwaite, QEMU Developers
On 29 November 2013 11:01, Peter Maydell <peter.maydell@linaro.org> wrote:
> On 27 November 2013 08:23, liguang <lig.fnst@cn.fujitsu.com> wrote:
>> Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
>> ---
>> include/hw/ptimer.h | 3 +++
>> 1 files changed, 3 insertions(+), 0 deletions(-)
>>
>> diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h
>> index 28fcaf1..a9b8f1d 100644
>> --- a/include/hw/ptimer.h
>> +++ b/include/hw/ptimer.h
>> @@ -27,6 +27,9 @@ void ptimer_stop(ptimer_state *s);
>>
>> extern const VMStateDescription vmstate_ptimer;
>>
>> +#define VMSTATE_PTIMER_ARRAY(_f, _s, _n) \
>> + VMSTATE_STRUCT_ARRAY(_f, _s, _n, 0, vmstate_ptimer, ptimer_state*)
>
> The final parameter here should just be the struct type
> ("ptimer_state"), not a pointer-to-it.
Actually, looking at the patch where you've used this,
you do actually want to deal with an
array-of-pointers-to-ptimers. For that you need
#define VMSTATE_PTIMER_ARRAY(_f, _s, _n) \
VMSTATE_ARRAY_OF_POINTER(_f, _s, _n, 0, vmstate_ptimer, ptimer_state *)
(compare VMSTATE_TIMER_ARRAY in vmstate.h)
thanks
-- PMM
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v6 1/5] hw/ptimer: add VMSTATE_PTIMER_ARRAY
2013-11-29 11:11 ` Peter Maydell
@ 2013-12-02 4:28 ` Li Guang
0 siblings, 0 replies; 11+ messages in thread
From: Li Guang @ 2013-12-02 4:28 UTC (permalink / raw)
To: Peter Maydell; +Cc: Peter Crosthwaite, QEMU Developers
Peter Maydell wrote:
> On 29 November 2013 11:01, Peter Maydell<peter.maydell@linaro.org> wrote:
>
>> On 27 November 2013 08:23, liguang<lig.fnst@cn.fujitsu.com> wrote:
>>
>>> Signed-off-by: liguang<lig.fnst@cn.fujitsu.com>
>>> ---
>>> include/hw/ptimer.h | 3 +++
>>> 1 files changed, 3 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/include/hw/ptimer.h b/include/hw/ptimer.h
>>> index 28fcaf1..a9b8f1d 100644
>>> --- a/include/hw/ptimer.h
>>> +++ b/include/hw/ptimer.h
>>> @@ -27,6 +27,9 @@ void ptimer_stop(ptimer_state *s);
>>>
>>> extern const VMStateDescription vmstate_ptimer;
>>>
>>> +#define VMSTATE_PTIMER_ARRAY(_f, _s, _n) \
>>> + VMSTATE_STRUCT_ARRAY(_f, _s, _n, 0, vmstate_ptimer, ptimer_state*)
>>>
>> The final parameter here should just be the struct type
>> ("ptimer_state"), not a pointer-to-it.
>>
> Actually, looking at the patch where you've used this,
> you do actually want to deal with an
> array-of-pointers-to-ptimers. For that you need
>
> #define VMSTATE_PTIMER_ARRAY(_f, _s, _n) \
> VMSTATE_ARRAY_OF_POINTER(_f, _s, _n, 0, vmstate_ptimer, ptimer_state *)
>
> (compare VMSTATE_TIMER_ARRAY in vmstate.h)
>
>
>
OK, thanks!
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2013-12-02 4:30 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
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2013-11-27 8:23 [Qemu-devel] [PATCH v6 0/5] add sunxi machine type liguang
2013-11-27 8:23 ` [Qemu-devel] [PATCH v6 1/5] hw/ptimer: add VMSTATE_PTIMER_ARRAY liguang
2013-11-29 11:01 ` Peter Maydell
2013-11-29 11:11 ` Peter Maydell
2013-12-02 4:28 ` Li Guang
2013-11-27 8:23 ` [Qemu-devel] [PATCH v6 2/5] hw/timer: add sunxi timer device liguang
2013-11-27 8:23 ` [Qemu-devel] [PATCH v6 3/5] hw/intc: add sunxi interrupt controller device liguang
2013-11-27 8:23 ` [Qemu-devel] [PATCH v6 4/5] hw/arm: add sunxi machine type liguang
2013-11-27 8:23 ` [Qemu-devel] [PATCH v6 5/5] MAINTAINERS: add myself to maintain sunxi machine liguang
2013-11-27 8:28 ` [Qemu-devel] [PATCH v6 0/5] add sunxi machine type Peter Crosthwaite
2013-11-27 8:35 ` Li Guang
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