From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51701) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VleQQ-0003Kb-J2 for qemu-devel@nongnu.org; Wed, 27 Nov 2013 07:41:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VleQK-00013b-Ka for qemu-devel@nongnu.org; Wed, 27 Nov 2013 07:41:02 -0500 Received: from mx1.redhat.com ([209.132.183.28]:21491) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VleQK-00013X-CX for qemu-devel@nongnu.org; Wed, 27 Nov 2013 07:40:56 -0500 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id rARCet1n014406 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Wed, 27 Nov 2013 07:40:55 -0500 Message-ID: <5295E854.5010604@redhat.com> Date: Wed, 27 Nov 2013 13:40:52 +0100 From: Laszlo Ersek MIME-Version: 1.0 References: <1385553451-1352-1-git-send-email-kraxel@redhat.com> In-Reply-To: <1385553451-1352-1-git-send-email-kraxel@redhat.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v2] piix: fix 32bit pci hole List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Gerd Hoffmann Cc: qemu-devel@nongnu.org On 11/27/13 12:57, Gerd Hoffmann wrote: > Make the 32bit pci hole start at end of ram, so all possible address > space is covered. Of course the firmware can use less than that. > Leaving space unused is no problem, mapping pci bars outside the > hole causes problems though. > > Signed-off-by: Gerd Hoffmann > --- > hw/pci-host/piix.c | 10 +--------- > 1 file changed, 1 insertion(+), 9 deletions(-) > > diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c > index edc974e..8e41ac1 100644 > --- a/hw/pci-host/piix.c > +++ b/hw/pci-host/piix.c > @@ -345,15 +345,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, > f->ram_memory = ram_memory; > > i440fx = I440FX_PCI_HOST_BRIDGE(dev); > - /* Set PCI window size the way seabios has always done it. */ > - /* Power of 2 so bios can cover it with a single MTRR */ > - if (ram_size <= 0x80000000) { > - i440fx->pci_info.w32.begin = 0x80000000; > - } else if (ram_size <= 0xc0000000) { > - i440fx->pci_info.w32.begin = 0xc0000000; > - } else { > - i440fx->pci_info.w32.begin = 0xe0000000; > - } > + i440fx->pci_info.w32.begin = pci_hole_start; > > memory_region_init_alias(&f->pci_hole, OBJECT(d), "pci-hole", f->pci_address_space, > pci_hole_start, pci_hole_size); > Reviewed-by: Laszlo Ersek Thanks! Laszlo