* [Qemu-devel] [PATCH 2/2] target-i386: Intel MPX
@ 2013-12-02 16:42 Liu, Jinsong
2013-12-02 17:32 ` Paolo Bonzini
0 siblings, 1 reply; 3+ messages in thread
From: Liu, Jinsong @ 2013-12-02 16:42 UTC (permalink / raw)
To: Paolo Bonzini, Gleb Natapov, qemu-devel@nongnu.org, kvm
Cc: haoxudong.hao@gmail.com
[-- Attachment #1: Type: text/plain, Size: 2169 bytes --]
>From 1a199d68265ffeb0234530f29d92a00a5edeff75 Mon Sep 17 00:00:00 2001
From: Liu Jinsong <jinsong.liu@intel.com>
Date: Tue, 3 Dec 2013 05:08:19 +0800
Subject: [PATCH 2/2] target-i386: Intel MPX
Add some MPX related definiation, and hardcode sizes and offsets
of xsave features 3 and 4.
Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
---
target-i386/cpu.c | 4 ++++
target-i386/cpu.h | 10 +++++++---
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 544b57f..52ca029 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -336,6 +336,10 @@ typedef struct ExtSaveArea {
static const ExtSaveArea ext_save_areas[] = {
[2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
.offset = 0x240, .size = 0x100 },
+ [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
+ .offset = 0x3c0, .size = 0x40 },
+ [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
+ .offset = 0x400, .size = 0x10 },
};
const char *get_register_name_32(unsigned int reg)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index ea373e8..2975644 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -380,9 +380,12 @@
#define MSR_VM_HSAVE_PA 0xc0010117
-#define XSTATE_FP 1
-#define XSTATE_SSE 2
-#define XSTATE_YMM 4
+#define XSTATE_FP (1ULL << 0)
+#define XSTATE_SSE (1ULL << 1)
+#define XSTATE_YMM (1ULL << 2)
+#define XSTATE_BNDREGS (1ULL << 3)
+#define XSTATE_BNDCSR (1ULL << 4)
+
/* CPUID feature words */
typedef enum FeatureWord {
@@ -545,6 +548,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EBX_ERMS (1 << 9)
#define CPUID_7_0_EBX_INVPCID (1 << 10)
#define CPUID_7_0_EBX_RTM (1 << 11)
+#define CPUID_7_0_EBX_MPX (1 << 14)
#define CPUID_7_0_EBX_RDSEED (1 << 18)
#define CPUID_7_0_EBX_ADX (1 << 19)
#define CPUID_7_0_EBX_SMAP (1 << 20)
--
1.7.1
[-- Attachment #2: 0002-target-i386-Intel-MPX.patch --]
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From 1a199d68265ffeb0234530f29d92a00a5edeff75 Mon Sep 17 00:00:00 2001
From: Liu Jinsong <jinsong.liu@intel.com>
Date: Tue, 3 Dec 2013 05:08:19 +0800
Subject: [PATCH 2/2] target-i386: Intel MPX
Add some MPX related definiation, and hardcode sizes and offsets
of xsave features 3 and 4.
Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
---
target-i386/cpu.c | 4 ++++
target-i386/cpu.h | 10 +++++++---
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 544b57f..52ca029 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -336,6 +336,10 @@ typedef struct ExtSaveArea {
static const ExtSaveArea ext_save_areas[] = {
[2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
.offset = 0x240, .size = 0x100 },
+ [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
+ .offset = 0x3c0, .size = 0x40 },
+ [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
+ .offset = 0x400, .size = 0x10 },
};
const char *get_register_name_32(unsigned int reg)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index ea373e8..2975644 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -380,9 +380,12 @@
#define MSR_VM_HSAVE_PA 0xc0010117
-#define XSTATE_FP 1
-#define XSTATE_SSE 2
-#define XSTATE_YMM 4
+#define XSTATE_FP (1ULL << 0)
+#define XSTATE_SSE (1ULL << 1)
+#define XSTATE_YMM (1ULL << 2)
+#define XSTATE_BNDREGS (1ULL << 3)
+#define XSTATE_BNDCSR (1ULL << 4)
+
/* CPUID feature words */
typedef enum FeatureWord {
@@ -545,6 +548,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EBX_ERMS (1 << 9)
#define CPUID_7_0_EBX_INVPCID (1 << 10)
#define CPUID_7_0_EBX_RTM (1 << 11)
+#define CPUID_7_0_EBX_MPX (1 << 14)
#define CPUID_7_0_EBX_RDSEED (1 << 18)
#define CPUID_7_0_EBX_ADX (1 << 19)
#define CPUID_7_0_EBX_SMAP (1 << 20)
--
1.7.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH 2/2] target-i386: Intel MPX
2013-12-02 16:42 [Qemu-devel] [PATCH 2/2] target-i386: Intel MPX Liu, Jinsong
@ 2013-12-02 17:32 ` Paolo Bonzini
2013-12-04 7:39 ` Liu, Jinsong
0 siblings, 1 reply; 3+ messages in thread
From: Paolo Bonzini @ 2013-12-02 17:32 UTC (permalink / raw)
To: Liu, Jinsong
Cc: haoxudong.hao@gmail.com, qemu-devel@nongnu.org, Gleb Natapov, kvm
Il 02/12/2013 17:42, Liu, Jinsong ha scritto:
> From 1a199d68265ffeb0234530f29d92a00a5edeff75 Mon Sep 17 00:00:00 2001
> From: Liu Jinsong <jinsong.liu@intel.com>
> Date: Tue, 3 Dec 2013 05:08:19 +0800
> Subject: [PATCH 2/2] target-i386: Intel MPX
>
> Add some MPX related definiation, and hardcode sizes and offsets
> of xsave features 3 and 4.
>
> Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
kvm_get/put_xsave support is still missing.
> ---
> target-i386/cpu.c | 4 ++++
> target-i386/cpu.h | 10 +++++++---
> 2 files changed, 11 insertions(+), 3 deletions(-)
>
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 544b57f..52ca029 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -336,6 +336,10 @@ typedef struct ExtSaveArea {
> static const ExtSaveArea ext_save_areas[] = {
> [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
> .offset = 0x240, .size = 0x100 },
> + [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
> + .offset = 0x3c0, .size = 0x40 },
> + [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
> + .offset = 0x400, .size = 0x10 },
> };
>
> const char *get_register_name_32(unsigned int reg)
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index ea373e8..2975644 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -380,9 +380,12 @@
>
> #define MSR_VM_HSAVE_PA 0xc0010117
>
> -#define XSTATE_FP 1
> -#define XSTATE_SSE 2
> -#define XSTATE_YMM 4
> +#define XSTATE_FP (1ULL << 0)
> +#define XSTATE_SSE (1ULL << 1)
> +#define XSTATE_YMM (1ULL << 2)
> +#define XSTATE_BNDREGS (1ULL << 3)
> +#define XSTATE_BNDCSR (1ULL << 4)
> +
>
> /* CPUID feature words */
> typedef enum FeatureWord {
> @@ -545,6 +548,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
> #define CPUID_7_0_EBX_ERMS (1 << 9)
> #define CPUID_7_0_EBX_INVPCID (1 << 10)
> #define CPUID_7_0_EBX_RTM (1 << 11)
> +#define CPUID_7_0_EBX_MPX (1 << 14)
> #define CPUID_7_0_EBX_RDSEED (1 << 18)
> #define CPUID_7_0_EBX_ADX (1 << 19)
> #define CPUID_7_0_EBX_SMAP (1 << 20)
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH 2/2] target-i386: Intel MPX
2013-12-02 17:32 ` Paolo Bonzini
@ 2013-12-04 7:39 ` Liu, Jinsong
0 siblings, 0 replies; 3+ messages in thread
From: Liu, Jinsong @ 2013-12-04 7:39 UTC (permalink / raw)
To: Paolo Bonzini
Cc: haoxudong.hao@gmail.com, qemu-devel@nongnu.org, Gleb Natapov, kvm
Paolo Bonzini wrote:
> Il 02/12/2013 17:42, Liu, Jinsong ha scritto:
>> From 1a199d68265ffeb0234530f29d92a00a5edeff75 Mon Sep 17 00:00:00
>> 2001 From: Liu Jinsong <jinsong.liu@intel.com>
>> Date: Tue, 3 Dec 2013 05:08:19 +0800
>> Subject: [PATCH 2/2] target-i386: Intel MPX
>>
>> Add some MPX related definiation, and hardcode sizes and offsets
>> of xsave features 3 and 4.
>>
>> Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
>
> kvm_get/put_xsave support is still missing.
Thanks! Will add kvm_get/put_xsave support and send out later.
Jinsong
>
>> ---
>> target-i386/cpu.c | 4 ++++
>> target-i386/cpu.h | 10 +++++++---
>> 2 files changed, 11 insertions(+), 3 deletions(-)
>>
>> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
>> index 544b57f..52ca029 100644
>> --- a/target-i386/cpu.c
>> +++ b/target-i386/cpu.c
>> @@ -336,6 +336,10 @@ typedef struct ExtSaveArea {
>> static const ExtSaveArea ext_save_areas[] = {
>> [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
>> .offset = 0x240, .size = 0x100 },
>> + [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
>> + .offset = 0x3c0, .size = 0x40 },
>> + [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
>> + .offset = 0x400, .size = 0x10 },
>> };
>>
>> const char *get_register_name_32(unsigned int reg)
>> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
>> index ea373e8..2975644 100644
>> --- a/target-i386/cpu.h
>> +++ b/target-i386/cpu.h
>> @@ -380,9 +380,12 @@
>>
>> #define MSR_VM_HSAVE_PA 0xc0010117
>>
>> -#define XSTATE_FP 1
>> -#define XSTATE_SSE 2
>> -#define XSTATE_YMM 4
>> +#define XSTATE_FP (1ULL << 0)
>> +#define XSTATE_SSE (1ULL << 1)
>> +#define XSTATE_YMM (1ULL << 2)
>> +#define XSTATE_BNDREGS (1ULL << 3)
>> +#define XSTATE_BNDCSR (1ULL << 4) +
>>
>> /* CPUID feature words */
>> typedef enum FeatureWord {
>> @@ -545,6 +548,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
>> #define CPUID_7_0_EBX_ERMS (1 << 9)
>> #define CPUID_7_0_EBX_INVPCID (1 << 10)
>> #define CPUID_7_0_EBX_RTM (1 << 11)
>> +#define CPUID_7_0_EBX_MPX (1 << 14)
>> #define CPUID_7_0_EBX_RDSEED (1 << 18)
>> #define CPUID_7_0_EBX_ADX (1 << 19)
>> #define CPUID_7_0_EBX_SMAP (1 << 20)
^ permalink raw reply [flat|nested] 3+ messages in thread
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2013-12-02 17:32 ` Paolo Bonzini
2013-12-04 7:39 ` Liu, Jinsong
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