From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51973) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VnXMM-0004Lj-Gy for qemu-devel@nongnu.org; Mon, 02 Dec 2013 12:32:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VnXMG-0002ly-My for qemu-devel@nongnu.org; Mon, 02 Dec 2013 12:32:38 -0500 Received: from mail-ea0-x234.google.com ([2a00:1450:4013:c01::234]:41945) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VnXMG-0002lo-F4 for qemu-devel@nongnu.org; Mon, 02 Dec 2013 12:32:32 -0500 Received: by mail-ea0-f180.google.com with SMTP id f15so9191254eak.25 for ; Mon, 02 Dec 2013 09:32:31 -0800 (PST) Sender: Paolo Bonzini Message-ID: <529CC42B.3090201@redhat.com> Date: Mon, 02 Dec 2013 18:32:27 +0100 From: Paolo Bonzini MIME-Version: 1.0 References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 2/2] target-i386: Intel MPX List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Liu, Jinsong" Cc: "haoxudong.hao@gmail.com" , "qemu-devel@nongnu.org" , Gleb Natapov , kvm Il 02/12/2013 17:42, Liu, Jinsong ha scritto: > From 1a199d68265ffeb0234530f29d92a00a5edeff75 Mon Sep 17 00:00:00 2001 > From: Liu Jinsong > Date: Tue, 3 Dec 2013 05:08:19 +0800 > Subject: [PATCH 2/2] target-i386: Intel MPX > > Add some MPX related definiation, and hardcode sizes and offsets > of xsave features 3 and 4. > > Signed-off-by: Liu Jinsong kvm_get/put_xsave support is still missing. > --- > target-i386/cpu.c | 4 ++++ > target-i386/cpu.h | 10 +++++++--- > 2 files changed, 11 insertions(+), 3 deletions(-) > > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index 544b57f..52ca029 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@ -336,6 +336,10 @@ typedef struct ExtSaveArea { > static const ExtSaveArea ext_save_areas[] = { > [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX, > .offset = 0x240, .size = 0x100 }, > + [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, > + .offset = 0x3c0, .size = 0x40 }, > + [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX, > + .offset = 0x400, .size = 0x10 }, > }; > > const char *get_register_name_32(unsigned int reg) > diff --git a/target-i386/cpu.h b/target-i386/cpu.h > index ea373e8..2975644 100644 > --- a/target-i386/cpu.h > +++ b/target-i386/cpu.h > @@ -380,9 +380,12 @@ > > #define MSR_VM_HSAVE_PA 0xc0010117 > > -#define XSTATE_FP 1 > -#define XSTATE_SSE 2 > -#define XSTATE_YMM 4 > +#define XSTATE_FP (1ULL << 0) > +#define XSTATE_SSE (1ULL << 1) > +#define XSTATE_YMM (1ULL << 2) > +#define XSTATE_BNDREGS (1ULL << 3) > +#define XSTATE_BNDCSR (1ULL << 4) > + > > /* CPUID feature words */ > typedef enum FeatureWord { > @@ -545,6 +548,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; > #define CPUID_7_0_EBX_ERMS (1 << 9) > #define CPUID_7_0_EBX_INVPCID (1 << 10) > #define CPUID_7_0_EBX_RTM (1 << 11) > +#define CPUID_7_0_EBX_MPX (1 << 14) > #define CPUID_7_0_EBX_RDSEED (1 << 18) > #define CPUID_7_0_EBX_ADX (1 << 19) > #define CPUID_7_0_EBX_SMAP (1 << 20) >