From: Richard Henderson <rth@twiddle.net>
To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: patches@linaro.org, Michael Matz <matz@suse.de>,
Alexander Graf <agraf@suse.de>,
C Fontana <claudio.fontana@linaro.org>,
Dirk Mueller <dmueller@suse.de>,
Laurent Desnogues <laurent.desnogues@gmail.com>,
kvmarm@lists.cs.columbia.edu
Subject: Re: [Qemu-devel] [PATCH 09/12] target-arm: A64: add support for BR, BLR and RET insns
Date: Wed, 04 Dec 2013 13:00:06 +1300 [thread overview]
Message-ID: <529E7086.4030706@twiddle.net> (raw)
In-Reply-To: <1386107477-24165-10-git-send-email-peter.maydell@linaro.org>
On 12/04/2013 10:51 AM, Peter Maydell wrote:
> From: Alexander Graf <agraf@suse.de>
>
> Implement BR, BLR and RET. This is all of the 'unconditional
> branch (register)' instruction category except for ERET
> and DPRS (which are system mode only).
>
> Signed-off-by: Alexander Graf <agraf@suse.de>
> [claudio: reimplemented on top of new decoder structure]
> Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target-arm/translate-a64.c | 43 +++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 41 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson <rth@twiddle.net>
r~
next prev parent reply other threads:[~2013-12-04 0:00 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-12-03 21:51 [Qemu-devel] [PATCH 00/12] target-arm: A64 decoder, foundation plus branches Peter Maydell
2013-12-03 21:51 ` [Qemu-devel] [PATCH 01/12] target-arm: Split A64 from A32/T32 gen_intermediate_code_internal() Peter Maydell
2013-12-03 23:34 ` Richard Henderson
2013-12-03 21:51 ` [Qemu-devel] [PATCH 02/12] target-arm: A64: add set_pc cpu method Peter Maydell
2013-12-03 23:35 ` Richard Henderson
2013-12-03 21:51 ` [Qemu-devel] [PATCH 03/12] target-arm: A64: provide functions for accessing FPCR and FPSR Peter Maydell
2013-12-03 23:39 ` Richard Henderson
2013-12-03 21:51 ` [Qemu-devel] [PATCH 04/12] target-arm: Support fp registers in gdb stub Peter Maydell
2013-12-03 23:40 ` Richard Henderson
2013-12-03 21:51 ` [Qemu-devel] [PATCH 05/12] target-arm: A64: add stubs for a64 specific helpers Peter Maydell
2013-12-03 23:41 ` Richard Henderson
2013-12-03 21:51 ` [Qemu-devel] [PATCH 06/12] target-arm: A64: provide skeleton for a64 insn decoding Peter Maydell
2013-12-03 23:41 ` Richard Henderson
2013-12-03 21:51 ` [Qemu-devel] [PATCH 07/12] target-arm: A64: expand decoding skeleton for system instructions Peter Maydell
2013-12-03 23:15 ` Christopher Covington
2013-12-04 0:21 ` Peter Maydell
2013-12-03 23:49 ` Richard Henderson
2013-12-03 21:51 ` [Qemu-devel] [PATCH 08/12] target-arm: A64: add support for B and BL insns Peter Maydell
2013-12-03 21:51 ` [Qemu-devel] [PATCH 09/12] target-arm: A64: add support for BR, BLR and RET insns Peter Maydell
2013-12-04 0:00 ` Richard Henderson [this message]
2013-12-03 21:51 ` [Qemu-devel] [PATCH 10/12] target-arm: A64: add support for conditional branches Peter Maydell
2013-12-04 0:03 ` Richard Henderson
2013-12-04 0:22 ` Peter Maydell
2013-12-03 21:51 ` [Qemu-devel] [PATCH 11/12] target-arm: A64: add support for 'test and branch' imm Peter Maydell
2013-12-04 0:07 ` Richard Henderson
2013-12-04 0:22 ` Peter Maydell
2013-12-03 21:51 ` [Qemu-devel] [PATCH 12/12] target-arm: A64: add support for compare and branch imm Peter Maydell
2013-12-04 0:10 ` Richard Henderson
2013-12-04 0:32 ` Peter Maydell
2013-12-04 0:48 ` Richard Henderson
2013-12-04 11:05 ` Peter Maydell
2013-12-04 17:02 ` Peter Maydell
2013-12-04 17:31 ` Richard Henderson
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