* [Qemu-devel] [PATCH v2 2/2] target-i386: Intel MPX
@ 2013-12-04 7:56 Liu, Jinsong
2013-12-04 8:52 ` Paolo Bonzini
0 siblings, 1 reply; 6+ messages in thread
From: Liu, Jinsong @ 2013-12-04 7:56 UTC (permalink / raw)
To: Paolo Bonzini, Gleb Natapov, qemu-devel@nongnu.org, kvm
[-- Attachment #1: Type: text/plain, Size: 4203 bytes --]
>From 256484fd75d4eb4d248e5e0f493f16182da59dc2 Mon Sep 17 00:00:00 2001
From: Liu Jinsong <jinsong.liu@intel.com>
Date: Wed, 4 Dec 2013 16:56:49 +0800
Subject: [PATCH v2 2/2] target-i386: Intel MPX
Add some MPX related definiation, and hardcode sizes and offsets
of xsave features 3 and 4. It also add corresponding part to
kvm_get/put_xsave.
Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
---
target-i386/cpu.c | 4 ++++
target-i386/cpu.h | 24 +++++++++++++++++++++---
target-i386/kvm.c | 10 ++++++++++
3 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 544b57f..52ca029 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -336,6 +336,10 @@ typedef struct ExtSaveArea {
static const ExtSaveArea ext_save_areas[] = {
[2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
.offset = 0x240, .size = 0x100 },
+ [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
+ .offset = 0x3c0, .size = 0x40 },
+ [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
+ .offset = 0x400, .size = 0x10 },
};
const char *get_register_name_32(unsigned int reg)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index ea373e8..4020591 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -380,9 +380,12 @@
#define MSR_VM_HSAVE_PA 0xc0010117
-#define XSTATE_FP 1
-#define XSTATE_SSE 2
-#define XSTATE_YMM 4
+#define XSTATE_FP (1ULL << 0)
+#define XSTATE_SSE (1ULL << 1)
+#define XSTATE_YMM (1ULL << 2)
+#define XSTATE_BNDREGS (1ULL << 3)
+#define XSTATE_BNDCSR (1ULL << 4)
+
/* CPUID feature words */
typedef enum FeatureWord {
@@ -545,6 +548,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EBX_ERMS (1 << 9)
#define CPUID_7_0_EBX_INVPCID (1 << 10)
#define CPUID_7_0_EBX_RTM (1 << 11)
+#define CPUID_7_0_EBX_MPX (1 << 14)
#define CPUID_7_0_EBX_RDSEED (1 << 18)
#define CPUID_7_0_EBX_ADX (1 << 19)
#define CPUID_7_0_EBX_SMAP (1 << 20)
@@ -695,6 +699,18 @@ typedef union {
uint64_t q;
} MMXReg;
+typedef struct BNDReg {
+ uint64_t lb;
+ uint64_t ub;
+} BNDReg;
+
+typedef struct BNDCSReg {
+ uint64_t cfg;
+ uint64_t pad;
+ uint64_t sts_lo;
+ uint64_t sts_hi;
+} BNDCSReg;
+
#ifdef HOST_WORDS_BIGENDIAN
#define XMM_B(n) _b[15 - (n)]
#define XMM_W(n) _w[7 - (n)]
@@ -912,6 +928,8 @@ typedef struct CPUX86State {
uint64_t xstate_bv;
XMMReg ymmh_regs[CPU_NB_REGS];
+ BNDReg bnd_regs[4];
+ BNDCSReg bndcs_regs;
uint64_t xcr0;
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 749aa09..347d3d3 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -980,6 +980,8 @@ static int kvm_put_fpu(X86CPU *cpu)
#define XSAVE_XMM_SPACE 40
#define XSAVE_XSTATE_BV 128
#define XSAVE_YMMH_SPACE 144
+#define XSAVE_BNDREGS 240
+#define XSAVE_BNDCSR 256
static int kvm_put_xsave(X86CPU *cpu)
{
@@ -1012,6 +1014,10 @@ static int kvm_put_xsave(X86CPU *cpu)
*(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
sizeof env->ymmh_regs);
+ memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
+ sizeof env->bnd_regs);
+ memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
+ sizeof(env->bndcs_regs));
r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
return r;
}
@@ -1294,6 +1300,10 @@ static int kvm_get_xsave(X86CPU *cpu)
env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
sizeof env->ymmh_regs);
+ memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
+ sizeof env->bnd_regs);
+ memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
+ sizeof(env->bndcs_regs));
return 0;
}
--
1.7.1
[-- Attachment #2: 0002-target-i386-Intel-MPX.patch --]
[-- Type: application/octet-stream, Size: 4204 bytes --]
From 256484fd75d4eb4d248e5e0f493f16182da59dc2 Mon Sep 17 00:00:00 2001
From: Liu Jinsong <jinsong.liu@intel.com>
Date: Wed, 4 Dec 2013 16:56:49 +0800
Subject: [PATCH v2 2/2] target-i386: Intel MPX
Add some MPX related definiation, and hardcode sizes and offsets
of xsave features 3 and 4. It also add corresponding part to
kvm_get/put_xsave.
Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
---
target-i386/cpu.c | 4 ++++
target-i386/cpu.h | 24 +++++++++++++++++++++---
target-i386/kvm.c | 10 ++++++++++
3 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 544b57f..52ca029 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -336,6 +336,10 @@ typedef struct ExtSaveArea {
static const ExtSaveArea ext_save_areas[] = {
[2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
.offset = 0x240, .size = 0x100 },
+ [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
+ .offset = 0x3c0, .size = 0x40 },
+ [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
+ .offset = 0x400, .size = 0x10 },
};
const char *get_register_name_32(unsigned int reg)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index ea373e8..4020591 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -380,9 +380,12 @@
#define MSR_VM_HSAVE_PA 0xc0010117
-#define XSTATE_FP 1
-#define XSTATE_SSE 2
-#define XSTATE_YMM 4
+#define XSTATE_FP (1ULL << 0)
+#define XSTATE_SSE (1ULL << 1)
+#define XSTATE_YMM (1ULL << 2)
+#define XSTATE_BNDREGS (1ULL << 3)
+#define XSTATE_BNDCSR (1ULL << 4)
+
/* CPUID feature words */
typedef enum FeatureWord {
@@ -545,6 +548,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EBX_ERMS (1 << 9)
#define CPUID_7_0_EBX_INVPCID (1 << 10)
#define CPUID_7_0_EBX_RTM (1 << 11)
+#define CPUID_7_0_EBX_MPX (1 << 14)
#define CPUID_7_0_EBX_RDSEED (1 << 18)
#define CPUID_7_0_EBX_ADX (1 << 19)
#define CPUID_7_0_EBX_SMAP (1 << 20)
@@ -695,6 +699,18 @@ typedef union {
uint64_t q;
} MMXReg;
+typedef struct BNDReg {
+ uint64_t lb;
+ uint64_t ub;
+} BNDReg;
+
+typedef struct BNDCSReg {
+ uint64_t cfg;
+ uint64_t pad;
+ uint64_t sts_lo;
+ uint64_t sts_hi;
+} BNDCSReg;
+
#ifdef HOST_WORDS_BIGENDIAN
#define XMM_B(n) _b[15 - (n)]
#define XMM_W(n) _w[7 - (n)]
@@ -912,6 +928,8 @@ typedef struct CPUX86State {
uint64_t xstate_bv;
XMMReg ymmh_regs[CPU_NB_REGS];
+ BNDReg bnd_regs[4];
+ BNDCSReg bndcs_regs;
uint64_t xcr0;
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 749aa09..347d3d3 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -980,6 +980,8 @@ static int kvm_put_fpu(X86CPU *cpu)
#define XSAVE_XMM_SPACE 40
#define XSAVE_XSTATE_BV 128
#define XSAVE_YMMH_SPACE 144
+#define XSAVE_BNDREGS 240
+#define XSAVE_BNDCSR 256
static int kvm_put_xsave(X86CPU *cpu)
{
@@ -1012,6 +1014,10 @@ static int kvm_put_xsave(X86CPU *cpu)
*(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
sizeof env->ymmh_regs);
+ memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
+ sizeof env->bnd_regs);
+ memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
+ sizeof(env->bndcs_regs));
r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
return r;
}
@@ -1294,6 +1300,10 @@ static int kvm_get_xsave(X86CPU *cpu)
env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
sizeof env->ymmh_regs);
+ memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
+ sizeof env->bnd_regs);
+ memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
+ sizeof(env->bndcs_regs));
return 0;
}
--
1.7.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH v2 2/2] target-i386: Intel MPX
2013-12-04 7:56 [Qemu-devel] [PATCH v2 2/2] target-i386: Intel MPX Liu, Jinsong
@ 2013-12-04 8:52 ` Paolo Bonzini
2013-12-04 11:30 ` Liu, Jinsong
0 siblings, 1 reply; 6+ messages in thread
From: Paolo Bonzini @ 2013-12-04 8:52 UTC (permalink / raw)
To: Liu, Jinsong; +Cc: qemu-devel@nongnu.org, Gleb Natapov, kvm
Il 04/12/2013 08:56, Liu, Jinsong ha scritto:
> From 256484fd75d4eb4d248e5e0f493f16182da59dc2 Mon Sep 17 00:00:00 2001
> From: Liu Jinsong <jinsong.liu@intel.com>
> Date: Wed, 4 Dec 2013 16:56:49 +0800
> Subject: [PATCH v2 2/2] target-i386: Intel MPX
>
> Add some MPX related definiation, and hardcode sizes and offsets
> of xsave features 3 and 4. It also add corresponding part to
> kvm_get/put_xsave.
>
> Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
> ---
> target-i386/cpu.c | 4 ++++
> target-i386/cpu.h | 24 +++++++++++++++++++++---
> target-i386/kvm.c | 10 ++++++++++
> 3 files changed, 35 insertions(+), 3 deletions(-)
>
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 544b57f..52ca029 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -336,6 +336,10 @@ typedef struct ExtSaveArea {
> static const ExtSaveArea ext_save_areas[] = {
> [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
> .offset = 0x240, .size = 0x100 },
> + [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
> + .offset = 0x3c0, .size = 0x40 },
> + [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
> + .offset = 0x400, .size = 0x10 },
> };
>
> const char *get_register_name_32(unsigned int reg)
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index ea373e8..4020591 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -380,9 +380,12 @@
>
> #define MSR_VM_HSAVE_PA 0xc0010117
>
> -#define XSTATE_FP 1
> -#define XSTATE_SSE 2
> -#define XSTATE_YMM 4
> +#define XSTATE_FP (1ULL << 0)
> +#define XSTATE_SSE (1ULL << 1)
> +#define XSTATE_YMM (1ULL << 2)
> +#define XSTATE_BNDREGS (1ULL << 3)
> +#define XSTATE_BNDCSR (1ULL << 4)
> +
>
> /* CPUID feature words */
> typedef enum FeatureWord {
> @@ -545,6 +548,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
> #define CPUID_7_0_EBX_ERMS (1 << 9)
> #define CPUID_7_0_EBX_INVPCID (1 << 10)
> #define CPUID_7_0_EBX_RTM (1 << 11)
> +#define CPUID_7_0_EBX_MPX (1 << 14)
> #define CPUID_7_0_EBX_RDSEED (1 << 18)
> #define CPUID_7_0_EBX_ADX (1 << 19)
> #define CPUID_7_0_EBX_SMAP (1 << 20)
> @@ -695,6 +699,18 @@ typedef union {
> uint64_t q;
> } MMXReg;
>
> +typedef struct BNDReg {
> + uint64_t lb;
> + uint64_t ub;
> +} BNDReg;
> +
> +typedef struct BNDCSReg {
> + uint64_t cfg;
> + uint64_t pad;
> + uint64_t sts_lo;
> + uint64_t sts_hi;
> +} BNDCSReg;
> +
> #ifdef HOST_WORDS_BIGENDIAN
> #define XMM_B(n) _b[15 - (n)]
> #define XMM_W(n) _w[7 - (n)]
> @@ -912,6 +928,8 @@ typedef struct CPUX86State {
>
> uint64_t xstate_bv;
> XMMReg ymmh_regs[CPU_NB_REGS];
> + BNDReg bnd_regs[4];
> + BNDCSReg bndcs_regs;
>
> uint64_t xcr0;
>
> diff --git a/target-i386/kvm.c b/target-i386/kvm.c
> index 749aa09..347d3d3 100644
> --- a/target-i386/kvm.c
> +++ b/target-i386/kvm.c
> @@ -980,6 +980,8 @@ static int kvm_put_fpu(X86CPU *cpu)
> #define XSAVE_XMM_SPACE 40
> #define XSAVE_XSTATE_BV 128
> #define XSAVE_YMMH_SPACE 144
> +#define XSAVE_BNDREGS 240
> +#define XSAVE_BNDCSR 256
>
> static int kvm_put_xsave(X86CPU *cpu)
> {
> @@ -1012,6 +1014,10 @@ static int kvm_put_xsave(X86CPU *cpu)
> *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
> memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
> sizeof env->ymmh_regs);
> + memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
> + sizeof env->bnd_regs);
> + memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
> + sizeof(env->bndcs_regs));
> r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
> return r;
> }
> @@ -1294,6 +1300,10 @@ static int kvm_get_xsave(X86CPU *cpu)
> env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
> memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
> sizeof env->ymmh_regs);
> + memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
> + sizeof env->bnd_regs);
> + memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
> + sizeof(env->bndcs_regs));
> return 0;
> }
Almost there. Migration (vmstate) is still missing.
Paolo
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH v2 2/2] target-i386: Intel MPX
2013-12-04 8:52 ` Paolo Bonzini
@ 2013-12-04 11:30 ` Liu, Jinsong
2013-12-04 17:23 ` Paolo Bonzini
0 siblings, 1 reply; 6+ messages in thread
From: Liu, Jinsong @ 2013-12-04 11:30 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel@nongnu.org, Gleb Natapov, kvm
>
> Almost there. Migration (vmstate) is still missing.
>
Like this:
==================
>From faead85c0dbe62da896e0ed9e165d98e10216968 Mon Sep 17 00:00:00 2001
From: Liu Jinsong <jinsong.liu@intel.com>
Date: Wed, 4 Dec 2013 16:56:49 +0800
Subject: [PATCH 2/2] target-i386: Intel MPX
Add some MPX related definiation, and hardcode sizes and offsets
of xsave features 3 and 4. It also add corresponding part to
kvm_get/put_xsave, and vmstate.
Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
---
target-i386/cpu.c | 4 ++++
target-i386/cpu.h | 22 +++++++++++++++++++---
target-i386/kvm.c | 10 ++++++++++
target-i386/machine.c | 32 ++++++++++++++++++++++++++++++++
4 files changed, 65 insertions(+), 3 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 544b57f..52ca029 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -336,6 +336,10 @@ typedef struct ExtSaveArea {
static const ExtSaveArea ext_save_areas[] = {
[2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
.offset = 0x240, .size = 0x100 },
+ [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
+ .offset = 0x3c0, .size = 0x40 },
+ [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
+ .offset = 0x400, .size = 0x10 },
};
const char *get_register_name_32(unsigned int reg)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index ea373e8..5c1dd17 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -380,9 +380,12 @@
#define MSR_VM_HSAVE_PA 0xc0010117
-#define XSTATE_FP 1
-#define XSTATE_SSE 2
-#define XSTATE_YMM 4
+#define XSTATE_FP (1ULL << 0)
+#define XSTATE_SSE (1ULL << 1)
+#define XSTATE_YMM (1ULL << 2)
+#define XSTATE_BNDREGS (1ULL << 3)
+#define XSTATE_BNDCSR (1ULL << 4)
+
/* CPUID feature words */
typedef enum FeatureWord {
@@ -545,6 +548,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EBX_ERMS (1 << 9)
#define CPUID_7_0_EBX_INVPCID (1 << 10)
#define CPUID_7_0_EBX_RTM (1 << 11)
+#define CPUID_7_0_EBX_MPX (1 << 14)
#define CPUID_7_0_EBX_RDSEED (1 << 18)
#define CPUID_7_0_EBX_ADX (1 << 19)
#define CPUID_7_0_EBX_SMAP (1 << 20)
@@ -695,6 +699,16 @@ typedef union {
uint64_t q;
} MMXReg;
+typedef struct BNDReg {
+ uint64_t lb;
+ uint64_t ub;
+} BNDReg;
+
+typedef struct BNDCSReg {
+ uint64_t cfg;
+ uint64_t sts;
+} BNDCSReg;
+
#ifdef HOST_WORDS_BIGENDIAN
#define XMM_B(n) _b[15 - (n)]
#define XMM_W(n) _w[7 - (n)]
@@ -912,6 +926,8 @@ typedef struct CPUX86State {
uint64_t xstate_bv;
XMMReg ymmh_regs[CPU_NB_REGS];
+ BNDReg bnd_regs[4];
+ BNDCSReg bndcs_regs;
uint64_t xcr0;
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 749aa09..347d3d3 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -980,6 +980,8 @@ static int kvm_put_fpu(X86CPU *cpu)
#define XSAVE_XMM_SPACE 40
#define XSAVE_XSTATE_BV 128
#define XSAVE_YMMH_SPACE 144
+#define XSAVE_BNDREGS 240
+#define XSAVE_BNDCSR 256
static int kvm_put_xsave(X86CPU *cpu)
{
@@ -1012,6 +1014,10 @@ static int kvm_put_xsave(X86CPU *cpu)
*(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
sizeof env->ymmh_regs);
+ memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
+ sizeof env->bnd_regs);
+ memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
+ sizeof(env->bndcs_regs));
r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
return r;
}
@@ -1294,6 +1300,10 @@ static int kvm_get_xsave(X86CPU *cpu)
env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
sizeof env->ymmh_regs);
+ memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
+ sizeof env->bnd_regs);
+ memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
+ sizeof(env->bndcs_regs));
return 0;
}
diff --git a/target-i386/machine.c b/target-i386/machine.c
index e568da2..ca8be7d 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -63,6 +63,36 @@ static const VMStateDescription vmstate_ymmh_reg = {
#define VMSTATE_YMMH_REGS_VARS(_field, _state, _n, _v) \
VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_ymmh_reg, XMMReg)
+static const VMStateDescription vmstate_bnd_regs = {
+ .name = "bnd_regs",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT64(lb, BNDReg),
+ VMSTATE_UINT64(ub, BNDReg),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+#define VMSTATE_BNDREG_VARS(_field, _state, _n, _v) \
+ VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_bnd_regs, BNDReg)
+
+static const VMStateDescription vmstate_bndcs_regs = {
+ .name = "bndcs_regs",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT64(cfg, BNDCSReg),
+ VMSTATE_UINT64(sts, BNDCSReg),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+#define VMSTATE_BNDCSR_VARS(_field, _state, _v) \
+ VMSTATE_STRUCT(_field, _state, _v, vmstate_bndcs_regs, BNDCSReg)
+
static const VMStateDescription vmstate_mtrr_var = {
.name = "mtrr_var",
.version_id = 1,
@@ -606,6 +636,8 @@ const VMStateDescription vmstate_x86_cpu = {
VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
VMSTATE_YMMH_REGS_VARS(env.ymmh_regs, X86CPU, CPU_NB_REGS, 12),
+ VMSTATE_BNDREG_VARS(env.bnd_regs, X86CPU, 4, 12),
+ VMSTATE_BNDCSR_VARS(env.bndcs_regs, X86CPU, 12),
VMSTATE_END_OF_LIST()
/* The above list is not sorted /wrt version numbers, watch out! */
},
--
1.7.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH v2 2/2] target-i386: Intel MPX
2013-12-04 11:30 ` Liu, Jinsong
@ 2013-12-04 17:23 ` Paolo Bonzini
2013-12-05 15:26 ` Liu, Jinsong
0 siblings, 1 reply; 6+ messages in thread
From: Paolo Bonzini @ 2013-12-04 17:23 UTC (permalink / raw)
To: Liu, Jinsong; +Cc: qemu-devel@nongnu.org, Gleb Natapov, kvm
Il 04/12/2013 12:30, Liu, Jinsong ha scritto:
>> >
>> > Almost there. Migration (vmstate) is still missing.
>> >
> Like this:
>
> ==================
> From faead85c0dbe62da896e0ed9e165d98e10216968 Mon Sep 17 00:00:00 2001
> From: Liu Jinsong <jinsong.liu@intel.com>
> Date: Wed, 4 Dec 2013 16:56:49 +0800
> Subject: [PATCH 2/2] target-i386: Intel MPX
>
> Add some MPX related definiation, and hardcode sizes and offsets
> of xsave features 3 and 4. It also add corresponding part to
> kvm_get/put_xsave, and vmstate.
>
> Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
> ---
> target-i386/cpu.c | 4 ++++
> target-i386/cpu.h | 22 +++++++++++++++++++---
> target-i386/kvm.c | 10 ++++++++++
> target-i386/machine.c | 32 ++++++++++++++++++++++++++++++++
> 4 files changed, 65 insertions(+), 3 deletions(-)
>
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 544b57f..52ca029 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -336,6 +336,10 @@ typedef struct ExtSaveArea {
> static const ExtSaveArea ext_save_areas[] = {
> [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
> .offset = 0x240, .size = 0x100 },
> + [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
> + .offset = 0x3c0, .size = 0x40 },
> + [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
> + .offset = 0x400, .size = 0x10 },
> };
>
> const char *get_register_name_32(unsigned int reg)
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index ea373e8..5c1dd17 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -380,9 +380,12 @@
>
> #define MSR_VM_HSAVE_PA 0xc0010117
>
> -#define XSTATE_FP 1
> -#define XSTATE_SSE 2
> -#define XSTATE_YMM 4
> +#define XSTATE_FP (1ULL << 0)
> +#define XSTATE_SSE (1ULL << 1)
> +#define XSTATE_YMM (1ULL << 2)
> +#define XSTATE_BNDREGS (1ULL << 3)
> +#define XSTATE_BNDCSR (1ULL << 4)
> +
>
> /* CPUID feature words */
> typedef enum FeatureWord {
> @@ -545,6 +548,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
> #define CPUID_7_0_EBX_ERMS (1 << 9)
> #define CPUID_7_0_EBX_INVPCID (1 << 10)
> #define CPUID_7_0_EBX_RTM (1 << 11)
> +#define CPUID_7_0_EBX_MPX (1 << 14)
> #define CPUID_7_0_EBX_RDSEED (1 << 18)
> #define CPUID_7_0_EBX_ADX (1 << 19)
> #define CPUID_7_0_EBX_SMAP (1 << 20)
> @@ -695,6 +699,16 @@ typedef union {
> uint64_t q;
> } MMXReg;
>
> +typedef struct BNDReg {
> + uint64_t lb;
> + uint64_t ub;
> +} BNDReg;
> +
> +typedef struct BNDCSReg {
> + uint64_t cfg;
> + uint64_t sts;
> +} BNDCSReg;
> +
> #ifdef HOST_WORDS_BIGENDIAN
> #define XMM_B(n) _b[15 - (n)]
> #define XMM_W(n) _w[7 - (n)]
> @@ -912,6 +926,8 @@ typedef struct CPUX86State {
>
> uint64_t xstate_bv;
> XMMReg ymmh_regs[CPU_NB_REGS];
> + BNDReg bnd_regs[4];
> + BNDCSReg bndcs_regs;
>
> uint64_t xcr0;
>
> diff --git a/target-i386/kvm.c b/target-i386/kvm.c
> index 749aa09..347d3d3 100644
> --- a/target-i386/kvm.c
> +++ b/target-i386/kvm.c
> @@ -980,6 +980,8 @@ static int kvm_put_fpu(X86CPU *cpu)
> #define XSAVE_XMM_SPACE 40
> #define XSAVE_XSTATE_BV 128
> #define XSAVE_YMMH_SPACE 144
> +#define XSAVE_BNDREGS 240
> +#define XSAVE_BNDCSR 256
>
> static int kvm_put_xsave(X86CPU *cpu)
> {
> @@ -1012,6 +1014,10 @@ static int kvm_put_xsave(X86CPU *cpu)
> *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
> memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
> sizeof env->ymmh_regs);
> + memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
> + sizeof env->bnd_regs);
> + memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
> + sizeof(env->bndcs_regs));
> r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
> return r;
> }
> @@ -1294,6 +1300,10 @@ static int kvm_get_xsave(X86CPU *cpu)
> env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
> memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
> sizeof env->ymmh_regs);
> + memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
> + sizeof env->bnd_regs);
> + memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
> + sizeof(env->bndcs_regs));
> return 0;
> }
>
> diff --git a/target-i386/machine.c b/target-i386/machine.c
> index e568da2..ca8be7d 100644
> --- a/target-i386/machine.c
> +++ b/target-i386/machine.c
> @@ -63,6 +63,36 @@ static const VMStateDescription vmstate_ymmh_reg = {
> #define VMSTATE_YMMH_REGS_VARS(_field, _state, _n, _v) \
> VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_ymmh_reg, XMMReg)
>
> +static const VMStateDescription vmstate_bnd_regs = {
> + .name = "bnd_regs",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .fields = (VMStateField []) {
> + VMSTATE_UINT64(lb, BNDReg),
> + VMSTATE_UINT64(ub, BNDReg),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +#define VMSTATE_BNDREG_VARS(_field, _state, _n, _v) \
> + VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_bnd_regs, BNDReg)
> +
> +static const VMStateDescription vmstate_bndcs_regs = {
> + .name = "bndcs_regs",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .fields = (VMStateField []) {
> + VMSTATE_UINT64(cfg, BNDCSReg),
> + VMSTATE_UINT64(sts, BNDCSReg),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +#define VMSTATE_BNDCSR_VARS(_field, _state, _v) \
> + VMSTATE_STRUCT(_field, _state, _v, vmstate_bndcs_regs, BNDCSReg)
> +
> static const VMStateDescription vmstate_mtrr_var = {
> .name = "mtrr_var",
> .version_id = 1,
> @@ -606,6 +636,8 @@ const VMStateDescription vmstate_x86_cpu = {
> VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
> VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
> VMSTATE_YMMH_REGS_VARS(env.ymmh_regs, X86CPU, CPU_NB_REGS, 12),
> + VMSTATE_BNDREG_VARS(env.bnd_regs, X86CPU, 4, 12),
> + VMSTATE_BNDCSR_VARS(env.bndcs_regs, X86CPU, 12),
You need to put these two in a subsection, so that it is not emitted
when MPX is not enabled (i.e. when xstate_bv & (1<<3) == 0).
VMSTATE_BNDCSR_VARS doesn't need to be a separate struct, you can inline
bndcs_regs.cfs and bndcs_regs.sts directly in the subsection.
The rest looks good.
Paolo
> VMSTATE_END_OF_LIST()
> /* The above list is not sorted /wrt version numbers, watch out! */
> },
> -- 1.7.1 -- To unsubscribe from this list: send the line "unsubscribe
> kvm" in the body of a message to majordomo@vger.kernel.org More
> majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH v2 2/2] target-i386: Intel MPX
2013-12-04 17:23 ` Paolo Bonzini
@ 2013-12-05 15:26 ` Liu, Jinsong
2013-12-05 16:52 ` Paolo Bonzini
0 siblings, 1 reply; 6+ messages in thread
From: Liu, Jinsong @ 2013-12-05 15:26 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: qemu-devel@nongnu.org, Gleb Natapov, kvm
Paolo Bonzini wrote:
> Il 04/12/2013 12:30, Liu, Jinsong ha scritto:
>>>>
>>>> Almost there. Migration (vmstate) is still missing.
>>>>
>> Like this:
>>
>> ==================
>> From faead85c0dbe62da896e0ed9e165d98e10216968 Mon Sep 17 00:00:00
>> 2001
>> From: Liu Jinsong <jinsong.liu@intel.com>
>> Date: Wed, 4 Dec 2013 16:56:49 +0800
>> Subject: [PATCH 2/2] target-i386: Intel MPX
>>
>> Add some MPX related definiation, and hardcode sizes and offsets
>> of xsave features 3 and 4. It also add corresponding part to
>> kvm_get/put_xsave, and vmstate.
>>
>> Signed-off-by: Liu Jinsong <jinsong.liu@intel.com>
>> ---
>> target-i386/cpu.c | 4 ++++
>> target-i386/cpu.h | 22 +++++++++++++++++++---
>> target-i386/kvm.c | 10 ++++++++++
>> target-i386/machine.c | 32 ++++++++++++++++++++++++++++++++
>> 4 files changed, 65 insertions(+), 3 deletions(-)
>>
>> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
>> index 544b57f..52ca029 100644
>> --- a/target-i386/cpu.c
>> +++ b/target-i386/cpu.c
>> @@ -336,6 +336,10 @@ typedef struct ExtSaveArea {
>> static const ExtSaveArea ext_save_areas[] = {
>> [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
>> .offset = 0x240, .size = 0x100 },
>> + [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
>> + .offset = 0x3c0, .size = 0x40 },
>> + [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
>> + .offset = 0x400, .size = 0x10 },
>> };
>>
>> const char *get_register_name_32(unsigned int reg)
>> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
>> index ea373e8..5c1dd17 100644
>> --- a/target-i386/cpu.h
>> +++ b/target-i386/cpu.h
>> @@ -380,9 +380,12 @@
>>
>> #define MSR_VM_HSAVE_PA 0xc0010117
>>
>> -#define XSTATE_FP 1
>> -#define XSTATE_SSE 2
>> -#define XSTATE_YMM 4
>> +#define XSTATE_FP (1ULL << 0)
>> +#define XSTATE_SSE (1ULL << 1)
>> +#define XSTATE_YMM (1ULL << 2)
>> +#define XSTATE_BNDREGS (1ULL << 3)
>> +#define XSTATE_BNDCSR (1ULL << 4) +
>>
>> /* CPUID feature words */
>> typedef enum FeatureWord {
>> @@ -545,6 +548,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
>> #define CPUID_7_0_EBX_ERMS (1 << 9)
>> #define CPUID_7_0_EBX_INVPCID (1 << 10)
>> #define CPUID_7_0_EBX_RTM (1 << 11)
>> +#define CPUID_7_0_EBX_MPX (1 << 14)
>> #define CPUID_7_0_EBX_RDSEED (1 << 18)
>> #define CPUID_7_0_EBX_ADX (1 << 19)
>> #define CPUID_7_0_EBX_SMAP (1 << 20)
>> @@ -695,6 +699,16 @@ typedef union {
>> uint64_t q;
>> } MMXReg;
>>
>> +typedef struct BNDReg {
>> + uint64_t lb;
>> + uint64_t ub;
>> +} BNDReg;
>> +
>> +typedef struct BNDCSReg {
>> + uint64_t cfg;
>> + uint64_t sts;
>> +} BNDCSReg;
>> +
>> #ifdef HOST_WORDS_BIGENDIAN
>> #define XMM_B(n) _b[15 - (n)]
>> #define XMM_W(n) _w[7 - (n)]
>> @@ -912,6 +926,8 @@ typedef struct CPUX86State {
>>
>> uint64_t xstate_bv;
>> XMMReg ymmh_regs[CPU_NB_REGS];
>> + BNDReg bnd_regs[4];
>> + BNDCSReg bndcs_regs;
>>
>> uint64_t xcr0;
>>
>> diff --git a/target-i386/kvm.c b/target-i386/kvm.c
>> index 749aa09..347d3d3 100644
>> --- a/target-i386/kvm.c
>> +++ b/target-i386/kvm.c
>> @@ -980,6 +980,8 @@ static int kvm_put_fpu(X86CPU *cpu) #define
>> XSAVE_XMM_SPACE 40 #define XSAVE_XSTATE_BV 128
>> #define XSAVE_YMMH_SPACE 144
>> +#define XSAVE_BNDREGS 240
>> +#define XSAVE_BNDCSR 256
>>
>> static int kvm_put_xsave(X86CPU *cpu)
>> {
>> @@ -1012,6 +1014,10 @@ static int kvm_put_xsave(X86CPU *cpu)
>> *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV] = env->xstate_bv;
>> memcpy(&xsave->region[XSAVE_YMMH_SPACE], env->ymmh_regs,
>> sizeof env->ymmh_regs);
>> + memcpy(&xsave->region[XSAVE_BNDREGS], env->bnd_regs,
>> + sizeof env->bnd_regs);
>> + memcpy(&xsave->region[XSAVE_BNDCSR], &env->bndcs_regs,
>> + sizeof(env->bndcs_regs));
>> r = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave); return
>> r; }
>> @@ -1294,6 +1300,10 @@ static int kvm_get_xsave(X86CPU *cpu)
>> env->xstate_bv = *(uint64_t *)&xsave->region[XSAVE_XSTATE_BV];
>> memcpy(env->ymmh_regs, &xsave->region[XSAVE_YMMH_SPACE],
>> sizeof env->ymmh_regs);
>> + memcpy(env->bnd_regs, &xsave->region[XSAVE_BNDREGS],
>> + sizeof env->bnd_regs);
>> + memcpy(&env->bndcs_regs, &xsave->region[XSAVE_BNDCSR],
>> + sizeof(env->bndcs_regs));
>> return 0;
>> }
>>
>> diff --git a/target-i386/machine.c b/target-i386/machine.c
>> index e568da2..ca8be7d 100644
>> --- a/target-i386/machine.c
>> +++ b/target-i386/machine.c
>> @@ -63,6 +63,36 @@ static const VMStateDescription vmstate_ymmh_reg
>> = { #define VMSTATE_YMMH_REGS_VARS(_field, _state, _n, _v)
>> \ VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v,
>> vmstate_ymmh_reg, XMMReg)
>>
>> +static const VMStateDescription vmstate_bnd_regs = { + .name =
>> "bnd_regs", + .version_id = 1,
>> + .minimum_version_id = 1,
>> + .minimum_version_id_old = 1,
>> + .fields = (VMStateField []) {
>> + VMSTATE_UINT64(lb, BNDReg),
>> + VMSTATE_UINT64(ub, BNDReg),
>> + VMSTATE_END_OF_LIST()
>> + }
>> +};
>> +
>> +#define VMSTATE_BNDREG_VARS(_field, _state, _n, _v) \
>> + VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_bnd_regs,
>> BNDReg) + +static const VMStateDescription vmstate_bndcs_regs = { +
>> .name = "bndcs_regs", + .version_id = 1,
>> + .minimum_version_id = 1,
>> + .minimum_version_id_old = 1,
>> + .fields = (VMStateField []) {
>> + VMSTATE_UINT64(cfg, BNDCSReg),
>> + VMSTATE_UINT64(sts, BNDCSReg),
>> + VMSTATE_END_OF_LIST()
>> + }
>> +};
>> +
>> +#define VMSTATE_BNDCSR_VARS(_field, _state, _v) \
>> + VMSTATE_STRUCT(_field, _state, _v, vmstate_bndcs_regs,
>> BNDCSReg) + static const VMStateDescription vmstate_mtrr_var = {
>> .name = "mtrr_var", .version_id = 1,
>> @@ -606,6 +636,8 @@ const VMStateDescription vmstate_x86_cpu = {
>> VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
>> VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
>> VMSTATE_YMMH_REGS_VARS(env.ymmh_regs, X86CPU, CPU_NB_REGS,
>> 12), + VMSTATE_BNDREG_VARS(env.bnd_regs, X86CPU, 4, 12),
>> + VMSTATE_BNDCSR_VARS(env.bndcs_regs, X86CPU, 12),
>
> You need to put these two in a subsection, so that it is not emitted
> when MPX is not enabled (i.e. when xstate_bv & (1<<3) == 0).
> VMSTATE_BNDCSR_VARS doesn't need to be a separate struct, you can
> inline bndcs_regs.cfs and bndcs_regs.sts directly in the subsection.
>
> The rest looks good.
>
> Paolo
Sorry, those macro seems too opaque to me, I try several ways but fail.
Would you help me to add incremental patch based on current patches?
Thanks,
Jinsong
>
>> VMSTATE_END_OF_LIST()
>> /* The above list is not sorted /wrt version numbers, watch
>> out! */ }, -- 1.7.1 -- To unsubscribe from this list: send the
>> line "unsubscribe
>> kvm" in the body of a message to majordomo@vger.kernel.org More
>> majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH v2 2/2] target-i386: Intel MPX
2013-12-05 15:26 ` Liu, Jinsong
@ 2013-12-05 16:52 ` Paolo Bonzini
0 siblings, 0 replies; 6+ messages in thread
From: Paolo Bonzini @ 2013-12-05 16:52 UTC (permalink / raw)
To: Liu, Jinsong; +Cc: qemu-devel@nongnu.org, Gleb Natapov, kvm
Il 05/12/2013 16:26, Liu, Jinsong ha scritto:
> Sorry, those macro seems too opaque to me, I try several ways but fail.
> Would you help me to add incremental patch based on current patches?
Something like this (untested):
diff --git a/target-i386/machine.c b/target-i386/machine.c
index ca8be7d..71379b1 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -75,23 +75,8 @@ static const VMStateDescription vmstate_bnd_regs = {
}
};
-#define VMSTATE_BNDREG_VARS(_field, _state, _n, _v) \
- VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_bnd_regs, BNDReg)
-
-static const VMStateDescription vmstate_bndcs_regs = {
- .name = "bndcs_regs",
- .version_id = 1,
- .minimum_version_id = 1,
- .minimum_version_id_old = 1,
- .fields = (VMStateField []) {
- VMSTATE_UINT64(cfg, BNDCSReg),
- VMSTATE_UINT64(sts, BNDCSReg),
- VMSTATE_END_OF_LIST()
- }
-};
-
-#define VMSTATE_BNDCSR_VARS(_field, _state, _v) \
- VMSTATE_STRUCT(_field, _state, _v, vmstate_bndcs_regs, BNDCSReg)
+#define VMSTATE_BND_REGS(_field, _state, _n) \
+ VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_bnd_regs, BNDReg)
static const VMStateDescription vmstate_mtrr_var = {
.name = "mtrr_var",
@@ -536,6 +521,29 @@ static const VMStateDescription vmstate_msr_architectural_pmu = {
}
};
+static bool mpx_needed(void *opaque)
+{
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
+
} /* MISSING: Check for any MPX register != 0 here, return true if so. */
+ return false;
+}
+
+static const VMStateDescription vmstate_mpx = {
+ .name = "cpu/mpx",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_BND_REGS(env.bnd_regs, X86CPU, 4),
+ VMSTATE_UINT64(env.bndcs_regs.cfg, X86CPU),
+ VMSTATE_UINT64(env.bndcs_regs.sts, X86CPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
const VMStateDescription vmstate_x86_cpu = {
.name = "cpu",
.version_id = 12,
@@ -636,8 +642,6 @@ const VMStateDescription vmstate_x86_cpu = {
VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
VMSTATE_YMMH_REGS_VARS(env.ymmh_regs, X86CPU, CPU_NB_REGS, 12),
- VMSTATE_BNDREG_VARS(env.bnd_regs, X86CPU, 4, 12),
- VMSTATE_BNDCSR_VARS(env.bndcs_regs, X86CPU, 12),
VMSTATE_END_OF_LIST()
/* The above list is not sorted /wrt version numbers, watch out! */
},
@@ -670,6 +674,9 @@ const VMStateDescription vmstate_x86_cpu = {
.vmsd = &vmstate_msr_architectural_pmu,
.needed = pmu_enable_needed,
} , {
+ .vmsd = &vmstate_mpx,
+ .needed = mpx_needed,
+ } , {
/* empty */
}
}
This is the bulk of the required changes.
Also, env.bndcs_regs.cfg is really BNDCFGU and should be called cfgu; and
you need to save BNDCFGS too. This needs a small change above to vmstate_mpx,
and other changes in kvm_get_supported_msrs, kvm_get_msrs, kvm_put_msrs
and the CPUX86State struct.
Paolo
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2013-12-04 7:56 [Qemu-devel] [PATCH v2 2/2] target-i386: Intel MPX Liu, Jinsong
2013-12-04 8:52 ` Paolo Bonzini
2013-12-04 11:30 ` Liu, Jinsong
2013-12-04 17:23 ` Paolo Bonzini
2013-12-05 15:26 ` Liu, Jinsong
2013-12-05 16:52 ` Paolo Bonzini
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