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Sender: Richard Henderson <rth7680@gmail.com>
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Date: Thu, 05 Dec 2013 11:29:52 +1300
From: Richard Henderson <rth@twiddle.net>
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Subject: Re: [Qemu-devel] [PATCH v2 08/12] target-arm: A64: add support for
	B and BL insns
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To: Peter Maydell <peter.maydell@linaro.org>
Cc: Patch Tracking <patches@linaro.org>, Michael Matz <matz@suse.de>, Alexander Graf <agraf@suse.de>, QEMU Developers <qemu-devel@nongnu.org>, C Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Laurent Desnogues <laurent.desnogues@gmail.com>, "kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>

On 12/05/2013 11:14 AM, Peter Maydell wrote:
> On 4 December 2013 21:55, Richard Henderson <rth@twiddle.net> wrote:
>> On 12/05/2013 08:33 AM, Peter Maydell wrote:
>>> @@ -680,6 +720,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
>>>      dc->condjmp = 0;
>>>
>>>      dc->aarch64 = 1;
>>> +    dc->tmp_a64_count = 0;
>>>      dc->thumb = 0;
>>>      dc->bswap_code = 0;
>>>      dc->condexec_mask = 0;
>>
>> Still no initialization of ->tmp_a64[]?
> 
> It doesn't need initialization, does it? It's a static array, and we
> fill it as new temps are requested. So all we need to do is clear
> the count so it starts "empty". Or have I missed something?

Well, barring bugs, no.

But I suggested clearing to TCGV_UNUSED for --enable-tcg-debug at minimum so as
to catch those.


r~