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Sender: Richard Henderson <rth7680@gmail.com>
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Date: Fri, 06 Dec 2013 08:34:34 +1300
From: Richard Henderson <rth@twiddle.net>
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Subject: Re: [Qemu-devel] [PATCH v3 08/12] target-arm: A64: add support for
	B and BL insns
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To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: patches@linaro.org, Michael Matz <matz@suse.de>, C Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Laurent Desnogues <laurent.desnogues@gmail.com>, =?ISO-8859-1?Q?Alex_Benn=E9e?= <alex.bennee@linaro.org>, kvmarm@lists.cs.columbia.edu

On 12/06/2013 01:39 AM, Peter Maydell wrote:
> From: Alexander Graf <agraf@suse.de>
> 
> Implement the B and BL instructions (PC relative branches and calls).
> 
> For convenience in managing TCG temporaries which might be generated
> if a source register is the zero-register XZR, we provide a simple
> mechanism for creating a new temp which is automatically freed at the
> end of decode of the instruction.
> 
> Signed-off-by: Alexander Graf <agraf@suse.de>
> [claudio: renamed functions, adapted to new decoder layout]
> Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target-arm/translate-a64.c |   64 ++++++++++++++++++++++++++++++++++++++++++--
>  target-arm/translate.h     |    3 +++
>  2 files changed, 65 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~