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Sender: Richard Henderson <rth7680@gmail.com>
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Date: Fri, 06 Dec 2013 12:05:05 +1300
From: Richard Henderson <rth@twiddle.net>
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Subject: Re: [Qemu-devel] [PATCH 10/13] target-arm: A64: add support for
	bitfield insns
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To: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Cc: patches@linaro.org, Michael Matz <matz@suse.de>, Claudio Fontana <claudio.fontana@linaro.org>, Dirk Mueller <dmueller@suse.de>, Will Newton <will.newton@linaro.org>, Laurent Desnogues <laurent.desnogues@gmail.com>, =?ISO-8859-1?Q?Alex_Benn=E9e?= <alex.bennee@linaro.org>, kvmarm@lists.cs.columbia.edu, Christoffer Dall <christoffer.dall@linaro.org>

On 12/06/2013 10:51 AM, Peter Maydell wrote:
> From: Claudio Fontana <claudio.fontana@linaro.org>
> 
> This patch implements the C3.4.2 Bitfield instructions:
> SBFM, BFM, UBFM.
> 
> Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target-arm/translate-a64.c |   54 ++++++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 52 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <rth@twiddle.net>

> +    if (opc != 1) { /* SBFM or UBFM */
> +        tcg_gen_movi_i64(tcg_rd, 0);
> +    }
> +
> +    /* do the bit move operation */
> +    if (si >= ri) {
> +        /* Wd<s-r:0> = Wn<s:r> */
> +        tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
> +        pos = 0;
> +        len = (si - ri) + 1;
> +    } else {
> +        /* Wd<32+s-r,32-r> = Wn<s:0> */
> +        pos = bitsize - ri;
> +        len = si + 1;
> +    }
> +
> +    tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
> +
> +    if (opc == 0) { /* SBFM - sign extend the destination field */
> +        tcg_gen_shli_i64(tcg_rd, tcg_rd, 64 - (pos + len));
> +        tcg_gen_sari_i64(tcg_rd, tcg_rd, 64 - (pos + len));
> +    }

OPTME: It's probably worth recognizing the common cases of ext{8,16,32}{u,s}.


r~